Micron technology, inc. (20240223196). DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE simplified abstract
Contents
DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE
Organization Name
Inventor(s)
Vijayakrishna J. Vankayala of Allen TX (US)
DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240223196 titled 'DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE
The memory device described in the patent application includes a clock input for receiving a clock signal from a host device, a command input for receiving command and address bits from the host device, and multiple die stacked in a three-dimensional stack.
- The first die in the stack contains memory cells and local control circuitry, including division circuitry that generates multiple clocks with lower frequencies from a divided clock received from the clock input.
- Transmitters in the memory device transmit the multiple clocks using inter-die interconnects between the stacked die.
Potential Applications: - This technology could be used in high-performance computing systems that require efficient clock distribution across multiple memory die. - It may find applications in data centers where fast and reliable memory access is crucial for processing large amounts of data.
Problems Solved: - Efficient clock distribution in stacked memory die. - Reduction of clock skew and latency in memory systems.
Benefits: - Improved performance and reliability in memory devices. - Enhanced scalability in multi-die memory architectures.
Commercial Applications: Title: "Advanced Clock Distribution Technology for High-Performance Memory Systems" This technology could be commercialized for use in servers, supercomputers, and other high-performance computing systems where fast and reliable memory access is essential.
Questions about the technology: 1. How does the division circuitry in the first die help in generating multiple clocks with lower frequencies?
- The division circuitry receives the clock signal from the clock input, divides it to generate a lower frequency clock, and then further divides it to create multiple clocks with even lower frequencies.
2. What are the advantages of using inter-die interconnects for transmitting clocks between stacked memory die?
- Inter-die interconnects help in reducing clock skew and latency, ensuring synchronized operation of the memory devices.
Original Abstract Submitted
a memory device includes a clock input configured to receive a clock from a host device. the memory device also includes a command input configured to receive command and address bits from the host device. the memory device further includes multiple die stacked in a three-dimensional stack. a first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. the first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. the memory device also includes one or more transmitters configured to transmit the multiple clocks using inter-die interconnects between the multiple die.
