Micron technology, inc. (20240203481). DECODING ARCHITECTURE FOR MEMORY DEVICES simplified abstract
Contents
DECODING ARCHITECTURE FOR MEMORY DEVICES
Organization Name
Inventor(s)
Paolo Fantini of Vimercate (IT)
Lorenzo Fratin of Buccinasco (IT)
Fabio Pellizzer of Boise ID (US)
DECODING ARCHITECTURE FOR MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240203481 titled 'DECODING ARCHITECTURE FOR MEMORY DEVICES
The patent application describes a decoding architecture for memory devices, specifically focusing on word line plates within a memory array.
- Word line plates in a memory array consist of a sheet of conductive material with a first portion extending in one direction and multiple fingers extending in another direction within the same plane.
- Two word line plates in the same plane can be activated using a shared electrode, allowing for efficient memory cell access.
- Memory cells connected to the word line plates sharing the electrode can represent a logical page for accessing memory cells.
- Memory cells can be accessed by applying different voltages to the word line plate and pillar electrode connected to the memory cell.
- The architecture enables parallel or simultaneous access operations for multiple memory cells within the same page of memory cells.
Potential Applications: - This technology can be applied in various memory devices such as solid-state drives, smartphones, and computers. - It can enhance the speed and efficiency of memory access in electronic devices.
Problems Solved: - Improves memory access efficiency and speed. - Enables simultaneous access to multiple memory cells within the same page.
Benefits: - Faster and more efficient memory access. - Enhanced performance of electronic devices.
Commercial Applications: Title: Advanced Memory Decoding Architecture for Enhanced Performance in Electronic Devices This technology can be utilized in the development of faster and more efficient memory devices, leading to improved performance in a wide range of electronic products. The market implications include increased demand for high-speed memory solutions in consumer electronics, data centers, and other industries.
Questions about Memory Decoding Architecture: 1. How does the shared electrode system improve memory access efficiency? The shared electrode system allows for the activation of multiple word line plates in the same plane, enabling faster and more efficient access to memory cells within a logical page.
2. What are the potential applications of this decoding architecture in the consumer electronics industry? This decoding architecture can be applied in various consumer electronics devices such as smartphones, tablets, and laptops to enhance memory access speed and overall performance.
Original Abstract Submitted
methods, systems, and devices for a decoding architecture for memory devices are described. word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. two word line plates in a same plane may be activated via a shared electrode. memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. a memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.
