Micron technology, inc. (20240192874). APPARATUSES AND METHODS FOR SHARED ROW AND COLUMN ADDRESS BUSES simplified abstract
Contents
APPARATUSES AND METHODS FOR SHARED ROW AND COLUMN ADDRESS BUSES
Organization Name
Inventor(s)
Hiroshi Akamatsu of Atlanta GA (US)
Reuben Pradhan of Atlanta GA (US)
APPARATUSES AND METHODS FOR SHARED ROW AND COLUMN ADDRESS BUSES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240192874 titled 'APPARATUSES AND METHODS FOR SHARED ROW AND COLUMN ADDRESS BUSES
The patent application describes apparatuses and methods for shared row and column address buses in a memory system. Row and column addresses are distributed along separate global buses in a central logic region of the memory, and then coupled through a shared address bus to a bank logic region.
- Row and column addresses are distributed along separate global buses in a central logic region of a memory.
- The row and column addresses are coupled through a shared address bus from the central logic region to a bank logic region.
- The row address may be provided along the shared address bus at a first time, and the column address may be provided at a second time.
Potential Applications: - Memory systems - Computer architecture - Data storage systems
Problems Solved: - Efficient distribution of row and column addresses in a memory system - Simplified address bus architecture
Benefits: - Improved memory access speed - Enhanced memory system performance - Reduced complexity in memory address distribution
Commercial Applications: Title: "Innovative Memory System Address Bus Architecture for Enhanced Performance" This technology can be applied in various commercial sectors such as: - Data centers - High-performance computing - Embedded systems
Questions about Shared Row and Column Address Buses: 1. How does the shared address bus architecture improve memory system performance?
- The shared address bus allows for efficient distribution of row and column addresses, reducing latency and improving overall memory access speed.
2. What are the potential challenges in implementing shared row and column address buses in memory systems?
- Some challenges may include ensuring proper synchronization of row and column addresses and managing the data flow through the shared address bus.
Original Abstract Submitted
apparatuses and methods for shared row and column address buses. row and column addresses are distributed along separate respective global buses in a central logic region of a memory. the row and column addresses are coupled through a shared address bus from the central logic region to a bank logic region. for example the row address may be provided along the shared address bus at a first time and the column address may be provided along the shared address bus at a second time.
