Micron technology, inc. (20240185935). BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK simplified abstract

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BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK

Organization Name

micron technology, inc.

Inventor(s)

Yu-Chung Lien of San Jose CA (US)

Zhenming Zhou of San Jose CA (US)

BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240185935 titled 'BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK

The patent application describes a system with a memory device and a processing device that can perform operations on a set of cells in a block of the memory device, which consists of multiple decks. The system determines if a second deck is physically below a first deck, where the first deck meets a functionality criterion but the second deck does not. If the second deck is below the first deck, the system performs a program operation on the cells using a higher voltage during a program verify phase.

  • The system can perform operations on cells in a memory device block with multiple decks.
  • It checks if a second deck is physically below a first deck that meets a functionality criterion.
  • If the second deck is below the first deck, a program operation is performed using a higher voltage.
  • This innovation allows for efficient and targeted programming of memory cells.

Potential Applications

This technology can be applied in various memory devices and storage systems where precise programming of cells is required.

Problems Solved

This system addresses the challenge of efficiently programming memory cells in a block with multiple decks, ensuring accurate and reliable operations.

Benefits

- Improved efficiency in programming memory cells - Enhanced reliability and accuracy in memory operations - Targeted programming based on deck criteria

Commercial Applications

Title: Advanced Memory Programming System This technology can be utilized in the development of high-performance memory devices for various industries, including data storage, telecommunications, and computing.

Prior Art

There may be existing technologies related to memory programming systems, but this specific approach of determining deck hierarchy and applying different voltages for programming may be novel.

Frequently Updated Research

Stay updated on advancements in memory programming systems and related technologies to enhance the efficiency and performance of memory devices.

Questions about Memory Programming Systems

Question 1

How does the system determine the hierarchy of decks in a memory block?

The system determines the hierarchy based on whether a second deck is physically below a first deck that meets specific functionality criteria.

Question 2

What are the potential implications of using different voltages for programming memory cells in terms of performance and reliability?

Using higher voltages for programming during a program verify phase can potentially improve the efficiency and accuracy of memory operations, leading to enhanced performance and reliability.


Original Abstract Submitted

a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells in the block using a first bitline voltage applied during a program verify phase, wherein the first bitline voltage is higher than a default program verify bitline voltage.