Micron technology, inc. (20240178189). APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES simplified abstract
Contents
- 1 APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 How does this technology compare to existing semiconductor packaging solutions in terms of performance and cost?
- 1.11 What are the specific design considerations for integrating multiple semiconductor dies on the front-side RDL structure?
- 1.12 Original Abstract Submitted
APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES
Organization Name
Inventor(s)
Shing-Yih Shih of New Taipei City (TW)
APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240178189 titled 'APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND EMBEDDED INTERCONNECT STRUCTURES
Simplified Explanation
The semiconductor package described in the abstract includes a resin molded package substrate with metal vias, front-side and back-side RDL structures, and a bridge TSV interconnect component embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure on the silicon substrate portion, and TSVs in the silicon substrate portion. Additionally, a first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure, and they are coplanar.
- Resin molded package substrate with metal vias
- Bridge TSV interconnect component with silicon substrate portion and TSVs
- Front-side and back-side RDL structures
- Mounting of first and second semiconductor dies on front-side RDL structure
Potential Applications
The technology described in this patent application could be applied in the semiconductor industry for advanced packaging solutions, such as in high-performance computing, data centers, and telecommunications.
Problems Solved
This technology addresses the need for improved interconnect solutions in semiconductor packages, offering enhanced performance and reliability for complex electronic systems.
Benefits
The benefits of this technology include increased integration density, improved signal integrity, and enhanced thermal management in semiconductor packages.
Potential Commercial Applications
The potential commercial applications of this technology could be in the development of advanced microprocessors, memory modules, and other high-speed electronic devices.
Possible Prior Art
One possible prior art for this technology could be the use of through-silicon vias (TSVs) in semiconductor packaging for vertical interconnects. Additionally, the integration of multiple semiconductor dies in a single package is a common practice in the industry.
Unanswered Questions
How does this technology compare to existing semiconductor packaging solutions in terms of performance and cost?
The article does not provide a direct comparison with existing semiconductor packaging solutions, so it is unclear how this technology stacks up in terms of performance and cost.
What are the specific design considerations for integrating multiple semiconductor dies on the front-side RDL structure?
The article mentions mounting a first and second semiconductor die on the front-side RDL structure, but it does not delve into the specific design considerations or challenges involved in this process.
Original Abstract Submitted
a semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side rdl structure, and a back-side rdl structure. a bridge tsv interconnect component is embedded in the resin molded core. the bridge tsv interconnect component has a silicon substrate portion, an rdl structure integrally constructed on the silicon substrate portion, and tsvs in the silicon substrate portion. a first semiconductor die and a second semiconductor die are mounted on the front-side rdl structure. the first semiconductor die and the second semiconductor die are coplanar.
