Micron technology, inc. (20240162156). REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY simplified abstract
Contents
- 1 REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY
Organization Name
Inventor(s)
Adam Thomas Barton of Boise ID (US)
REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240162156 titled 'REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY
Simplified Explanation
The patent application describes methods, systems, and devices for reducing resistivity for access lines in a memory array. A first metal layer is formed above a via that connects an access line of a memory array with a driver. The first metal layer is oxidized, and then a second metal layer is formed above the oxidized first metal layer. Access lines of the memory device are formed from the second metal layer, the oxidized first metal layer, or both.
- Formation of first metal layer above via
- Oxidation of first metal layer
- Formation of second metal layer above oxidized first metal layer
- Creation of access lines from second metal layer, oxidized first metal layer, or both
Potential Applications
The technology described in the patent application could be applied in the manufacturing of memory devices, such as DRAM or NAND flash memory, to improve the performance and reliability of access lines.
Problems Solved
This technology addresses the issue of resistivity in access lines of memory arrays, which can impact the speed and efficiency of data transfer within the memory device.
Benefits
- Improved conductivity of access lines - Enhanced performance and reliability of memory arrays - Potential cost savings in memory device manufacturing
Potential Commercial Applications
Optimizing Access Line Resistivity in Memory Arrays
Possible Prior Art
Prior art related to methods for reducing resistivity in access lines of memory arrays may include techniques for improving metal layer formation and oxidation processes.
Unanswered Questions
How does the oxidation of the first metal layer impact the overall conductivity of the access lines?
The patent application mentions the oxidation of the first metal layer, but does not provide specific details on how this process affects the conductivity of the access lines.
What are the specific memory array configurations that would benefit most from this technology?
While the patent application describes a general method for reducing resistivity in access lines, it does not specify which types of memory arrays or applications would see the greatest improvements from implementing this technology.
Original Abstract Submitted
methods, systems, and devices for reduced resistivity for access lines in a memory array are described. a first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. the first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. one or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.
