Micron Technology, Inc. patent applications published on September 5th, 2024

Summary of the patent applications from Micron Technology, Inc. on September 5th, 2024

1. 'Summary': Micron Technology, Inc. has recently filed patents for innovative memory cell structures, memory array designs, memory system reset technology, and advanced error correction technology for memory systems. These patents aim to enhance memory cell performance, improve data storage efficiency, optimize memory system communication, and ensure data integrity in memory systems.

2. 'Key Points of Patents':

• Memory Cell Structures: Support sidewall structures for memory cells in vertical structures, consisting of first electrode, second electrode, and self-selecting storage element with bulk and sidewall regions.
• Memory Array Design: Utilizes vertically-alternating tiers of insulative material and memory cells with transistors, capacitors, sense lines, capacitor-electrode structure, and access-line pillar.
• Memory System Reset Technology: Implements efficient reset techniques for protocol layers in memory systems to enhance system performance and reduce downtime for maintenance.
• Error Correction Technology: Utilizes ECC decoding to process data in memory components, constructing codewords, performing error correction, and enhancing data accuracy and system reliability.

3. 'Notable Applications':

• Memory cell structures can be used in memory storage devices, semiconductor industry, and data storage systems.
• Memory array design could find applications in electronic devices, data centers, and computing systems requiring high-density memory storage.
• Memory system reset technology can optimize memory system performance in data centers, servers, and networking equipment.
• Error correction technology is beneficial for data storage systems, communication systems, and information security applications.

Patent applications for Micron Technology, Inc. on September 5th, 2024

PERFORMANCE MANANGEMENT USING INTELLIGENT PRIORITIZATION OF MEMORY OPERATIONS (18593678)

Main Inventor

Lei PAN

MNAND FIELD TO PREDICT DEVICE PERFORMANCE (18590721)

Main Inventor

Gianluca Coppola

PROGRAM VOLTAGE SELECTION DURING ALL LEVELS PROGRAMMING OF A MEMORY DEVICE (18593779)

Main Inventor

Sheyang Ning

DYNAMIC MEMORY MANAGEMENT OPERATION (18604118)

Main Inventor

Xing Wang

MEDIA SCAN METHOD TO REDUCE ACTIVE IDLE POWER OF MEMORY DEVICES (18423272)

Main Inventor

Dengfeng Ruan

CONFIGURABLE MEMORY DIE CAPACITANCE (18604203)

Main Inventor

Jingwei Cheng

BAD BLOCK MAPPING BASED ON BAD BLOCK DISTRIBUTION IN A MEMORY SUB-SYSTEM (18587184)

Main Inventor

Dahai Tian

Network-Ready Storage Products with Computational Storage Processors (18646650)

Main Inventor

Luca Bert

MEMORY WITH EFFICIENT STORAGE OF EVENT LOG DATA (18646668)

Main Inventor

Steven Gaskill

MOBILE STORAGE RANDOM READ PERFORMANCE ESTIMATION ENHANCEMENTS (18647677)

Main Inventor

David Aaron Palmer

INTERLEAVED REED-SOLOMON (IRS) WITH COLLABORATIVE DECODING (18415627)

Main Inventor

Joseph M. MCCRATE

ACCESSING DATA USING ERROR CORRECTION OPERATION(S) TO REDUCE LATENCY AT A MEMORY SUB-SYSTEM (18655091)

Main Inventor

Vamsi Pavan Rayaprolu

MEMORY BANK PROTECTION (18660954)

Main Inventor

Paolo Amato

APPARATUSES AND METHODS FOR READ COMMANDS WITH DIFFERENT LEVELS OF ECC CAPABILITY (18588402)

Main Inventor

Sujeet Ayyapureddi

APPARATUSES AND METHODS FOR SELECTABLE EXPANSION OF ERROR CORRECTION CAPABILITY (18588373)

Main Inventor

Sujeet Ayyapureddi

MAPPING DESCRIPTORS FOR READ OPERATIONS (18602994)

Main Inventor

Xing Hui Duan

VOLTAGE-TRIGGERED PERFORMANCE THROTTLING (18441996)

Main Inventor

Hui Wang

PREDICTIVE CENTER ALLOCATION DATA STRUCTURE (18591851)

Main Inventor

Leon Zlotnik

COHERENT MEMORY ACCESS (18129559)

Main Inventor

Timothy P. Finkbeiner

NAMESPACE MAPPING STRUCTURAL ADJUSTMENT IN NON-VOLATILE MEMORY DEVICES (18659331)

Main Inventor

Alex Frolikov

CXL DRAM SWITCH FABRIC (18433191)

Main Inventor

Satheesh Babu MUTHUPANDI

PREDICTIVE CENTER ALLOCATION DATA STRUCTURE (18591906)

Main Inventor

Leon Zlotnik

DYNAMIC MACHINE READABLE CODE (18646934)

Main Inventor

Yashvi SINGH

DATA INTEGRITY IMPROVEMENT PROGRAMMING TECHNIQUES (18404587)

Main Inventor

Christopher Joseph Bueb

MEMORY BLOCK CHARACTERISTIC DETERMINATION (18659845)

Main Inventor

Zhongyuan Lu

READ DISTURB MITIGATION BASED ON SIGNAL AND NOISE CHARACTERISTICS OF MEMORY CELLS COLLECTED FOR READ CALIBRATION (18657672)

Main Inventor

Patrick Robert Khayat

TECHNIQUES FOR DETERMINING AN INTERFACE CONNECTION STATUS (18660002)

Main Inventor

Melissa I. Uribe

Methods of Forming Material Within Openings Extending into a Semiconductor Construction, and Semiconductor Constructions Having Fluorocarbon Material (18663364)

Main Inventor

Gurtej S. Sandhu

FLEXIBLE DESIGN AND PLACEMENT OF ALIGNMENT MARKS (18593504)

Main Inventor

Shruthi Kumara Vadivel

STACKED SEMICONDUCTOR DEVICE (18426271)

Main Inventor

Bharat Bhushan

Memory Cells and Integrated Assemblies having Charge-Trapping-Material with Trap-Enhancing-Additive (18658367)

Main Inventor

Manzar Siddik

LIGHT EMITTING DIODES AND ASSOCIATED METHODS OF MANUFACTURING (18664203)

Main Inventor

Scott D. Schellhammer

HETEROGENOUS INTERLEAVED REED-SOLOMON (HETIRS) WITH ERASURE DECODING (18415626)

Main Inventor

Joseph M. MCCRATE

RESET TECHNIQUES FOR PROTOCOL LAYERS OF A MEMORY SYSTEM (18590755)

Main Inventor

Junjun Wang

Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor ([[Micron Technology, Inc. (18647122). Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor simplified abstract|18647122]])

Main Inventor

Durai Vishak Nirmal Ramaswamy

SIDEWALL STRUCTURES FOR MEMORY CELLS IN VERTICAL STRUCTURES (18419190)

Main Inventor

Lorenzo Fratin