Micron Technology, Inc. patent applications published on September 12th, 2024
Summary of the patent applications from Micron Technology, Inc. on September 12th, 2024
1. **Summary**: Micron Technology, Inc. has recently filed patents for innovative semiconductor device stacking, advanced integrated circuit technology, memory module interfaces, and on-die inter-symbol interference prevention circuits. These patents introduce new methods for optimizing space utilization, improving electrical connectivity, enhancing system performance, and reducing interference in communication systems.
2. **Key Points of Patents**: - Staggered arrangement of semiconductor dies on a substrate with conductive structures for electrical coupling. - Integration of transistors, capacitors, and memory modules for enhanced performance in electronic devices. - Parallel alignment of memory modules to circuit boards for improved data transfer speeds and efficiency. - On-die ISI prevention circuit for managing inter-symbol interference in communication systems.
3. **Notable Applications**: - These technologies can be applied in various semiconductor devices, integrated circuits, memory modules, and high-speed communication systems. - Commercial applications include consumer electronics, telecommunications equipment, automotive electronics, data centers, and networking systems. - The innovations address challenges in space optimization, system performance, and signal integrity, benefiting a wide range of industries and applications.
Contents
- 1 Patent applications for Micron Technology, Inc. on September 12th, 2024
- 1.1 APPARATUS AND TEST ELEMENT GROUP (18441926)
- 1.2 PATTERN-BASED ACTIVATION OF MEMORY POWER CONSUMPTION MODE (18667548)
- 1.3 MEMORY MANAGEMENT (18657466)
- 1.4 ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS (18663978)
- 1.5 ADAPTIVE OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES (18666667)
- 1.6 PROTECTED VIRTUAL PARTITIONS IN NON-VOLATILE MEMORY STORAGE DEVICES WITH HOST-CONFIGURABLE ENDURANCE (18584635)
- 1.7 DEFERRED ZONE ADJUSTMENT IN ZONE MEMORY SYSTEM (18665196)
- 1.8 SINGLE-LEVEL CELL BLOCK STORING DATA FOR MIGRATION TO MULTIPLE MULTI-LEVEL CELL BLOCKS (18670006)
- 1.9 PLANE BALANCING IN A MEMORY SYSTEM (18651452)
- 1.10 MANAGING ADDRESS ACCESS INFORMATION (18608591)
- 1.11 MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GENERATION (18651590)
- 1.12 MEMORY DEVICE HAVING BONDED INTEGRATED CIRCUIT DIES USED FOR MULTIPLICATION (18423151)
- 1.13 MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING SETS OF FOUR MEMORY CELLS (18423168)
- 1.14 MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS HAVING DIFFERENT BIAS LEVELS BASED ON BIT SIGNIFICANCE (18423186)
- 1.15 DATA CACHING FOR FAST SYSTEM BOOT-UP (18609981)
- 1.16 MEMORY DIE FAULT DETECTION USING A CALIBRATION PIN (18584385)
- 1.17 ERROR CORRECTION MEMORY DEVICE WITH FAST DATA ACCESS (18604227)
- 1.18 DATA PROTECTION AND RECOVERY (18444523)
- 1.19 PARTIALLY PROGRAMMED BLOCK READ OPERATIONS (18591368)
- 1.20 MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING SETS OF TWO MEMORY CELLS (18423163)
- 1.21 TECHNIQUES TO CONFIGURE DRIVERS (18597576)
- 1.22 PRE-DECODER CIRCUITRY (18667802)
- 1.23 TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS (18604192)
- 1.24 ONE-LADDER READ OF MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED TWO-PASS DATA PROGRAMMING TECHNIQUES (18668021)
- 1.25 MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING LOGICAL STATES OF MEMORY CELLS (18423161)
- 1.26 MEMORY DEVICE FOR SUMMATION OF OUTPUTS OF SIGNED MULTIPLICATIONS (18423174)
- 1.27 MEMORY DEVICE FOR SIGNED MULTI-BIT TO MULTI-BIT MULTIPLICATIONS (18423178)
- 1.28 MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS WITH DIFFERENT THRESHOLDS BASED ON BIT SIGNIFICANCE (18423181)
- 1.29 PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY (18666063)
- 1.30 SEMICONDUCTOR ASSEMBLIES WITH RECESSED INDUCTORS, AND METHODS FOR MAKING THE SAME (18431817)
- 1.31 SEMICONDUCTOR DEVICES WITH FLEXIBLE REINFORCEMENT STRUCTURE (18668887)
- 1.32 MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICE PACKAGES AND ELECTRONIC SYSTEMS (18424693)
- 1.33 SEMICONDUCTOR DEVICE HAVING CONTACT PLUG CONNECTED TO DIFFUSION REGION (18441908)
- 1.34 MICROELECTRONIC DEVICES INCLUDING CONTACT STRUCTURES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS (18424704)
- 1.35 CONNECTOR ASSEMBLY WITH INTEGRATED DATA AND BACKUP ENERGY CONNECTIONS (18596264)
- 1.36 SECURE MEMORY SYSTEM PROGRAMMING FOR HOST DEVICE VERIFICATION (18665153)
- 1.37 APPARATUS WITH SPEED SELECTION MECHANISM AND METHOD FOR OPERATING (18584986)
- 1.38 INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS (18667116)
- 1.39 Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors (18666498)
- 1.40 STACKED SEMICONDUCTOR DEVICE (18426282)
Patent applications for Micron Technology, Inc. on September 12th, 2024
APPARATUS AND TEST ELEMENT GROUP (18441926)
Main Inventor
FUMIE UCHIDA
PATTERN-BASED ACTIVATION OF MEMORY POWER CONSUMPTION MODE (18667548)
Main Inventor
Tao Xiong
MEMORY MANAGEMENT (18657466)
Main Inventor
Horia C. Simionescu
ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS (18663978)
Main Inventor
Yu-Chung Lien
ADAPTIVE OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES (18666667)
Main Inventor
Jay Sarkar
PROTECTED VIRTUAL PARTITIONS IN NON-VOLATILE MEMORY STORAGE DEVICES WITH HOST-CONFIGURABLE ENDURANCE (18584635)
Main Inventor
Christopher Joseph BUEB
DEFERRED ZONE ADJUSTMENT IN ZONE MEMORY SYSTEM (18665196)
Main Inventor
Oyvind Hachre
SINGLE-LEVEL CELL BLOCK STORING DATA FOR MIGRATION TO MULTIPLE MULTI-LEVEL CELL BLOCKS (18670006)
Main Inventor
Johnny Au LAM
PLANE BALANCING IN A MEMORY SYSTEM (18651452)
Main Inventor
John J. Kane
MANAGING ADDRESS ACCESS INFORMATION (18608591)
Main Inventor
Keun Soo Song
MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GENERATION (18651590)
Main Inventor
Kishore Kumar Muchherla
MEMORY DEVICE HAVING BONDED INTEGRATED CIRCUIT DIES USED FOR MULTIPLICATION (18423151)
Main Inventor
Hernan Castro
MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING SETS OF FOUR MEMORY CELLS (18423168)
Main Inventor
Hernan Castro
MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS HAVING DIFFERENT BIAS LEVELS BASED ON BIT SIGNIFICANCE (18423186)
Main Inventor
Hernan Castro
DATA CACHING FOR FAST SYSTEM BOOT-UP (18609981)
Main Inventor
Francesco Basso
MEMORY DIE FAULT DETECTION USING A CALIBRATION PIN (18584385)
Main Inventor
Scott E. Schaefer
ERROR CORRECTION MEMORY DEVICE WITH FAST DATA ACCESS (18604227)
Main Inventor
Scott E. Schaefer
DATA PROTECTION AND RECOVERY (18444523)
Main Inventor
Joseph M. McCrate
PARTIALLY PROGRAMMED BLOCK READ OPERATIONS (18591368)
Main Inventor
Pitamber Shukla
MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING SETS OF TWO MEMORY CELLS (18423163)
Main Inventor
Hernan Castro
TECHNIQUES TO CONFIGURE DRIVERS (18597576)
Main Inventor
Martin Bach
PRE-DECODER CIRCUITRY (18667802)
Main Inventor
Jin Seung Son
TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS (18604192)
Main Inventor
Paolo Fantini
ONE-LADDER READ OF MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED TWO-PASS DATA PROGRAMMING TECHNIQUES (18668021)
Main Inventor
Phong Sy Nguyen
MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING LOGICAL STATES OF MEMORY CELLS (18423161)
Main Inventor
Hernan Castro
MEMORY DEVICE FOR SUMMATION OF OUTPUTS OF SIGNED MULTIPLICATIONS (18423174)
Main Inventor
Hernan Castro
MEMORY DEVICE FOR SIGNED MULTI-BIT TO MULTI-BIT MULTIPLICATIONS (18423178)
Main Inventor
Hernan Castro
MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS WITH DIFFERENT THRESHOLDS BASED ON BIT SIGNIFICANCE (18423181)
Main Inventor
Hernan Castro
PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY (18666063)
Main Inventor
Yu-Chung Lien
SEMICONDUCTOR ASSEMBLIES WITH RECESSED INDUCTORS, AND METHODS FOR MAKING THE SAME (18431817)
Main Inventor
Dustin L. Holloway
SEMICONDUCTOR DEVICES WITH FLEXIBLE REINFORCEMENT STRUCTURE (18668887)
Main Inventor
Owen R. Fay
MICROELECTRONIC DEVICES, AND RELATED MEMORY DEVICE PACKAGES AND ELECTRONIC SYSTEMS (18424693)
Main Inventor
Chin Hui Chong
SEMICONDUCTOR DEVICE HAVING CONTACT PLUG CONNECTED TO DIFFUSION REGION (18441908)
Main Inventor
MOEKO KAWANA
MICROELECTRONIC DEVICES INCLUDING CONTACT STRUCTURES, AND RELATED MEMORY DEVICES, AND ELECTRONIC SYSTEMS (18424704)
Main Inventor
Darwin A. Clampitt
CONNECTOR ASSEMBLY WITH INTEGRATED DATA AND BACKUP ENERGY CONNECTIONS (18596264)
Main Inventor
Mark A. Tverdy
SECURE MEMORY SYSTEM PROGRAMMING FOR HOST DEVICE VERIFICATION (18665153)
Main Inventor
Olivier Duval
APPARATUS WITH SPEED SELECTION MECHANISM AND METHOD FOR OPERATING (18584986)
Main Inventor
Chulkyu Lee
INTERFACES FOR COUPLING A MEMORY MODULE TO A CIRCUIT BOARD, AND ASSOCIATED DEVICES, MODULES, AND SYSTEMS (18667116)
Main Inventor
Anthony D. Veches
Integrated Components Which Have Both Horizontally-Oriented Transistors and Vertically-Oriented Transistors (18666498)
Main Inventor
Scott J. Derner
STACKED SEMICONDUCTOR DEVICE (18426282)
Main Inventor
Yeon Seung Jung
