Micron Technology, Inc. patent applications published on October 17th, 2024
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Contents
- 1 Patent applications for Micron Technology, Inc. on October 17th, 2024
- 1.1 DATA COMPRESSION FOR MAPPING TABLES (18610028)
- 1.2 MEMORY DEVICE LOG DATA STORAGE (18756399)
- 1.3 DYNAMIC WRITE SPEEDS FOR DATA PROGRAMMING (18603031)
- 1.4 DETECTION AND LATENCY REDUCTION OF WRITE-INTENSIVE PROCEDURES IN A MEMORY SYSTEM (18625007)
- 1.5 MEMORY SYSTEM PROCEDURE DETECTION AND LATENCY REDUCTION (18629685)
- 1.6 ADAPTIVE POLLING FOR HIGHER DENSITY STORAGE (18603033)
- 1.7 TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS (18638480)
- 1.8 HOST RECOVERY FOR A STUCK CONDITION (18638471)
- 1.9 INTELLIGENT PERFORMANCE MODE SELECTION TO MANAGE QUALITY OF SERVICE (18629767)
- 1.10 DYNAMICALLY ADJUSTING DATA READ SIZE (18630609)
- 1.11 IMPLICIT ORDERED COMMAND HANDLING (18646025)
- 1.12 DETERMINING AVAILABLE RESOURCES FOR STORING DATA (18644759)
- 1.13 READING SEQUENTIAL DATA USING MAPPING INFORMATION STORED AT A HOST DEVICE (18616970)
- 1.14 PRE-OPERATION FOR APPLICATION TO BOOST FIRMWARE PERFORMANCE (18626039)
- 1.15 DYNAMIC STATUS REGISTERS ARRAY (18633028)
- 1.16 MANAGING DATA INTEGRITY USING A CHANGE IN A NUMBER OF DATA ERRORS AND AN AMOUNT OF TIME IN WHICH THE CHANGE OCCURRED (18755592)
- 1.17 DECODER FOR BURST CORRECTION READ SOLOMON DECODING FOR MEMORY APPLICATIONS (18415634)
- 1.18 DYNAMIC PARITY SCHEME (18626135)
- 1.19 HARDWARE RESET MANAGEMENT FOR UNIVERSAL FLASH STORAGE (18638245)
- 1.20 MEMORY DEVICE HEALTH MONITORING LOGIC (18630614)
- 1.21 MEMORY SUB-SYSTEM LUN BYPASSING (18036781)
- 1.22 VIRTUAL INDEXING IN A MEMORY DEVICE (18037631)
- 1.23 TECHNIQUES FOR LOGICAL-TO-PHYSICAL INFORMATION COMPRESSION (18612896)
- 1.24 WEAR LEVELING TECHNIQUES USING DATA CHARACTERISTICS (18630915)
- 1.25 INTELLIGENT CONTENT MIGRATION WITH BORROWED MEMORY (18751020)
- 1.26 CACHE WITH SET ASSOCIATIVITY HAVING DATA DEFINED CACHE SETS (18748668)
- 1.27 ADDRESS SCRAMBLING BY LINEAR MAPS IN GALOIS FIELDS (18755382)
- 1.28 PARALLEL RAS CHANNELS IN CXL MEMORY DEVICE (18444550)
- 1.29 MANAGING ENCRYPTION KEYS PER LOGICAL BLOCK ON A PERSISTENT MEMORY DEVICE (18754830)
- 1.30 ARTIFICIAL NEURAL NETWORK TRAINING FOR MEAN TIME TO FAILURE PREDICTIONS (18632708)
- 1.31 SURVEILLANCE USING TRANSFER LEARNING OF A FEDERATED MODEL (18624754)
- 1.32 PULSE BASED MULTI-LEVEL CELL PROGRAMMING (18633362)
- 1.33 TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENT (18614244)
- 1.34 DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICES (18755033)
- 1.35 VARIABLE PAGE SIZE ARCHITECTURE (18617019)
- 1.36 Usage-Based Disturbance Counter Clearance (18628127)
- 1.37 Usage-Based Disturbance Mitigation (18624920)
- 1.38 APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSES (18629445)
- 1.39 DATA INPUT BUFFER WITH A BRANCHED DFE RESET PATH (18542581)
- 1.40 SOCKET DESIGN FOR A MEMORY DEVICE (18616989)
- 1.41 PERFORMING DATA INTEGRITY CHECKS TO IDENTIFY DEFECTIVE WORDLINES (18755062)
- 1.42 PERFORMING BLOCK-LEVEL MEDIA MANAGEMENT OPERATIONS FOR BLOCK STRIPES IN A MEMORY DEVICE (18755046)
- 1.43 MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES (18753717)
- 1.44 CENTRALIZED ERROR CORRECTION CIRCUIT (18647867)
- 1.45 INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST FOR MULTIPLE MEMORY DEVICE RANKS (18756406)
- 1.46 READ PASS VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING (18622190)
- 1.47 MEMORY DEVICE HEALTH MONITORING AND DYNAMIC ADJUSTMENT OF DEVICE PARAMETERS (18627984)
- 1.48 MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION (18753389)
- 1.49 THERMALLY REGULATED SEMICONDUCTOR DEVICE (18605034)
- 1.50 MEMORY DEVICE WITH LOW DENSITY THERMAL BARRIER (18640682)
- 1.51 METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING DIFFERENTLY SIZED CONDUCTIVE CONTACT STRUCTURES (18752525)
- 1.52 SUBSTRATE ALPHA PARTICLE SHIELD FOR SEMICONDUCTOR PACKAGES (18507801)
- 1.53 THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS (18751061)
- 1.54 APPARATUS INCLUDING STANDARD CELL (18604217)
- 1.55 METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (18619000)
- 1.56 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (18623552)
- 1.57 Memory Circuitry And Methods Used In Forming Memory Circuitry (18615110)
Patent applications for Micron Technology, Inc. on October 17th, 2024
DATA COMPRESSION FOR MAPPING TABLES (18610028)
Main Inventor
Deping He
MEMORY DEVICE LOG DATA STORAGE (18756399)
Main Inventor
Scheheresade VIRANI
DYNAMIC WRITE SPEEDS FOR DATA PROGRAMMING (18603031)
Main Inventor
Jameer Mulani
DETECTION AND LATENCY REDUCTION OF WRITE-INTENSIVE PROCEDURES IN A MEMORY SYSTEM (18625007)
Main Inventor
Yanhua Bi
MEMORY SYSTEM PROCEDURE DETECTION AND LATENCY REDUCTION (18629685)
Main Inventor
Yanhua Bi
ADAPTIVE POLLING FOR HIGHER DENSITY STORAGE (18603033)
Main Inventor
Jameer Mulani
TRANSISTOR CONFIGURATIONS FOR VERTICAL MEMORY ARRAYS (18638480)
Main Inventor
Ferdinando Bedeschi
HOST RECOVERY FOR A STUCK CONDITION (18638471)
Main Inventor
Deping He
INTELLIGENT PERFORMANCE MODE SELECTION TO MANAGE QUALITY OF SERVICE (18629767)
Main Inventor
Lei Pan
DYNAMICALLY ADJUSTING DATA READ SIZE (18630609)
Main Inventor
Wenjun Wu
IMPLICIT ORDERED COMMAND HANDLING (18646025)
Main Inventor
Huachen Li
DETERMINING AVAILABLE RESOURCES FOR STORING DATA (18644759)
Main Inventor
Roberto Izzi
READING SEQUENTIAL DATA USING MAPPING INFORMATION STORED AT A HOST DEVICE (18616970)
Main Inventor
Roberto Izzi
PRE-OPERATION FOR APPLICATION TO BOOST FIRMWARE PERFORMANCE (18626039)
Main Inventor
Zhengbo Wang
DYNAMIC STATUS REGISTERS ARRAY (18633028)
Main Inventor
Giuseppe Cariello
MANAGING DATA INTEGRITY USING A CHANGE IN A NUMBER OF DATA ERRORS AND AN AMOUNT OF TIME IN WHICH THE CHANGE OCCURRED (18755592)
Main Inventor
Ryan G. Fisher
DECODER FOR BURST CORRECTION READ SOLOMON DECODING FOR MEMORY APPLICATIONS (18415634)
Main Inventor
Joseph M. MCCRATE
DYNAMIC PARITY SCHEME (18626135)
Main Inventor
Gennaro Schettino
HARDWARE RESET MANAGEMENT FOR UNIVERSAL FLASH STORAGE (18638245)
Main Inventor
Luca Porzio
MEMORY DEVICE HEALTH MONITORING LOGIC (18630614)
Main Inventor
Scott E. Schaefer
MEMORY SUB-SYSTEM LUN BYPASSING (18036781)
Main Inventor
Meng Wei
VIRTUAL INDEXING IN A MEMORY DEVICE (18037631)
Main Inventor
Xiangang Luo
TECHNIQUES FOR LOGICAL-TO-PHYSICAL INFORMATION COMPRESSION (18612896)
Main Inventor
Daming Liu
WEAR LEVELING TECHNIQUES USING DATA CHARACTERISTICS (18630915)
Main Inventor
Giuseppe Cariello
INTELLIGENT CONTENT MIGRATION WITH BORROWED MEMORY (18751020)
Main Inventor
Kenneth Marion Curewitz
CACHE WITH SET ASSOCIATIVITY HAVING DATA DEFINED CACHE SETS (18748668)
Main Inventor
Steven Jeffrey Wallach
ADDRESS SCRAMBLING BY LINEAR MAPS IN GALOIS FIELDS (18755382)
Main Inventor
Marco Sforzin
PARALLEL RAS CHANNELS IN CXL MEMORY DEVICE (18444550)
Main Inventor
Nikesh AGARWAL
MANAGING ENCRYPTION KEYS PER LOGICAL BLOCK ON A PERSISTENT MEMORY DEVICE (18754830)
Main Inventor
Walter Andrew Hubis
ARTIFICIAL NEURAL NETWORK TRAINING FOR MEAN TIME TO FAILURE PREDICTIONS (18632708)
Main Inventor
Febin Sunny
SURVEILLANCE USING TRANSFER LEARNING OF A FEDERATED MODEL (18624754)
Main Inventor
Shashank Bangalore Lakshman
PULSE BASED MULTI-LEVEL CELL PROGRAMMING (18633362)
Main Inventor
Hernan A. Castro
TECHNIQUES TO MITIGATE MEMORY DIE MISALIGNMENT (18614244)
Main Inventor
Jie Yang
DETERMINING READ VOLTAGE OFFSET IN MEMORY DEVICES (18755033)
Main Inventor
Robert W. Mason
VARIABLE PAGE SIZE ARCHITECTURE (18617019)
Main Inventor
Corrado Villa
Usage-Based Disturbance Counter Clearance (18628127)
Main Inventor
Yang Lu
Usage-Based Disturbance Mitigation (18624920)
Main Inventor
Yang Lu
APPARATUSES AND METHODS FOR TRACKING WORD LINE ACCESSES (18629445)
Main Inventor
Yuan He
DATA INPUT BUFFER WITH A BRANCHED DFE RESET PATH (18542581)
Main Inventor
William Chad Waldrop
SOCKET DESIGN FOR A MEMORY DEVICE (18616989)
Main Inventor
Amitava Majumdar
PERFORMING DATA INTEGRITY CHECKS TO IDENTIFY DEFECTIVE WORDLINES (18755062)
Main Inventor
Jian Huang
PERFORMING BLOCK-LEVEL MEDIA MANAGEMENT OPERATIONS FOR BLOCK STRIPES IN A MEMORY DEVICE (18755046)
Main Inventor
Wei Wang
MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES (18753717)
Main Inventor
Mustafa N. Kaynak
CENTRALIZED ERROR CORRECTION CIRCUIT (18647867)
Main Inventor
Taeksang Song
INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST FOR MULTIPLE MEMORY DEVICE RANKS (18756406)
Main Inventor
Scott E. SCHAEFER
READ PASS VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING (18622190)
Main Inventor
Akira Goda
MEMORY DEVICE HEALTH MONITORING AND DYNAMIC ADJUSTMENT OF DEVICE PARAMETERS (18627984)
Main Inventor
Dongxiang Liao
MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION (18753389)
Main Inventor
Kishore Kumar Muchherla
THERMALLY REGULATED SEMICONDUCTOR DEVICE (18605034)
Main Inventor
Chen Yu Huang
MEMORY DEVICE WITH LOW DENSITY THERMAL BARRIER (18640682)
Main Inventor
Pengyuan Zheng
METHODS OF FORMING MICROELECTRONIC DEVICES INCLUDING DIFFERENTLY SIZED CONDUCTIVE CONTACT STRUCTURES (18752525)
Main Inventor
Lingyu Kong
SUBSTRATE ALPHA PARTICLE SHIELD FOR SEMICONDUCTOR PACKAGES (18507801)
Main Inventor
Chen-Yu HUANG
THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS (18751061)
Main Inventor
Jaspreet S. Gandhi
APPARATUS INCLUDING STANDARD CELL (18604217)
Main Inventor
Takamitsu Onda
METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (18619000)
Main Inventor
Fatma Arzum Simsek-Ege
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME (18623552)
Main Inventor
Naokazu Murata
Memory Circuitry And Methods Used In Forming Memory Circuitry (18615110)
Main Inventor
Yiping Wang
