Micron Technology, Inc. patent applications published on May 16th, 2024
Summary of the patent applications from Micron Technology, Inc. on May 16th, 2024
Micron Technology, Inc. has recently filed patents for innovative technologies in the field of microelectronics and semiconductor devices. These patents describe methods and structures aimed at improving the performance and efficiency of memory devices and vertical transistors. The technologies involve unique arrangements of conductive structures, sacrificial structures, and voids to enhance memory density, storage capacity, and data processing speeds. By utilizing specific annealing steps and innovative assembly designs, these patents address issues such as impurity concentration and memory cell performance, offering benefits such as enhanced reliability and improved device performance.
Notable Applications:
- Non-volatile memory devices
- High-density memory arrays
- Memory devices
- Electronic systems
- Semiconductor industry
- Electronics manufacturing
Contents
- 1 Patent applications for Micron Technology, Inc. on May 16th, 2024
- 1.1 SELECTIVELY USING HEROIC DATA RECOVERY METHODS IN A MEMORY DEVICE (18421389)
- 1.2 Methods and Apparatus for Characterizing Memory Devices (18420211)
- 1.3 NEURONAL TO MEMORY DEVICE COMMUNICATION (18498422)
- 1.4 APPARATUSES AND METHODS FOR SEPARATE WRITE ENABLE FOR SINGLE-PASS ACCESS OF DATA, METADATA, AND PARITY INFORMATION (18504362)
- 1.5 MEMORY CELL FOLDING OPERATIONS USING HOST SYSTEM MEMORY (18506874)
- 1.6 MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM (18419895)
- 1.7 DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS (18419846)
- 1.8 DYNAMICALLY ADJUSTING THE INITIAL POLLING TIMER IN MEMORY DEVICES (18382703)
- 1.9 TECHNIQUES FOR TEMPERATURE-BASED ACCESS OPERATIONS (18423002)
- 1.10 VARIABLE DENSITY STORAGE DEVICE (18492569)
- 1.11 Dynamic Virtual Channel Allocation for Time Sensitive Networking Bus (18492138)
- 1.12 RETRIEVAL OF LOG INFORMATION FROM A MEMORY DEVICE (18421861)
- 1.13 APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF (18504342)
- 1.14 DATA RECOVERY USING ORDERED DATA REQUESTS (18416967)
- 1.15 APPARATUSES AND METHODS FOR CONFIGURABLE ECC MODES (18504316)
- 1.16 QUALITY OF SERVICE MANAGEMENT IN A MEMORY SUB-SYSTEM (18388610)
- 1.17 INDEPENDENT FLASH TRANSLATION LAYER TABLES FOR MEMORY (18383746)
- 1.18 ARRAY ACCESS WITH RECEIVER MASKING (18419206)
- 1.19 PAGE REQUEST INTERFACE SUPPORT IN CACHING HOST MEMORY ADDRESS TRANSLATION DATA IN A MEMORY SUB-SYSTEM (18505302)
- 1.20 APPARATUS INCLUDING RECONFIGURABLE INTERFACE AND METHODS OF MANUFACTURING THE SAME (18421686)
- 1.21 Detection of Anomalous Sequences of Commands to Memory Systems (18487677)
- 1.22 USING MACHINE LEARNING TO IDENTIFY MEMORY COMPATIBILITY (18497642)
- 1.23 Image Data Storage and Processing for Preview with Fast and Smooth Transition (18491582)
- 1.24 DEFECT CHARACTERIZATION IN SEMICONDUCTOR DEVICES BASED ON IMAGE PROCESSING (18388623)
- 1.25 Quantization at Different Levels for Data Used in Artificial Neural Network Computations (18500672)
- 1.26 APPARATUSES AND METHODS FOR INPUT BUFFER DATA FEEDBACK EQUALIZATION CIRCUITS (18055588)
- 1.27 INTERNAL AND EXTERNAL DATA TRANSFER FOR STACKED MEMORY DIES (18407062)
- 1.28 Programmable Memory Timing (18420404)
- 1.29 DECODING ARCHITECTURE FOR WORD LINE TILES (18409397)
- 1.30 Integrated Assemblies (18415023)
- 1.31 MEMORY READ VOLTAGE THRESHOLD TRACKING BASED ON MEMORY DEVICE-ORIGINATED METRICS CHARACTERIZING VOLTAGE DISTRIBUTIONS (18507387)
- 1.32 MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST AND LATENT READ DISTURB (18505855)
- 1.33 TRIM SETTING DETERMINATION FOR A MEMORY DEVICE (18389140)
- 1.34 READ COMMAND FAULT DETECTION IN A MEMORY SYSTEM (18423059)
- 1.35 APPARATUSES AND METHODS FOR ENHANCED METADATA SUPPORT (18504215)
- 1.36 APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF (18504324)
- 1.37 APPARATUSES AND METHODS FOR SEPARATE WRITE ENABLE FOR SINGLE-PASS ACCESS OF DATA, METADATA, AND PARITY INFORMATION (18504353)
- 1.38 SEMICONDUCTOR DEVICE HAVING CONTACT PLUG (18054637)
- 1.39 REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY (18513303)
- 1.40 LOAD SWITCH MOUNTING FOR A SEMICONDUCTOR PACKAGE (18503560)
- 1.41 PASSIVE ELECTRONIC COMPONENTS ON A SEMICONDUCTOR DIE (18497637)
- 1.42 ELECTRONIC DEVICES COMPRISING A STACK STRUCTURE, A SOURCE CONTACT, AND A DIELECTRIC MATERIAL (18421820)
- 1.43 Programmable Spread Spectrum Signaling over a Pin of an Integrated Circuit Device (18403097)
- 1.44 Homomorphic Vigilance on Communication Channels (18488908)
- 1.45 MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS (18054291)
- 1.46 Integrated Assemblies and Methods of Forming Integrated Assemblies (18415928)
- 1.47 MEMORY STRUCTURES WITH VOIDS (18510464)
- 1.48 Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry (18522637)
Patent applications for Micron Technology, Inc. on May 16th, 2024
SELECTIVELY USING HEROIC DATA RECOVERY METHODS IN A MEMORY DEVICE (18421389)
Main Inventor
Curtis W. Egan
Methods and Apparatus for Characterizing Memory Devices (18420211)
Main Inventor
Jonathan D. Harms
NEURONAL TO MEMORY DEVICE COMMUNICATION (18498422)
Main Inventor
John D. Hopkins
APPARATUSES AND METHODS FOR SEPARATE WRITE ENABLE FOR SINGLE-PASS ACCESS OF DATA, METADATA, AND PARITY INFORMATION (18504362)
Main Inventor
Sujeet Ayyapureddi
MEMORY CELL FOLDING OPERATIONS USING HOST SYSTEM MEMORY (18506874)
Main Inventor
Ritesh Tiwari
MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM (18419895)
Main Inventor
Kishore Kumar Muchherla
DESCRAMBLING OF SCRAMBLED LINEAR CODEWORDS USING NON-LINEAR SCRAMBLERS (18419846)
Main Inventor
Patrick Robert Khayat
DYNAMICALLY ADJUSTING THE INITIAL POLLING TIMER IN MEMORY DEVICES (18382703)
Main Inventor
Kai Wen Wu
TECHNIQUES FOR TEMPERATURE-BASED ACCESS OPERATIONS (18423002)
Main Inventor
Olivier Duval
VARIABLE DENSITY STORAGE DEVICE (18492569)
Main Inventor
Christopher Joseph Bueb
Dynamic Virtual Channel Allocation for Time Sensitive Networking Bus (18492138)
Main Inventor
Poorna Kale
RETRIEVAL OF LOG INFORMATION FROM A MEMORY DEVICE (18421861)
Main Inventor
Shawn Storm
APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF (18504342)
Main Inventor
Sujeet Ayyapureddi
DATA RECOVERY USING ORDERED DATA REQUESTS (18416967)
Main Inventor
Tal Sharifie
APPARATUSES AND METHODS FOR CONFIGURABLE ECC MODES (18504316)
Main Inventor
Sujeet Ayyapureddi
QUALITY OF SERVICE MANAGEMENT IN A MEMORY SUB-SYSTEM (18388610)
Main Inventor
Raja V.S. Halaharivi
INDEPENDENT FLASH TRANSLATION LAYER TABLES FOR MEMORY (18383746)
Main Inventor
Marco Redaelli
ARRAY ACCESS WITH RECEIVER MASKING (18419206)
Main Inventor
Natalija Jovanovic
PAGE REQUEST INTERFACE SUPPORT IN CACHING HOST MEMORY ADDRESS TRANSLATION DATA IN A MEMORY SUB-SYSTEM (18505302)
Main Inventor
Raja V. S. Halaharivi
APPARATUS INCLUDING RECONFIGURABLE INTERFACE AND METHODS OF MANUFACTURING THE SAME (18421686)
Main Inventor
Won Joo Yun
Detection of Anomalous Sequences of Commands to Memory Systems (18487677)
Main Inventor
Saideep Tiku
USING MACHINE LEARNING TO IDENTIFY MEMORY COMPATIBILITY (18497642)
Main Inventor
Libo WANG
Image Data Storage and Processing for Preview with Fast and Smooth Transition (18491582)
Main Inventor
Saideep Tiku
DEFECT CHARACTERIZATION IN SEMICONDUCTOR DEVICES BASED ON IMAGE PROCESSING (18388623)
Main Inventor
Nagasubramaniyan Chandrasekaran
Quantization at Different Levels for Data Used in Artificial Neural Network Computations (18500672)
Main Inventor
Saideep Tiku
APPARATUSES AND METHODS FOR INPUT BUFFER DATA FEEDBACK EQUALIZATION CIRCUITS (18055588)
Main Inventor
KOHEI NAKAMURA
INTERNAL AND EXTERNAL DATA TRANSFER FOR STACKED MEMORY DIES (18407062)
Main Inventor
Kang-Yong Kim
Programmable Memory Timing (18420404)
Main Inventor
Kang-Yong Kim
DECODING ARCHITECTURE FOR WORD LINE TILES (18409397)
Main Inventor
Paolo Fantini
Integrated Assemblies (18415023)
Main Inventor
Yuan He
MEMORY READ VOLTAGE THRESHOLD TRACKING BASED ON MEMORY DEVICE-ORIGINATED METRICS CHARACTERIZING VOLTAGE DISTRIBUTIONS (18507387)
Main Inventor
Shantilal Rayshi Doru
MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST AND LATENT READ DISTURB (18505855)
Main Inventor
Nicola Ciocchini
TRIM SETTING DETERMINATION FOR A MEMORY DEVICE (18389140)
Main Inventor
Aswin Thiruvengadam
READ COMMAND FAULT DETECTION IN A MEMORY SYSTEM (18423059)
Main Inventor
Melissa I. Uribe
APPARATUSES AND METHODS FOR ENHANCED METADATA SUPPORT (18504215)
Main Inventor
Scott E. Smith
APPARATUSES AND METHODS FOR SINGLE-PASS ACCESS OF ECC INFORMATION, METADATA INFORMATION OR COMBINATIONS THEREOF (18504324)
Main Inventor
Scott E. Smith
APPARATUSES AND METHODS FOR SEPARATE WRITE ENABLE FOR SINGLE-PASS ACCESS OF DATA, METADATA, AND PARITY INFORMATION (18504353)
Main Inventor
Sujeet Ayyapureddi
SEMICONDUCTOR DEVICE HAVING CONTACT PLUG (18054637)
Main Inventor
KEIICHI TSUCHIYA
REDUCED RESISTIVITY FOR ACCESS LINES IN A MEMORY ARRAY (18513303)
Main Inventor
Lei Wei
LOAD SWITCH MOUNTING FOR A SEMICONDUCTOR PACKAGE (18503560)
Main Inventor
Seng Kim YE
PASSIVE ELECTRONIC COMPONENTS ON A SEMICONDUCTOR DIE (18497637)
Main Inventor
Kelvin Aik Boo TAN
ELECTRONIC DEVICES COMPRISING A STACK STRUCTURE, A SOURCE CONTACT, AND A DIELECTRIC MATERIAL (18421820)
Main Inventor
Michael A. Lindemann
Programmable Spread Spectrum Signaling over a Pin of an Integrated Circuit Device (18403097)
Main Inventor
Robert Richard Noel Bielby
Homomorphic Vigilance on Communication Channels (18488908)
Main Inventor
Saideep Tiku
MICROELECTRONIC DEVICES INCLUDING STAIRCASE STRUCTURES, RELATED MEMORY DEVICES, ELECTRONIC SYSTEMS, AND METHODS (18054291)
Main Inventor
Yuichi Yokoyama
Integrated Assemblies and Methods of Forming Integrated Assemblies (18415928)
Main Inventor
Jordan D. Greenlee
MEMORY STRUCTURES WITH VOIDS (18510464)
Main Inventor
Alessandro Calderoni
Vertical Transistor, Integrated Circuitry, Method Of Forming A Vertical Transistor, And Method Of Forming Integrated Circuitry (18522637)
Main Inventor
Hung-Wei Liu
