Micron Technology, Inc. patent applications published on July 25th, 2024
Summary of the patent applications from Micron Technology, Inc. on July 25th, 2024
1. **Summary**: Micron Technology, Inc. has recently filed patents for advanced transistor technology and memory storage technology. The transistor technology involves the formation of liners outside of channel material strings in two tiers to increase conductivity. On the other hand, the memory storage technology includes an integrated assembly with memory regions, conductive posts, and doped semiconductor material for improved performance and reliability.
2. **Key Points of Patents**: - Formation of liners outside of channel material strings in two tiers. - Creation of void spaces in the second tier. - Diffusion of dopants from conductively-doped semiconductive material into the channel material. - Integration of memory regions and conductive posts in a single assembly. - Use of channel-material pillars and conductive posts for electrical connections. - Direct adjacency of doped-semiconductor material to the source structure. - Liners for protection and insulation of the conductive posts.
3. **Notable Applications**: - Improved performance and reliability of integrated assemblies. - Simplified manufacturing processes. - Enhanced functionality of memory devices.
Contents
- 1 Patent applications for Micron Technology, Inc. on July 25th, 2024
- 1.1 ARTIFICIAL INTELLIGENCE-ENABLED ALARM FOR DETECTING PASSENGERS LOCKED IN VEHICLE (18628571)
- 1.2 PROGRAM PULSE MODIFICATION (18406852)
- 1.3 Solid State Drives Configurable to Use Storage Spaces of Remote Devices in Activities Involving Proof of Space (18624547)
- 1.4 DYNAMIC BLOCK CATEGORIZATION TO IMPROVE RELIABILITY AND PERFORMANCE IN MEMORY SUB-SYSTEM (18624657)
- 1.5 DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM (18406687)
- 1.6 VOLATILE MEMORY TO NON-VOLATILE MEMORY INTERFACE FOR POWER MANAGEMENT (18619046)
- 1.7 FIRMWARE POWER UP SEQUENCING IN MEMORY SUB-SYSTEMS (18627186)
- 1.8 LOW PASS THROUGH VOLTAGE ON LOWER TIER WORDLINES FOR READ DISTURB IMPROVEMENT (18412010)
- 1.9 Optimize Information Requests to a Memory System (18624796)
- 1.10 WORKLOAD-BASED SCAN OPTIMIZATION (18623881)
- 1.11 LOGICAL UNIT NUMBER QUEUES AND LOGICAL UNIT NUMBER QUEUE SCHEDULING FOR MEMORY DEVICES (18628060)
- 1.12 AUTOMOTIVE ELECTRONIC CONTROL UNIT PRE-BOOTING FOR IMPROVED MAN MACHINE INTERFACE PERFORMANCE (18628600)
- 1.13 ERROR TRACKING BY A MEMORY SYSTEM (18391371)
- 1.14 MEMORY SUB-SYSTEM WITH DYNAMIC CALIBRATION USING COMPONENT-BASED FUNCTION(S) (18585400)
- 1.15 SELECTABLE SIGNAL, LOGGING, AND STATE EXTRACTION (18627278)
- 1.16 APPARATUSES, SYSTEMS, AND METHODS FOR PER ROW ERROR SCRUB INFORMATION (18625539)
- 1.17 WRITE BUDGET CONTROL OF TIME-SHIFT BUFFER FOR STREAMING DEVICES (18624426)
- 1.18 RECALL PENDING CACHE LINE EVICTION (18591718)
- 1.19 DISTRIBUTED COMPUTING BASED ON MEMORY AS A SERVICE (18623794)
- 1.20 MEMORY SYSTEM FOR BINDING DATA TO A MEMORY NAMESPACE (18604086)
- 1.21 Current-Controlled Buffer Using Analog Bias (18506229)
- 1.22 Artificial Neural Network Computation using Integrated Circuit Devices having Analog Inference Capability (18601627)
- 1.23 AUTOMATIC GENERATION OF PROFILES BASED ON OCCUPANT IDENTIFICATION (18627188)
- 1.24 ARTIFICIAL INTELLIGENCE-BASED PERSISTENCE OF VEHICLE BLACK BOX DATA (18627233)
- 1.25 METHODS FOR TUNING COMMAND/ADDRESS BUS TIMING AND MEMORY DEVICES AND MEMORY SYSTEMS USING THE SAME (18623355)
- 1.26 MITIGATING DISTURBANCE OF DIGIT LINES AT PLATE EDGES (18405792)
- 1.27 REFRESHING A MEMORY DEVICE USING REAL-TIME CLOCK INFORMATION (18417818)
- 1.28 SYSTEMS AND METHODS FOR IMPROVED DUAL-TAIL LATCH WITH LOAD CONTROL (18506208)
- 1.29 ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES (18405049)
- 1.30 DRAIN-SIDE WORDLINE VOLTAGE BOOSTING TO REDUCE LATERAL ELECTRON FIELD DURING A PROGRAMMING OPERATION (18411532)
- 1.31 STORING ONE DATA VALUE BY PROGRAMMING A FIRST MEMORY CELL AND A SECOND MEMORY CELL (18601810)
- 1.32 DYNAMIC WORD LINE ALLOCATION IN MEMORY SYSTEMS (18417517)
- 1.33 APPARATUS AND INTERNAL VOLTAGE GENERATING CIRCUIT INCLUDING VOLTAGE DIVIDING CIRCUIT (18521490)
- 1.34 CHOPLESS FLOW FOR STAIRLESS ELECTRICAL INTERCONNECT STRUCTURE (18420074)
- 1.35 METHODS OF FORMING MICROELECTRONIC DEVICES (18623507)
- 1.36 Methods of Forming Conductive Pipes Between Neighboring Features, and Integrated Assemblies Having Conductive Pipes Between Neighboring Features (18594397)
- 1.37 SEMICONDUCTOR DEVICE HAVING DUTY-CYCLE CORRECTOR (18624648)
- 1.38 MANAGING ERROR CONTROL INFORMATION USING A REGISTER (18594795)
- 1.39 MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES (18623929)
- 1.40 NAND STAIRCASE LANDING PADS CONVERSION (18417709)
- 1.41 Integrated Assemblies and Methods of Forming Integrated Assemblies (18584275)
- 1.42 Integrated Assemblies and Methods of Forming Integrated Assemblies (18585372)
- 1.43 Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells (18597695)
- 1.44 MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND WRAPPED DATA LINE STRUCTURE (18623956)
Patent applications for Micron Technology, Inc. on July 25th, 2024
ARTIFICIAL INTELLIGENCE-ENABLED ALARM FOR DETECTING PASSENGERS LOCKED IN VEHICLE (18628571)
Main Inventor
Gil Golov
PROGRAM PULSE MODIFICATION (18406852)
Main Inventor
Lei Lin
Solid State Drives Configurable to Use Storage Spaces of Remote Devices in Activities Involving Proof of Space (18624547)
Main Inventor
Joseph Harold Steinmetz
DYNAMIC BLOCK CATEGORIZATION TO IMPROVE RELIABILITY AND PERFORMANCE IN MEMORY SUB-SYSTEM (18624657)
Main Inventor
Sandeep Reddy Kadasani
DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM (18406687)
Main Inventor
Yu-Chung LIEN
VOLATILE MEMORY TO NON-VOLATILE MEMORY INTERFACE FOR POWER MANAGEMENT (18619046)
Main Inventor
Shivam Swami
FIRMWARE POWER UP SEQUENCING IN MEMORY SUB-SYSTEMS (18627186)
Main Inventor
Ximin Shan
LOW PASS THROUGH VOLTAGE ON LOWER TIER WORDLINES FOR READ DISTURB IMPROVEMENT (18412010)
Main Inventor
Go Shikata
Optimize Information Requests to a Memory System (18624796)
Main Inventor
Trevor Conrad Meyerowitz
WORKLOAD-BASED SCAN OPTIMIZATION (18623881)
Main Inventor
Kishore Kumar Muchherla
LOGICAL UNIT NUMBER QUEUES AND LOGICAL UNIT NUMBER QUEUE SCHEDULING FOR MEMORY DEVICES (18628060)
Main Inventor
Shakeel Isamohiuddin BUKHARI
AUTOMOTIVE ELECTRONIC CONTROL UNIT PRE-BOOTING FOR IMPROVED MAN MACHINE INTERFACE PERFORMANCE (18628600)
Main Inventor
Gil Golov
ERROR TRACKING BY A MEMORY SYSTEM (18391371)
Main Inventor
Sai Krishna Mylavarapu
MEMORY SUB-SYSTEM WITH DYNAMIC CALIBRATION USING COMPONENT-BASED FUNCTION(S) (18585400)
Main Inventor
Gerald L. Cadloni
SELECTABLE SIGNAL, LOGGING, AND STATE EXTRACTION (18627278)
Main Inventor
Shawn Storm
APPARATUSES, SYSTEMS, AND METHODS FOR PER ROW ERROR SCRUB INFORMATION (18625539)
Main Inventor
Sujeet Ayyapureddi
WRITE BUDGET CONTROL OF TIME-SHIFT BUFFER FOR STREAMING DEVICES (18624426)
Main Inventor
Poorna Kale
RECALL PENDING CACHE LINE EVICTION (18591718)
Main Inventor
Dean E. Walker
DISTRIBUTED COMPUTING BASED ON MEMORY AS A SERVICE (18623794)
Main Inventor
Ameen D. Akel
MEMORY SYSTEM FOR BINDING DATA TO A MEMORY NAMESPACE (18604086)
Main Inventor
Samuel E. Bradshaw
Current-Controlled Buffer Using Analog Bias (18506229)
Main Inventor
Bhargav Kalva
Artificial Neural Network Computation using Integrated Circuit Devices having Analog Inference Capability (18601627)
Main Inventor
Poorna Kale
AUTOMATIC GENERATION OF PROFILES BASED ON OCCUPANT IDENTIFICATION (18627188)
Main Inventor
Robert Richard Noel Bielby
ARTIFICIAL INTELLIGENCE-BASED PERSISTENCE OF VEHICLE BLACK BOX DATA (18627233)
Main Inventor
Gil Golov
METHODS FOR TUNING COMMAND/ADDRESS BUS TIMING AND MEMORY DEVICES AND MEMORY SYSTEMS USING THE SAME (18623355)
Main Inventor
Eric J. Stave
MITIGATING DISTURBANCE OF DIGIT LINES AT PLATE EDGES (18405792)
Main Inventor
Makoto Kitagawa
REFRESHING A MEMORY DEVICE USING REAL-TIME CLOCK INFORMATION (18417818)
Main Inventor
Gianluca COPPOLA
SYSTEMS AND METHODS FOR IMPROVED DUAL-TAIL LATCH WITH LOAD CONTROL (18506208)
Main Inventor
Jinha Hwang
ELONGATED CAPACITORS IN 3D NAND MEMORY DEVICES (18405049)
Main Inventor
Yu-Chung Lien
DRAIN-SIDE WORDLINE VOLTAGE BOOSTING TO REDUCE LATERAL ELECTRON FIELD DURING A PROGRAMMING OPERATION (18411532)
Main Inventor
Vinh Quang Diep
STORING ONE DATA VALUE BY PROGRAMMING A FIRST MEMORY CELL AND A SECOND MEMORY CELL (18601810)
Main Inventor
Umberto Di Vincenzo
DYNAMIC WORD LINE ALLOCATION IN MEMORY SYSTEMS (18417517)
Main Inventor
Tarun Singh Yadav
APPARATUS AND INTERNAL VOLTAGE GENERATING CIRCUIT INCLUDING VOLTAGE DIVIDING CIRCUIT (18521490)
Main Inventor
KENICHI ECHIGOYA
CHOPLESS FLOW FOR STAIRLESS ELECTRICAL INTERCONNECT STRUCTURE (18420074)
Main Inventor
Surendranath C. Eruvuru
METHODS OF FORMING MICROELECTRONIC DEVICES (18623507)
Main Inventor
Shuangqiang Luo
Methods of Forming Conductive Pipes Between Neighboring Features, and Integrated Assemblies Having Conductive Pipes Between Neighboring Features (18594397)
Main Inventor
Ahmed Nayaz Noemaun
SEMICONDUCTOR DEVICE HAVING DUTY-CYCLE CORRECTOR (18624648)
Main Inventor
Yasuo Satoh
MANAGING ERROR CONTROL INFORMATION USING A REGISTER (18594795)
Main Inventor
Aaron P. Boehm
MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES (18623929)
Main Inventor
Kamal M. Karda
NAND STAIRCASE LANDING PADS CONVERSION (18417709)
Main Inventor
Mojtaba Asadirad
Integrated Assemblies and Methods of Forming Integrated Assemblies (18584275)
Main Inventor
Alyssa N. Scarbrough
Integrated Assemblies and Methods of Forming Integrated Assemblies (18585372)
Main Inventor
Alyssa N. Scarbrough
Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells (18597695)
Main Inventor
John D. Hopkins
MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND WRAPPED DATA LINE STRUCTURE (18623956)
Main Inventor
Kamal M. Karda
