Micron Technology, Inc. patent applications published on July 11th, 2024
Summary of the patent applications from Micron Technology, Inc. on July 11th, 2024
1. **Summary**: The recent patents filed by Micron Technology, Inc. focus on innovative techniques for memory cell protection, manufacturing 3D vertical arrays of memory cells, and modular die configurations for multi-channel memory. These patents aim to enhance memory cell reliability, performance, and density while streamlining manufacturing processes.
2. **Key Points of Patents**: - Techniques for reducing damage in memory cells during formation, particularly focusing on protecting sensitive regions of the cell structure. - Manufacturing 3D vertical arrays of memory cells using a series of steps involving dielectric material layers, conductive material, and chalcogenide material. - Modular die configurations for multi-channel memory, allowing for efficient operation and management of memory arrays.
3. **Notable Applications**: - Memory cell manufacturing processes. - Magnetic memory technologies. - Semiconductor industry. - Memory storage devices. - Data centers. - Consumer electronics. - IoT devices.
By implementing these patented technologies, Micron Technology, Inc. can lead advancements in the semiconductor market, offering more durable, efficient, and high-performance memory devices for various applications.
Contents
- 1 Patent applications for Micron Technology, Inc. on July 11th, 2024
- 1.1 POWER MANAGEMENT AND DELIVERY FOR HIGH BANDWIDTH MEMORY (18400614)
- 1.2 CLOCK PULSE MANAGEMENT TO REDUCE PEAK POWER LEVELS (18536694)
- 1.3 CLUSTER NAMESPACE FOR A MEMORY DEVICE (18048251)
- 1.4 MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL (18612028)
- 1.5 ADAPTIVE DIE SELECTION FOR BLOCK FAMILY SCAN (18403255)
- 1.6 MAXIMUM ROW ACTIVE TIME ENFORCEMENT FOR MEMORY DEVICES (18405998)
- 1.7 MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM (18402306)
- 1.8 SELF-OPTIMIZING CORRECTIVE READ OFFSETS WITH LATERAL CHARGE MIGRATION PROXIES (18407366)
- 1.9 APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME (18610770)
- 1.10 ADAPTIVE CONTROL FOR IN-MEMORY VERSIONING (17970132)
- 1.11 READ SOURCE DETERMINATION (18374982)
- 1.12 EMPTY PAGE SCAN OPERATIONS ADJUSTMENT (18617430)
- 1.13 CROSS-COMPARISON OF DATA COPY PAIRS DURING MEMORY DEVICE INITIALIZATION (18509587)
- 1.14 IDENTIFYING CENTER OF VALLEY IN MEMORY SYSTEMS (17972174)
- 1.15 STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL (18611094)
- 1.16 VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE (18616006)
- 1.17 SYSTEMS AND METHODS FOR CONTINUOUS IN-MEMORY VERSIONING (17972822)
- 1.18 COMMAND TIMER INTERRUPT (18048292)
- 1.19 WRITE OPERATIONS ON A NUMBER OF PLANES (18380895)
- 1.20 READ BUFFER ALLOCATION BALANCE BETWEEN MULTIPLE MEMORY DIES (18402573)
- 1.21 MANAGING RETENTION LATENCY FOR MEMORY DEVICES OF VEHICLE SYSTEMS (18405379)
- 1.22 SYSTEMS AND TECHNIQUES FOR TRANSFER OF DIRTY DATA (18520169)
- 1.23 MULTIPLANE DATA TRANSFER COMMANDS (18542388)
- 1.24 MEMORY SUB-SYSTEM COMMAND FENCING (18615760)
- 1.25 DYNAMIC RAIN FOR ZONED STORAGE SYSTEMS (18613950)
- 1.26 VECTOR INDEX REGISTERS (18612143)
- 1.27 SHADOW COMPUTATIONS IN BASE STATIONS (18612658)
- 1.28 PRIORITIZATION OF SUCCESSFUL READ RECOVERY OPERATIONS FOR A MEMORY DEVICE (18612210)
- 1.29 CLASSIFYING AN AREA AS HAZARDOUS OR NON-HAZARDOUS BASED ON AN OPERATION OF A SEMICONDUCTOR DEVICE (18405793)
- 1.30 COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN (18049454)
- 1.31 TECHNIQUES FOR IMPROVED DATA TRANSFER (18397889)
- 1.32 ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC (18611450)
- 1.33 COMMAND AND DATA PATH ERROR PROTECTION (18048283)
- 1.34 REDUNDANCY AND SWAPPING SCHEME FOR MEMORY REPAIR (18403198)
- 1.35 MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA (17972493)
- 1.36 ADJUSTABLE PERIODICITY OF BURST ACCESS OPERATIONS (18402566)
- 1.37 NETWORK CREDIT RETURN MECHANISMS (18610905)
- 1.38 DYNAMIC MACHINE READABLE CODE (18049435)
- 1.39 PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO SPIKING EVENTS, AND RELATED METHODS, SYSTEMS AND DEVICES (18582467)
- 1.40 FUSE DELAY OF A COMMAND IN A MEMORY PACKAGE (18615399)
- 1.41 MEMORY DEVICE HAVING SHARED READ/WRITE ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL (18615490)
- 1.42 APPARATUSES, SYSTEMS, AND METHODS FOR DATA TIMING ALIGNMENT WITH FAST ALIGNMENT MODE (18047950)
- 1.43 VOLTAGE REGULATOR SUPPLY FOR INDEPENDENT WORDLINE READS (18489454)
- 1.44 APPARATUS WITH MULTI-BIT CELL READ MECHANISM AND METHODS FOR OPERATING THE SAME (17970315)
- 1.45 POWER MANAGEMENT (18583066)
- 1.46 COMPACT DIGITAL THERMOMETER IN A MEMORY DEVICE (18489770)
- 1.47 MANAGING TRAP-UP IN A MEMORY SYSTEM (18393354)
- 1.48 SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM (18425383)
- 1.49 ASSOCIATIVE PROCESSING MEMORY SEQUENCE ALIGNMENT (18049498)
- 1.50 ASSOCIATIVE PROCESSING MEMORY SEQUENCE ALIGNMENT (18049506)
- 1.51 REDUCED PITCH MEMORY SUBSYSTEM FOR MEMORY DEVICE (18610267)
- 1.52 INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES (18616019)
- 1.53 SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHODS FOR ALIGNING DIES USING REGISTRATION MARKS (18614583)
- 1.54 STACKED MICROELECTRONIC PACKAGE WITH STACK MOUNTED COMPONENTS AND RELATED METHODS, DEVICES, AND SYSTEMS (18389613)
- 1.55 STACKED MICROELECTRONIC PACKAGES INCLUDING INTERPOSER STRUCTURES AND RELATED METHODS, DEVICES, AND SYSTEMS (18545996)
- 1.56 MICROELECTRONIC DEVICES INCLUDING CAPACITORS, AND RELATED ELECTRONIC SYSTEMS AND METHODS (18047978)
- 1.57 SOLID-STATE TRANSDUCER DEVICES WITH SELECTIVE WAVELENGTH REFLECTORS AND ASSOCIATED SYSTEMS AND METHODS (18444528)
- 1.58 ERROR PROTECTION FOR MANAGED MEMORY DEVICES (18048284)
- 1.59 Array Of Capacitors, Array Of Memory Cells, And Methods Used In Forming An Array Of Capacitors (18407675)
- 1.60 MICROELECTRONIC DEVICES WITH SOURCE REGION VERTICALLY BETWEEN TIERED DECKS, AND RELATED METHODS (18581667)
- 1.61 IMPROVED VERTICAL 3D MEMORY DEVICE AND ACCESSING METHOD (18407074)
- 1.62 ARCHITECTURE FOR MULTIDECK MEMORY ARRAYS (18617466)
- 1.63 TECHNIQUES FOR MODULAR DIE CONFIGURATIONS FOR MULTI-CHANNEL MEMORY (18400994)
- 1.64 THIN FILM TRANSISTORS AND RELATED FABRICATION TECHNIQUES (18417830)
- 1.65 METHOD FOR MANUFACTURING A MEMORY DEVICE AND MEMORY DEVICE MANUFACTURED THROUGH THE SAME METHOD (18615718)
- 1.66 CONFINED CELL STRUCTURES AND METHODS OF FORMING CONFINED CELL STRUCTURES (18615422)
Patent applications for Micron Technology, Inc. on July 11th, 2024
POWER MANAGEMENT AND DELIVERY FOR HIGH BANDWIDTH MEMORY (18400614)
Main Inventor
Rajesh H. Kariya
CLOCK PULSE MANAGEMENT TO REDUCE PEAK POWER LEVELS (18536694)
Main Inventor
Venkata Kiran Kumar Matturi
CLUSTER NAMESPACE FOR A MEMORY DEVICE (18048251)
Main Inventor
Gaurav SINHA
MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL (18612028)
Main Inventor
Tomoharu Tanaka
ADAPTIVE DIE SELECTION FOR BLOCK FAMILY SCAN (18403255)
Main Inventor
Kyungjin Kim
MAXIMUM ROW ACTIVE TIME ENFORCEMENT FOR MEMORY DEVICES (18405998)
Main Inventor
Donald M. Morgan
MANAGING ALLOCATION OF SUB-BLOCKS IN A MEMORY SUB-SYSTEM (18402306)
Main Inventor
Yu-Chung Lien
SELF-OPTIMIZING CORRECTIVE READ OFFSETS WITH LATERAL CHARGE MIGRATION PROXIES (18407366)
Main Inventor
Gianluca Nicosia
APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE SAME (18610770)
Main Inventor
Murong Lang
ADAPTIVE CONTROL FOR IN-MEMORY VERSIONING (17970132)
Main Inventor
David Andrew Roberts
READ SOURCE DETERMINATION (18374982)
Main Inventor
Tom V. Geukens
EMPTY PAGE SCAN OPERATIONS ADJUSTMENT (18617430)
Main Inventor
Peng Zhang
CROSS-COMPARISON OF DATA COPY PAIRS DURING MEMORY DEVICE INITIALIZATION (18509587)
Main Inventor
Angelo Covello
IDENTIFYING CENTER OF VALLEY IN MEMORY SYSTEMS (17972174)
Main Inventor
Kyungjin Kim
STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL (18611094)
Main Inventor
Eric N. Lee
VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE VOLTAGE (18616006)
Main Inventor
Kishore Kumar Muchherla
SYSTEMS AND METHODS FOR CONTINUOUS IN-MEMORY VERSIONING (17972822)
Main Inventor
Haojie Ye
COMMAND TIMER INTERRUPT (18048292)
Main Inventor
Chandrakanth Rapalli
WRITE OPERATIONS ON A NUMBER OF PLANES (18380895)
Main Inventor
Tom V. Geukens
READ BUFFER ALLOCATION BALANCE BETWEEN MULTIPLE MEMORY DIES (18402573)
Main Inventor
Wenjun Wu
MANAGING RETENTION LATENCY FOR MEMORY DEVICES OF VEHICLE SYSTEMS (18405379)
Main Inventor
Lei Pan
SYSTEMS AND TECHNIQUES FOR TRANSFER OF DIRTY DATA (18520169)
Main Inventor
Wenjun Wu
MULTIPLANE DATA TRANSFER COMMANDS (18542388)
Main Inventor
Giuseppe Cariello
MEMORY SUB-SYSTEM COMMAND FENCING (18615760)
Main Inventor
Dhawal Bavishi
DYNAMIC RAIN FOR ZONED STORAGE SYSTEMS (18613950)
Main Inventor
Luca Bert
VECTOR INDEX REGISTERS (18612143)
Main Inventor
Steven Jeffrey Wallach
SHADOW COMPUTATIONS IN BASE STATIONS (18612658)
Main Inventor
Dmitri Yudanov
PRIORITIZATION OF SUCCESSFUL READ RECOVERY OPERATIONS FOR A MEMORY DEVICE (18612210)
Main Inventor
Naveen BOLISETTY
CLASSIFYING AN AREA AS HAZARDOUS OR NON-HAZARDOUS BASED ON AN OPERATION OF A SEMICONDUCTOR DEVICE (18405793)
Main Inventor
Pavana Prakash
COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN (18049454)
Main Inventor
Melissa I. URIBE
TECHNIQUES FOR IMPROVED DATA TRANSFER (18397889)
Main Inventor
Jameer Mulani
ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC (18611450)
Main Inventor
Kishore Kumar Muchherla
COMMAND AND DATA PATH ERROR PROTECTION (18048283)
Main Inventor
Chandrakanth Rapalli
REDUNDANCY AND SWAPPING SCHEME FOR MEMORY REPAIR (18403198)
Main Inventor
Jaeil Kim
MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA (17972493)
Main Inventor
Christophe Vincent Antoine Laurent
ADJUSTABLE PERIODICITY OF BURST ACCESS OPERATIONS (18402566)
Main Inventor
Praveen Gurrala
NETWORK CREDIT RETURN MECHANISMS (18610905)
Main Inventor
Tony Brewer
DYNAMIC MACHINE READABLE CODE (18049435)
Main Inventor
Yashvi SINGH
PERFORMING PROCESSING-IN-MEMORY OPERATIONS RELATED TO SPIKING EVENTS, AND RELATED METHODS, SYSTEMS AND DEVICES (18582467)
Main Inventor
Dmitri Yudanov
FUSE DELAY OF A COMMAND IN A MEMORY PACKAGE (18615399)
Main Inventor
Christopher G. Wieduwilt
MEMORY DEVICE HAVING SHARED READ/WRITE ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL (18615490)
Main Inventor
Karthik Sarpatwari
APPARATUSES, SYSTEMS, AND METHODS FOR DATA TIMING ALIGNMENT WITH FAST ALIGNMENT MODE (18047950)
Main Inventor
BAOKANG WANG
VOLTAGE REGULATOR SUPPLY FOR INDEPENDENT WORDLINE READS (18489454)
Main Inventor
Federica Paolini
APPARATUS WITH MULTI-BIT CELL READ MECHANISM AND METHODS FOR OPERATING THE SAME (17970315)
Main Inventor
Matteo Impala'
POWER MANAGEMENT (18583066)
Main Inventor
Liang Yu
COMPACT DIGITAL THERMOMETER IN A MEMORY DEVICE (18489770)
Main Inventor
Chiara Cerafogli
MANAGING TRAP-UP IN A MEMORY SYSTEM (18393354)
Main Inventor
Pitamber Shukla
SELECTIVE DATA PATTERN WRITE SCRUB FOR A MEMORY SYSTEM (18425383)
Main Inventor
Zhongguang Xu
ASSOCIATIVE PROCESSING MEMORY SEQUENCE ALIGNMENT (18049498)
Main Inventor
Justin Eno
ASSOCIATIVE PROCESSING MEMORY SEQUENCE ALIGNMENT (18049506)
Main Inventor
Justin Eno
REDUCED PITCH MEMORY SUBSYSTEM FOR MEMORY DEVICE (18610267)
Main Inventor
Michael A. Smith
INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES (18616019)
Main Inventor
Kyle K. Kirby
SEMICONDUCTOR ASSEMBLIES WITH SYSTEM AND METHODS FOR ALIGNING DIES USING REGISTRATION MARKS (18614583)
Main Inventor
Shiro Uchiyama
STACKED MICROELECTRONIC PACKAGE WITH STACK MOUNTED COMPONENTS AND RELATED METHODS, DEVICES, AND SYSTEMS (18389613)
Main Inventor
Seng Kim Dalson Ye
STACKED MICROELECTRONIC PACKAGES INCLUDING INTERPOSER STRUCTURES AND RELATED METHODS, DEVICES, AND SYSTEMS (18545996)
Main Inventor
Seng Kim Dalson Ye
MICROELECTRONIC DEVICES INCLUDING CAPACITORS, AND RELATED ELECTRONIC SYSTEMS AND METHODS (18047978)
Main Inventor
Sanket S. Kelkar
SOLID-STATE TRANSDUCER DEVICES WITH SELECTIVE WAVELENGTH REFLECTORS AND ASSOCIATED SYSTEMS AND METHODS (18444528)
Main Inventor
Martin F. Schubert
ERROR PROTECTION FOR MANAGED MEMORY DEVICES (18048284)
Main Inventor
Chandrakanth Rapalli
Array Of Capacitors, Array Of Memory Cells, And Methods Used In Forming An Array Of Capacitors (18407675)
Main Inventor
Jordan D. Greenlee
MICROELECTRONIC DEVICES WITH SOURCE REGION VERTICALLY BETWEEN TIERED DECKS, AND RELATED METHODS (18581667)
Main Inventor
Darwin A. Clampitt
IMPROVED VERTICAL 3D MEMORY DEVICE AND ACCESSING METHOD (18407074)
Main Inventor
Paolo Fantini
ARCHITECTURE FOR MULTIDECK MEMORY ARRAYS (18617466)
Main Inventor
Riccardo Muzzetto
TECHNIQUES FOR MODULAR DIE CONFIGURATIONS FOR MULTI-CHANNEL MEMORY (18400994)
Main Inventor
James Brian Johnson
THIN FILM TRANSISTORS AND RELATED FABRICATION TECHNIQUES (18417830)
Main Inventor
Hernan A. Castro
METHOD FOR MANUFACTURING A MEMORY DEVICE AND MEMORY DEVICE MANUFACTURED THROUGH THE SAME METHOD (18615718)
Main Inventor
Paolo Fantini
CONFINED CELL STRUCTURES AND METHODS OF FORMING CONFINED CELL STRUCTURES (18615422)
Main Inventor
Jun Liu
