Micron Technology, Inc. patent applications published on February 15th, 2024
Jump to navigation
Jump to search
Contents
- 1 Patent applications for Micron Technology, Inc. on February 15th, 2024
- 1.1 SELECTIVELY USING HEROIC DATA RECOVERY METHODS IN A MEMORY DEVICE (17886987)
- 1.2 ADAPTIVE OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES (17884327)
- 1.3 SUSPENDING OPERATIONS OF A MEMORY SYSTEM (17884429)
- 1.4 WRITE QUALITY IN MEMORY SYSTEMS (17887258)
- 1.5 ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS (17888171)
- 1.6 SEQUENTIAL WRITE OPERATIONS USING MULTIPLE MEMORY DIES (17884422)
- 1.7 ADAPTIVE BITLINE VOLTAGE FOR MEMORY OPERATIONS (17888080)
- 1.8 BALANCED CODEWORDS FOR REDUCING A SELECTED STATE IN MEMORY CELLS (17887239)
- 1.9 COMPRESSION AND DECOMPRESSION OF TRIM DATA (17888309)
- 1.10 TEMPERATURE-DEPENDENT REFRESH OPERATIONS (17884278)
- 1.11 ASSIGNING BLOCKS OF MEMORY SYSTEMS (17887247)
- 1.12 RESUMING WRITE OPERATIONS AFTER SUSPENSION (17884441)
- 1.13 TECHNIQUES FOR STORING JOURNALING INFORMATION (17818920)
- 1.14 COMMAND SEQUENCE TO SUPPORT ADAPTIVE MEMORY SYSTEMS (17818922)
- 1.15 MEMORY SUB-SYSTEM TRANSFER QUEUE RETENTION (17887366)
- 1.16 CACHING FOR MULTIPLE-LEVEL MEMORY DEVICE (17888325)
- 1.17 COMMON RAIN BUFFER FOR MULTIPLE CURSORS (17887268)
- 1.18 REDUCING CRYPTOGRAPHIC UPDATE ERRORS IN MEMORY DEVICES USING CYCLICAL REDUNDANCY CHECKS (17887346)
- 1.19 ERROR-HANDLING MANAGEMENT DURING COPYBACK OPERATIONS IN MEMORY DEVICES (17884076)
- 1.20 MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY (17884432)
- 1.21 DYNAMIC PARITY SCHEME (17888299)
- 1.22 READ RECOVERY INCLUDING LOW-DENSITY PARITY-CHECK DECODING (17887813)
- 1.23 METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS (18383311)
- 1.24 REDUCING START UP TIMES IN DEVICE IDENTITY COMPOSITION ENGINE (DICE) DEVICES (17887330)
- 1.25 GENERATING ICE HAZARD MAP BASED ON WEATHER DATA TRANSMITTED BY VEHICLES (18495668)
- 1.26 CONFIGURABLE TYPES OF WRITE OPERATIONS (17818613)
- 1.27 SUB-WORD LINE DRIVER HAVING COMMON GATE BOOSTED VOLTAGE (17886217)
- 1.28 SYSTEMS AND METHODS FOR CONTROLLING COMMON MODE LEVEL FOR SENSE AMPLIFIER CIRCUITRY (17884261)
- 1.29 MODEL FOR PREDICTING MEMORY SYSTEM PERFORMANCE (17819567)
- 1.30 MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES BASED ON A SENSITIVITY METRIC (17884113)
- 1.31 ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS (17888225)
- 1.32 INDEPENDENT SENSING TIMES (17887348)
- 1.33 STORING BITS WITH CELLS IN A MEMORY DEVICE (17888298)
- 1.34 SCHEDULED INTERRUPTS FOR PEAK POWER MANAGEMENT TOKEN RING COMMUNICATION (18229249)
- 1.35 DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION (17819826)
- 1.36 MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES USING SEGMENTATION (17884107)
- 1.37 PROGRAMMABLE CHALCOGENIDE CAPACITORS (17884450)
- 1.38 SEMICONDUCTOR DEVICE INTERCONNECTS HAVING CONDUCTIVE ANNULUS-STABILIZED THROUGH-SILICON VIAS (17884468)
- 1.39 ELECTRONIC DEVICES INCLUDING STACKS INCLUDING CONDUCTIVE STRUCTURES ISOLATED BY SLOT STRUCTURES, AND RELATED SYSTEMS AND METHODS (17819538)
- 1.40 SPACER FOR CHIPS ON WAFER SEMICONDUCTOR DEVICE ASSEMBLIES (17888324)
- 1.41 THROUGH-SUBSTRATE CONNECTIONS FOR RECESSED SEMICONDUCTOR DIES (17884484)
- 1.42 SUBSTRATE FOR VERTICALLY ASSEMBLED SEMICONDUCTOR DIES (17884475)
- 1.43 SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTING (18486950)
- 1.44 THICK GATE OXIDE TRANSISTOR DEVICE AND METHOD (17883736)
- 1.45 FINFETS WITH REDUCED PARASITICS (17883919)
- 1.46 TECHNIQUES TO BALANCE LOG STRUCTURED MERGE TREES (17886865)
- 1.47 STRESS-RELEASING SOLDER MASK PATTERN FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS (17885338)
- 1.48 RECESSED CHANNEL FIN INTEGRATION (17886917)
- 1.49 MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS, AND METHODS OF FORMING THE SAME (17819575)
- 1.50 MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (18491711)
- 1.51 PILLAR AND WORD LINE PLATE ARCHITECTURE FOR A MEMORY ARRAY (17819569)
- 1.52 RANDOM NUMBER GENERATION BASED ON THRESHOLD VOLTAGE RANDOMNESS (17818617)
Patent applications for Micron Technology, Inc. on February 15th, 2024
SELECTIVELY USING HEROIC DATA RECOVERY METHODS IN A MEMORY DEVICE (17886987)
Main Inventor
Curtis W. Egan
ADAPTIVE OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES (17884327)
Main Inventor
Jay Sarkar
SUSPENDING OPERATIONS OF A MEMORY SYSTEM (17884429)
Main Inventor
David Aaron Palmer
WRITE QUALITY IN MEMORY SYSTEMS (17887258)
Main Inventor
Nitul Gohain
ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS (17888171)
Main Inventor
Yu-Chung Lien
SEQUENTIAL WRITE OPERATIONS USING MULTIPLE MEMORY DIES (17884422)
Main Inventor
Rakeshkumar Dayabhai Vaghasiya
ADAPTIVE BITLINE VOLTAGE FOR MEMORY OPERATIONS (17888080)
Main Inventor
Yu-Chung Lien
BALANCED CODEWORDS FOR REDUCING A SELECTED STATE IN MEMORY CELLS (17887239)
Main Inventor
Christophe Vincent Antoine Laurent
COMPRESSION AND DECOMPRESSION OF TRIM DATA (17888309)
Main Inventor
Reshmi Basu
TEMPERATURE-DEPENDENT REFRESH OPERATIONS (17884278)
Main Inventor
Martin Brox
ASSIGNING BLOCKS OF MEMORY SYSTEMS (17887247)
Main Inventor
Deping He
RESUMING WRITE OPERATIONS AFTER SUSPENSION (17884441)
Main Inventor
Amiya Banerjee
TECHNIQUES FOR STORING JOURNALING INFORMATION (17818920)
Main Inventor
Olivier Duval
COMMAND SEQUENCE TO SUPPORT ADAPTIVE MEMORY SYSTEMS (17818922)
Main Inventor
Deping He
MEMORY SUB-SYSTEM TRANSFER QUEUE RETENTION (17887366)
Main Inventor
Vinay Sandeep
CACHING FOR MULTIPLE-LEVEL MEMORY DEVICE (17888325)
Main Inventor
Reshmi Basu
COMMON RAIN BUFFER FOR MULTIPLE CURSORS (17887268)
Main Inventor
Rakeshkumar Dayabhai Vaghasiya
REDUCING CRYPTOGRAPHIC UPDATE ERRORS IN MEMORY DEVICES USING CYCLICAL REDUNDANCY CHECKS (17887346)
Main Inventor
Zhan Liu
ERROR-HANDLING MANAGEMENT DURING COPYBACK OPERATIONS IN MEMORY DEVICES (17884076)
Main Inventor
Patrick R. Khayat
MULTI-LAYER CODE RATE ARCHITECTURE FOR SPECIAL EVENT PROTECTION WITH REDUCED PERFORMANCE PENALTY (17884432)
Main Inventor
Kishore Kumar Muchherla
DYNAMIC PARITY SCHEME (17888299)
Main Inventor
Gennaro Schettino
READ RECOVERY INCLUDING LOW-DENSITY PARITY-CHECK DECODING (17887813)
Main Inventor
Prashant Parashari
METHOD OF NOTIFYING A PROCESS OR PROGRAMMABLE ATOMIC OPERATION TRAPS (18383311)
Main Inventor
Tony Brewer
REDUCING START UP TIMES IN DEVICE IDENTITY COMPOSITION ENGINE (DICE) DEVICES (17887330)
Main Inventor
Zhan Liu
GENERATING ICE HAZARD MAP BASED ON WEATHER DATA TRANSMITTED BY VEHICLES (18495668)
Main Inventor
Gil Golov
CONFIGURABLE TYPES OF WRITE OPERATIONS (17818613)
Main Inventor
Giuseppe Cariello
SUB-WORD LINE DRIVER HAVING COMMON GATE BOOSTED VOLTAGE (17886217)
Main Inventor
Tae H. Kim
SYSTEMS AND METHODS FOR CONTROLLING COMMON MODE LEVEL FOR SENSE AMPLIFIER CIRCUITRY (17884261)
Main Inventor
Ki-Jun Nam
MODEL FOR PREDICTING MEMORY SYSTEM PERFORMANCE (17819567)
Main Inventor
Vamsi Pavan Rayaprolu
MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES BASED ON A SENSITIVITY METRIC (17884113)
Main Inventor
Mustafa N. Kaynak
ADAPTIVE SENSING TIME FOR MEMORY OPERATIONS (17888225)
Main Inventor
Yu-Chung Lien
INDEPENDENT SENSING TIMES (17887348)
Main Inventor
Yu-Chung Lien
STORING BITS WITH CELLS IN A MEMORY DEVICE (17888298)
Main Inventor
Daniele Vimercati
SCHEDULED INTERRUPTS FOR PEAK POWER MANAGEMENT TOKEN RING COMMUNICATION (18229249)
Main Inventor
Jeremy Binfet
DETECTING A MEMORY WRITE RELIABILITY RISK WITHOUT USING A WRITE VERIFY OPERATION (17819826)
Main Inventor
Yu-Chung LIEN
MANAGING COMPENSATION FOR CELL-TO-CELL COUPLING AND LATERAL MIGRATION IN MEMORY DEVICES USING SEGMENTATION (17884107)
Main Inventor
Mustafa N. Kaynak
PROGRAMMABLE CHALCOGENIDE CAPACITORS (17884450)
Main Inventor
Hongmei Wang
SEMICONDUCTOR DEVICE INTERCONNECTS HAVING CONDUCTIVE ANNULUS-STABILIZED THROUGH-SILICON VIAS (17884468)
Main Inventor
Ren Yuan Huang
ELECTRONIC DEVICES INCLUDING STACKS INCLUDING CONDUCTIVE STRUCTURES ISOLATED BY SLOT STRUCTURES, AND RELATED SYSTEMS AND METHODS (17819538)
Main Inventor
Mark S. Swenson
SPACER FOR CHIPS ON WAFER SEMICONDUCTOR DEVICE ASSEMBLIES (17888324)
Main Inventor
Brandon P. Wirz
THROUGH-SUBSTRATE CONNECTIONS FOR RECESSED SEMICONDUCTOR DIES (17884484)
Main Inventor
Thiagarajan Raman
SUBSTRATE FOR VERTICALLY ASSEMBLED SEMICONDUCTOR DIES (17884475)
Main Inventor
Kunal R. Parekh
SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTING (18486950)
Main Inventor
Travis M. Jensen
THICK GATE OXIDE TRANSISTOR DEVICE AND METHOD (17883736)
Main Inventor
Bingwu Liu
FINFETS WITH REDUCED PARASITICS (17883919)
Main Inventor
Wenjun Li
TECHNIQUES TO BALANCE LOG STRUCTURED MERGE TREES (17886865)
Main Inventor
Alexander Tomlinson
STRESS-RELEASING SOLDER MASK PATTERN FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS (17885338)
Main Inventor
Kelvin Tan Aik Boo
RECESSED CHANNEL FIN INTEGRATION (17886917)
Main Inventor
Sangmin Hwang
MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS, AND METHODS OF FORMING THE SAME (17819575)
Main Inventor
Umberto Maria Meotto
MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS (18491711)
Main Inventor
Kunal R. Parekh
PILLAR AND WORD LINE PLATE ARCHITECTURE FOR A MEMORY ARRAY (17819569)
Main Inventor
Lorenzo Fratin
RANDOM NUMBER GENERATION BASED ON THRESHOLD VOLTAGE RANDOMNESS (17818617)
Main Inventor
Innocenzo Tortorelli
