Micron Technology, Inc. patent applications on September 5th, 2024
Patent Applications by Micron Technology, Inc. on September 5th, 2024
Micron Technology, Inc.: 36 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (10), G06F12/02 (6), G06F11/10 (6), H01L25/065 (2), H01L21/768 (2) G06F11/1044 (2), G06F12/0246 (2), G06F3/0655 (2), G06F3/0607 (1), G11C16/16 (1)
With keywords such as: memory, device, data, storage, include, performance, read, configured, cache, and block in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Lei PAN of Shanghai (CN) for micron technology, inc., Qi DONG of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0607
Abstract: exemplary methods, apparatuses, and systems include an update performance manager for controlling performance of a wireless update by adjusting prioritization of internal operations for a memory subsystem. the update performance manager receives a first notification representing an initialization of a file transfer that includes an update file from a host using wireless communication. the update performance manager enters an update mode by reducing a priority of at least one internal operation of the memory subsystem in response to the first notification. the update performance manager receives the update file. the update performance manager programs the update file to memory. the update performance manager receives a second notification being a completion of the file transfer. the update performance manager resetting the priority of the at least one internal operation of the memory subsystem to a default value in response to the second notification.
20240295965. MNAND FIELD TO PREDICT DEVICE PERFORMANCE_simplified_abstract_(micron technology, inc.)
Inventor(s): Gianluca Coppola of Liveri (IT) for micron technology, inc., Daniela Ruggeri of Torre Del Greco (IT) for micron technology, inc., Nicola Colella of Capodrise (IT) for micron technology, inc., Fabrizio Fiorenza of Giugliano in Campania (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: a memory device includes a memory array and a memory control unit. the memory array includes memory cells. the memory control unit is configured to calculate an amount of data that can be written by a host device to the memory device in a burst performance mode before changing to sustained performance mode; calculate an amount of data that can be written to the memory device in the sustained performance mode before changing to writing the memory according to a dirty performance mode; and provide results of the calculations to the host device.
Inventor(s): Sheyang Ning of San Jose CA (US) for micron technology, inc., Lawrence Celso Miranda of San Jose CA (US) for micron technology, inc., Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., Lee-eun Yu of San Jose CA (US) for micron technology, inc., Yeang Meng Hern of Singapore (SG) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: control logic in a memory device, identifies a set of a plurality of memory cells associated with a selected wordline to be programmed to respective programming levels during a program operation and causes a set of a plurality of pillars with which the set of the plurality of memory cells are associated to be boosted to respective pillar voltages corresponding to the respective programming levels. the control logic further causes a series of programming pulses to be applied to the selected wordline, wherein respective memory cells of the set of memory cells are programmed to each of the respective programming levels by each programming pulse in the series of programming pulses, wherein a first programming pulse in the series of programming pulses has a first magnitude, wherein a second programming pulse in the series of programming pulses has a second magnitude, and wherein the second magnitude of the second programming pulse is less than the first magnitude of the first programming pulse increased by a predefined pulse step amount.
20240295971. DYNAMIC MEMORY MANAGEMENT OPERATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Xing Wang of Shanghai (CN) for micron technology, inc., Liu Yang of Shanghai (CN) for micron technology, inc., Xiaolai Zhu of Shanghai (CN) for micron technology, inc., Bin Zhao of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0622
Abstract: methods, systems, and devices for dynamic memory management operation are described. a memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (slcs)). the memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes slcs after a memory management operation (e.g., a garbage collection operation). the memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes slcs or a third block that includes a second type of memory cells configured to store two or more bits of information.
Inventor(s): Dengfeng Ruan of Shanghai (CN) for micron technology, inc., Peng Fei of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: a method for reducing active idle power is a memory device includes incrementing, by a first processing device, a first counter when no read or write requests are received from a host system within a first predetermined period of time, and in response to determining that the first counter has reached a first predetermined threshold value, transitioning to a sleep mode. the method also includes incrementing, by a second processing device, a second counter when no read or write requests are received from the host system within a second predetermined period of time, and in response to determining that the second counter has reached a second predetermined threshold value, transitioning to the sleep mode.
20240295975. CONFIGURABLE MEMORY DIE CAPACITANCE_simplified_abstract_(micron technology, inc.)
Inventor(s): Jingwei Cheng of Shanghai (CN) for micron technology, inc., Cheng Zhang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06, G06F13/16, G11C7/10
CPC Code(s): G06F3/0629
Abstract: methods, systems, and devices for configurable memory die capacitance are described. a memory device may include a capacitive component, which may include one or more capacitors and associated switching components. the capacitive component may be coupled with an input/output (i/o) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the i/o pad via the switching components. switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the i/o pad. the capacitive component, i/o pad, and input buffer may be included in a same die of the memory device. in some cases, a configuration of the capacitive component may be based on signaling received from a host device.
Inventor(s): Dahai Tian of Shanghai (CN) for micron technology, inc., Jiankun Li of Guangdong (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a system includes a memory device having a plurality of memory dies and a processing device operatively coupled with the memory device. the processing device is to perform operations including identifying a first logical block stripe of the memory device. the first logical block stripe includes a first plurality of blocks of the memory device. the operations further include determining that the first logical block stripe belongs to a first group of logical block stripes of a plurality of logical block stripes of the memory device. the operations further include determining that a second logical block stripe including a second plurality of blocks belong to a second group of logical block stripes. the operations further include mapping a first block of the first plurality of blocks to the second logical block stripe. the first block satisfies an error condition.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a storage product manufactured as a component to be installed in a computing device to provide network storage services. the storage product has a network interface to receive storage access messages from a remote host system, a bus connector connectable via an external computer bus to an external local host system, a local storage device, and a computational storage processor. the storage product is configured to: separate the storage access messages into first messages, second messages, and third messages; provide the first messages to an external local host system to generate fourth messages; and provide the second messages to the computational storage processor to generate fifth messages. to implement network storage services provided via the network interface, the local storage device executes commands in the third messages, the fourth messages from the local host system, and the fifth messages from the computational storage processor.
Inventor(s): Steven Gaskill of Campbell CA (US) for micron technology, inc., Joe G. Mendes of Santa Cruz CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0655
Abstract: memory with efficient storage of event log data is disclosed herein. in one embodiment, a memory device includes a non-volatile memory subsystem storing a persistent event log file, and a volatile memory subsystem including a working buffer. the memory device is configured to write newly generated event log data of the memory device to the working buffer. the memory device is further configured to write the newly generated first event log data to a first subregion of the persistent event log file. the first subregion can be one of a plurality of subregions of the persistent event log file, and can correspond to an end of event log data stored to the persistent event log file. the volatile memory subsystem can be positioned inside or outside a controller operably connected to the non-volatile memory subsystem.
Inventor(s): David Aaron Palmer of Boise ID (US) for micron technology, inc., Xinghui Duan of Shanghai (CA) for micron technology, inc., Massimo Zucchinali of Torre Boldone (IT) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0659
Abstract: a computing system having a storage system that includes a storage device and a host device, where the host device is configured to issue memory access commands to the storage device. the computing system further includes a prediction system comprising processing circuitry that is configured to perform operations that cause the prediction system to identify one or more components of the storage system that limit random read performance of the storage system. the operations further cause the prediction system to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system. the operations additionally cause the prediction system to execute the model in a simulation of the storage system to generate a random read performance parameter for the storage system.
Inventor(s): Joseph M. MCCRATE of Boise ID (US) for micron technology, inc., Kirthi SHENOY of Boise ID (US) for micron technology, inc., Marco SFORZIN of Boise ID (US) for micron technology, inc., Brian M. TWAIT of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1044
Abstract: provided is a memory system comprising a plurality of memory components. the ecc decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ecc) decoding on the first and second codewords received read from the plurality of memory components wherein the ecc decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.
Inventor(s): Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Dung Viet Nguyen of San Jose CA (US) for micron technology, inc., Zixiang Loh of Folsom CA (US) for micron technology, inc., Sampath K. Ratnam of San Jose CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Thomas Herbert Lentz of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1044
Abstract: a request to access data programmed to a memory sub-system is received. a determination is made of whether a memory device that stores the data referenced by the request satisfies a weak memory device criterion in view of a quality rating for the device. in response to a determination that the memory device satisfies the weak memory device criterion, an error correction operation to access the data is performed in accordance with the request.
20240296094. MEMORY BANK PROTECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Paolo Amato of Treviglio (IT) for micron technology, inc., Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio (IT) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: systems, apparatuses, and methods related to memory bank protection are described. a quantity of errors within a single memory bank is determined and the determined quantity can be used to further determine whether to access other memory banks to correct the determined quantity. the memory bank protection described herein avoids a single memory bank of a memory die being a single point of failure (spof).
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1076
Abstract: apparatuses, systems, and methods for read commands with different levels of error correction code (ecc) capability. a memory receives a first type of read command and reads data with a first level of ecc and receives a second type of read command and reads the data with a second level of ecc. for example, single error correction (sec) may be used as part of the first type of read command and more errors may be detected/corrected as part of the second type of read command. a controller may read data using the first type of read command and if a signal is received indicating that an error was detected may read the data again using the second type of read command.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1096
Abstract: apparatuses, systems, and methods for selectable expansion of error correction capability. a memory includes an error correction code (ecc) circuit which generates a default number of parity bits based on written data, and uses those parity bits to correct error(s) in the data. a setting of the memory may specify some number of extra bits of parity. when enabled the ecc circuit may generate parity include the default parity and the extra parity. the default parity is stored in an ecc column plane. the extra parity is stored in the data column planes. when the extra parity is enabled, the ecc circuit may detect/correct more bits of error in the data.
20240296116. MAPPING DESCRIPTORS FOR READ OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Xing Hui Duan of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/128
CPC Code(s): G06F12/0238
Abstract: methods, systems, and devices for mapping descriptors for read operations are described. a memory device may include a first cache may include a mapping table between the logical addresses and the physical addresses, and a second cache may include one or more descriptors of one or more physical addresses of the memory array. a descriptor may include a starting logical address, a starting physical address, and a quantity of addresses in the descriptor, and may be configured to identify addresses or sets of address that are frequently accessed. when an access command (e.g., a read command) is received, the first cache may be queried and then the second cache may be queried (if there is a cache miss at the first cache). the physical address of the data of the memory array may be determined (and accessed) based on the descriptors stored in the second cache.
20240296117. VOLTAGE-TRIGGERED PERFORMANCE THROTTLING_simplified_abstract_(micron technology, inc.)
Inventor(s): Hui Wang of Shanghai (CN) for micron technology, inc., Minjian Wu of Zhejiang (CN) for micron technology, inc., Hongyan Li of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: exemplary methods, apparatuses, and systems include a performance throttling manager for controlling performance levels of a memory subsystem using input voltages. the performance throttling manager monitors input voltages to a memory device to determine a current input voltage value, while the memory device is operating at a first performance level. the performance throttling manager detects that the current input voltage value satisfies a threshold voltage value. the performance throttling manager selects a second performance level that is lower than the first performance level and throttles the performance of the memory device in response to detecting that the current input voltage value satisfies a threshold voltage value.
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/06
CPC Code(s): G06F12/0246
Abstract: an apparatus includes a memory resource configured to store data entries in data structures including a first data structure and a second data structure and a processing device coupled to the memory resources. the processing device is configured to determine a predicted address location in the first data structure for a data entry, determine an equivalent address location in the second data structure, and write the data entry to the equivalent address location in the second data structure.
20240296124. COHERENT MEMORY ACCESS_simplified_abstract_(micron technology, inc.)
Inventor(s): Timothy P. Finkbeiner of Boise ID (US) for micron technology, inc., Troy D. Larsen of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F12/0877
CPC Code(s): G06F12/0877
Abstract: apparatuses and methods related to providing coherent memory access. an apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. the first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. a second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.
Inventor(s): Alex Frolikov of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/1009
CPC Code(s): G06F12/1009
Abstract: a computer storage device having a host interface, a controller, non-volatile storage media, and firmware. the firmware instructs the controller to: allocate a named portion of the non-volatile storage device; generate, according to a first block size, first block-wise mapping data; translate, using the first block-wise mapping data, logical addresses defined in the named portion to logical addresses defined for the entire non-volatile storage media, which can then be further translated to physical addresses in a same way for all named portions; determine a second block size; generate, according to the second block size, second block-wise mapping data; translate, using the second block-wise mapping data, the logical addresses defined in the named portion to the logical addresses defined for the entire non-volatile storage media.
20240296136. CXL DRAM SWITCH FABRIC_simplified_abstract_(micron technology, inc.)
Inventor(s): Satheesh Babu MUTHUPANDI of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/42
CPC Code(s): G06F13/4221
Abstract: a system and method of using the system may comprise: a rack; a first rack server mounted within the rack; and a device including compute express link (cxl) switch fabric, processing circuitry operatively coupled to the cxl switch fabric, memory operatively coupled to the cxl switch fabric, and a chassis mounted within the rack, the chassis housing the cxl switch fabric, the processing circuitry, and the memory. the processing circuitry may be configured to control the cxl switch fabric to allocate or deallocate at least a portion of the memory to or from the rack server. the chassis may be arranged at a top of the rack. the processing circuitry may further be configured to control the cxl switch fabric to allocate or deallocate at least another portion of the memory to or from another rack server.
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc., Sureshkumar Shastry Vemuri of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F16/22, G06F12/02
CPC Code(s): G06F16/2272
Abstract: an apparatus includes a memory resource configured to store data entries in a data memory resource including a first data structure and a second data structure and a processing device coupled to the memory resource. the processing device is configured to determine a predicted address location in the first data structure, compare the predicted address location to at least one address threshold, alter the predicted address location to an altered predicted address location, determine an equivalent address location in a second data structure that is equivalent to the altered predicted address location, and write the data entry to the equivalent address location in the second data structure.
20240296304. DYNAMIC MACHINE READABLE CODE_simplified_abstract_(micron technology, inc.)
Inventor(s): Yashvi SINGH of Boise ID (US) for micron technology, inc., Diana Calhoun MAJERUS of Boise ID (US) for micron technology, inc., Kristina Lauren MING of Boise ID (US) for micron technology, inc., Maria Pat F. CHAVARRIA of Boise ID (US) for micron technology, inc.
IPC Code(s): G06K19/06, H04L9/08
CPC Code(s): G06K19/06037
Abstract: in some implementations, a server device may generate a machine readable code that conveys first information associated with a first entity. the server device may provide an indication of the machine readable code that indicates the first information. the server device may obtain a request to update information conveyed by the machine readable code, the request including an indication of at least one of the machine readable code or the first information. the server device may modify the first information conveyed by the machine readable code to second information, based on the request and based on authenticating the request, wherein the second information includes a first secure information layer indicating the first information and a second secure information layer indicating information indicated by the request. the server device may provide, to the communication device, an indication of at least one of the machine readable code or the second information.
Inventor(s): Christopher Joseph Bueb of Folsom CA (US) for micron technology, inc., Zheng Wang of Louisville CO (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/4096, G11C29/52
CPC Code(s): G11C11/40618
Abstract: methods, systems, and devices for data integrity improvement programming techniques are described. a memory system may be pre-programed with data prior to assembling the memory system, where assembling the memory system may adversely affect data integrity of a portion of the data. the data integrity of the portion of the data may be improved by programming additional data to the memory system or adjusting data characteristics associated with the portion of the data. the memory system may perform a start-up procedure in which the memory system may identify an indication to perform a refresh operation. the memory system may perform a refresh operation using the additional data programmed to the memory system or using the adjusted data characteristics to improve the data integrity of the portion of the data and mitigate performance issues otherwise associated with performing the refresh operation.
20240296892. MEMORY BLOCK CHARACTERISTIC DETERMINATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhongyuan Lu of Boise ID (US) for micron technology, inc., Niccolo' Righetti of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C7/04, G11C16/08, G11C16/26, G11C16/32
CPC Code(s): G11C16/16
Abstract: bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. if a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.
Inventor(s): Patrick Robert Khayat of San Diego CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., AbdelHakim S. Alhussien of San Jose CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G06F18/214, G06N20/00, G11C7/02, G11C16/10, G11C16/26, G11C16/30
CPC Code(s): G11C16/3431
Abstract: a memory device to perform a read disturb mitigation operation. for example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.
Inventor(s): Melissa I. Uribe of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G11C29/02, G11C11/4076, G11C11/4099, H03K19/20
CPC Code(s): G11C29/022
Abstract: methods, systems, and devices for techniques for determining an interface connection status are described. a system may include an interface between a host device and a memory device. the host device may transmit to the memory device first data in a pattern over a first set of transmission lines of the interface. the host device may also transmit to the memory device second data in the pattern over a second set of transmission lines of the interface. the memory device may compare the first data and the second data, and based on the comparison, send an indication of a connection status of the interface to the host device.
Inventor(s): Gurtej S. Sandhu of Boise ID (US) for micron technology, inc., Sony Varghese of Manchester-by-the-Sea MA (US) for micron technology, inc., John A. Smythe of Boise ID (US) for micron technology, inc., Hyun Sik Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/762, B29C35/08, B29C41/08, B29K83/00, B32B3/26, H01L21/02, H01L21/288, H01L21/32, H01L21/67, H01L21/768
CPC Code(s): H01L21/7624
Abstract: some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. some embodiments include methods of filling openings that extend into a semiconductor construction. the methods may include, for example, printing the material into the openings or pressing the material into the openings. the construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. in some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.
Inventor(s): Shruthi Kumara Vadivel of Boise ID (US) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc., Lance David Williamson of Boise ID (US) for micron technology, inc., Kaveri Jain of Hyderabad (IN) for micron technology, inc., Adam Lewis Olson of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/544, H01L21/308
CPC Code(s): H01L23/544
Abstract: a memory device can include a substrate and a first alignment mark embedded in the substrate. the first alignment mark can be configured to a reference for a patterned second masking layer which is different from a first masking layer deposited on the substrate, and onto which the second patterned masking layer is deposited. the first masking layer can be an opaque or semi-opaque sacrificial layer and a second alignment mark can comprise at least a portion of the first masking layer. a location of the second alignment mark can correspond to a particular structure location in the substrate. the patterned second masking layer can include an additional alignment mark that is spaced laterally apart from the second alignment mark and the patterned second masking layer can define one or more locations of one or more structural features in the substrate.
20240297149. STACKED SEMICONDUCTOR DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Bharat Bhushan of Taichung (TW) for micron technology, inc., Akshay N. Singh of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L21/56, H01L21/78, H01L23/00, H01L23/31, H01L25/00, H10B80/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor device assembly is provided. the semiconductor device assembly includes a logic die, a top memory die, and a one or more intermediate memory dies between the top memory die and the logic die. front sides of the one or more intermediate memory dies at which active circuitry is disposed face a front side of the top memory die. back sides of the one or more intermediate memory dies opposite the front sides face a back side of the logic die. in doing so, a cost-efficient, low-complexity semiconductor device can be assembled.
Inventor(s): Manzar Siddik of Boise ID (US) for micron technology, inc., Terry H. Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/792, G11C16/04, H01L29/423, H10B43/20, H10B43/30
CPC Code(s): H01L29/792
Abstract: some embodiments include a memory cell having charge-trapping-material between a semiconductor channel material and a gating region. the charge-trapping-material includes silicon, nitrogen and trap-enhancing-additive. the trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal. some embodiments include an integrated assembly having a stack of alternating first and second levels. the first levels include conductive structures and the second levels are insulative. channel-material-pillars extend through the stack. charge-trapping-regions are along the channel-material-pillars and are between the channel-material-pillars and the conductive structures. the charge-trapping-regions include a charge-trapping-material which contains silicon, nitrogen and trap-enhancing-additive. the trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal.
Inventor(s): Scott D. Schellhammer of Meridian ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc., Thomas Gehrke of Boise ID (US) for micron technology, inc., Zaiyuan Ren of Boise ID (US) for micron technology, inc., Anton J. De Villiers of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L33/24, H01L33/00, H01L33/16, H01L33/22, H01L33/32
CPC Code(s): H01L33/24
Abstract: light emitting diodes and associated methods of manufacturing are disclosed herein. in one embodiment, a light emitting diode (led) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. the semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. the second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.
Inventor(s): Joseph M. MCCRATE of Boise ID (US) for micron technology, inc., Kirthi SHENOY of Boise ID (US) for micron technology, inc., Marco SFORZIN of Boise ID (US) for micron technology, inc., Brian M. TWAIT of Boise ID (US) for micron technology, inc.
IPC Code(s): H03M13/37, G06F11/10, H03M13/15
CPC Code(s): H03M13/373
Abstract: provided is a memory system comprising a plurality of memory components. the ecc decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ecc) decoding on the first and second codewords received read from the plurality of memory components wherein the ecc decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.
Inventor(s): Junjun Wang of Shanghai (CN) for micron technology, inc., Zhanqiang Su of Shanghai (CN) for micron technology, inc.
IPC Code(s): H04L69/40, G06F11/14, H04L69/323, H04L69/324
CPC Code(s): H04L69/40
Abstract: methods, systems, and devices for reset techniques for protocol layers of a memory system are described. a communications link may be established between a host system and the memory system. in some examples, the communications link may be based on one or more first parameters associated with a first protocol layer and one or more second parameters associated with a second protocol layer. the system may support communication (e.g., from the host system to the memory system) of an indication to reset the communications link, and the host system, the memory system, or both may reset the one or more first parameters based on communicating the indication to reset the communications link. the host system and memory system may attempt to reestablish the communications link based on resetting the one or more first parameters and maintaining the one or more second parameters.
[[20240298451. Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor_simplified_abstract_(micron technology, inc.)]]
Inventor(s): Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B53/20, H01L21/02, H01L21/311, H01L21/768, H01L23/528, H01L27/06, H01L29/08, H01L29/10, H10B12/00, H10B41/27, H10B41/35, H10B41/41, H10B43/27, H10B43/35, H10B51/10, H10B51/20, H10B51/30, H10B53/10, H10B53/30
CPC Code(s): H10B53/20
Abstract: a memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. at least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. a capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. the first electrode is electrically coupled to the first source/drain region. a horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. a capacitor-electrode structure extends elevationally through the vertically-alternating tiers. individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. an access-line pillar extends elevationally through the vertically-alternating tiers. the gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. other embodiments, including method, are disclosed.
Inventor(s): Lorenzo Fratin of Buccinasco (MI) (IT) for micron technology, inc., Paolo Fantini of Vimercate (IT) for micron technology, inc., Enrico Varesi of Milano (MI) (IT) for micron technology, inc.
IPC Code(s): H10N70/00, G11C13/00, H01L25/065, H10B63/00
CPC Code(s): H10N70/8265
Abstract: methods, systems, and devices for techniques that support sidewall structures for memory cells in vertical structures are described. a memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. the self-selecting storage element may extend between the first electrode and the second electrode in a direction that is parallel with a plane defined by the substrate. the self-selecting storage element may also include a bulk region and a sidewall region. the bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. also, the sidewall region may extend between the first electrode and the second electrode.
Micron Technology, Inc. patent applications on September 5th, 2024
- Micron Technology, Inc.
- G06F3/06
- CPC G06F3/0607
- Micron technology, inc.
- CPC G06F3/0613
- CPC G06F3/0619
- CPC G06F3/0622
- CPC G06F3/0625
- G06F13/16
- G11C7/10
- CPC G06F3/0629
- CPC G06F3/064
- CPC G06F3/0655
- G06F12/02
- CPC G06F3/0659
- G06F11/10
- CPC G06F11/1044
- G06F11/07
- CPC G06F11/1068
- CPC G06F11/1076
- CPC G06F11/1096
- G06F12/128
- CPC G06F12/0238
- CPC G06F12/0246
- G06F12/06
- G06F12/0877
- CPC G06F12/0877
- G06F12/1009
- CPC G06F12/1009
- G06F13/42
- CPC G06F13/4221
- G06F16/22
- CPC G06F16/2272
- G06K19/06
- H04L9/08
- CPC G06K19/06037
- G11C11/406
- G11C11/4096
- G11C29/52
- CPC G11C11/40618
- G11C16/16
- G11C7/04
- G11C16/08
- G11C16/26
- G11C16/32
- CPC G11C16/16
- G11C16/34
- G06F18/214
- G06N20/00
- G11C7/02
- G11C16/10
- G11C16/30
- CPC G11C16/3431
- G11C29/02
- G11C11/4076
- G11C11/4099
- H03K19/20
- CPC G11C29/022
- H01L21/762
- B29C35/08
- B29C41/08
- B29K83/00
- B32B3/26
- H01L21/02
- H01L21/288
- H01L21/32
- H01L21/67
- H01L21/768
- CPC H01L21/7624
- H01L23/544
- H01L21/308
- CPC H01L23/544
- H01L25/065
- H01L21/56
- H01L21/78
- H01L23/00
- H01L23/31
- H01L25/00
- H10B80/00
- CPC H01L25/0657
- H01L29/792
- G11C16/04
- H01L29/423
- H10B43/20
- H10B43/30
- CPC H01L29/792
- H01L33/24
- H01L33/00
- H01L33/16
- H01L33/22
- H01L33/32
- CPC H01L33/24
- H03M13/37
- H03M13/15
- CPC H03M13/373
- H04L69/40
- G06F11/14
- H04L69/323
- H04L69/324
- CPC H04L69/40
- H10B53/20
- H01L21/311
- H01L23/528
- H01L27/06
- H01L29/08
- H01L29/10
- H10B12/00
- H10B41/27
- H10B41/35
- H10B41/41
- H10B43/27
- H10B43/35
- H10B51/10
- H10B51/20
- H10B51/30
- H10B53/10
- H10B53/30
- CPC H10B53/20
- H10N70/00
- G11C13/00
- H10B63/00
- CPC H10N70/8265
