Micron Technology, Inc. patent applications on September 26th, 2024
Patent Applications by Micron Technology, Inc. on September 26th, 2024
Micron Technology, Inc.: 49 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (11), G11C13/00 (4), G11C7/10 (4), G06F12/02 (3), G06F11/10 (3) H01L23/5283 (2), G06F3/0611 (2), G11C7/1039 (2), G06F12/0246 (2), G06F3/0608 (1)
With keywords such as: memory, device, data, voltage, coupled, methods, configured, cells, based, and logic in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Raja V.S. Halaharivi of Gilroy CA (US) for micron technology, inc., Yoav Weinberg of Toronto (CA) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0608
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: detecting an asynchronous power loss event at the memory device; receiving, from a host system, a memory access command; determining that a size of the memory access command satisfies a threshold criterion, wherein the threshold criterion corresponds to an atomic write unit size; responsive to determining that the size of the memory access command satisfies the threshold criterion, executing the memory access command using a hardware component of the memory device; and responsive to executing the memory access command, notifying the host system of completion of execution of the memory access command.
20240319879. TUNED DATAPATH IN STACKED MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Hari Giduturi of Folsom CA (US) for micron technology, inc., Bret Addison Johnson of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/061
Abstract: a device includes a first memory die and a second memory die directly coupled to the first memory die via a first bus. the device also includes a second bus directly coupled to the first memory die. the first memory die includes a first trim circuit that when in operation adjusts a delay of signal transmission by the first memory die to a first value, while the second memory die comprises a second trim circuit that when in operation adjusts a delay of signal transmission by the second memory die to a second value.
Inventor(s): Rohit SEHGAL of Boise ID (US) for micron technology, inc., Vishal TANNA of Boise ID (US) for micron technology, inc., Krishna SIDDHAREDDY of Boise ID (US) for micron technology, inc., Eishan MIRAKHUR of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. the system also includes dynamic random-access memory (dram) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the dram and configured to control a transfer of information between the dram and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.
Inventor(s): Zhenming Zhou of San Jose CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that the wordline is disposed on a first deck of the memory deck; responsive to determining that the wordline is disposed on the first deck, determining that the wordline is associated with a first group of wordlines associated with the first deck; and responsive to determining that the wordline is associated with the first group of wordlines associated with the first deck, performing the memory access operation on the set of cells connected to the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the first group of wordlines associated with the first deck.
Inventor(s): Hua Tan of Shanghai (CN) for micron technology, inc., Lingye Zhou of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: methods, systems, and devices for two-stage buffer operations supporting write commands are described. if data is written to a memory device starting at a multi-plane page offset other than zero, the read performance for the data may decrease significantly due to die misalignment. to avoid die misalignment, a memory system may support two buffers for write data: a flush buffer and a temporary buffer. the memory system may determine whether to add received data to the flush buffer, the temporary buffer, or a combination thereof based on a data transfer size and a threshold size. if the data in the temporary buffer satisfies a copy condition, the data in the temporary buffer is copied into the flush buffer. if the data in the flush buffer satisfies a flush condition, the data in the flush buffer is written to the memory device starting at a multi-plane page offset of zero.
Inventor(s): Peng Zhang of Los Altos CA (US) for micron technology, inc., Lei Lin of Fremont CA (US) for micron technology, inc., Hanping Chen of San Jose CA (US) for micron technology, inc., Li-Te Chang of San Jose CA (US) for micron technology, inc., Zhengang Chen of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0614
Abstract: a method for receiving a request for performing a programming operation on one or more memory blocks of a memory device, identifying a value of a media endurance metric associated with the one or more memory blocks, determining a programming voltage offset corresponding to the value of the media endurance metric, and performing, using the programming voltage offset, the programming operation on the one or more memory blocks. the method further includes identifying a program-verify voltage level associated with the one or more memory blocks, determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric, and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.
Inventor(s): Rohit SEHGAL of Boise ID (US) for micron technology, inc., Vishal TANNA of Boise ID (US) for micron technology, inc., Krishna SIDDHAREDDY of Boise ID (US) for micron technology, inc., Eishan MIRAKHUR of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0634
Abstract: provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. the system also includes dynamic random-access memory (dram) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the dram and configured to control a transfer of information between the dram and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.
20240319899. ASSIGNING BLOCKS OF MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Caixia Yang of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: methods, systems, and devices for assigning blocks of memory systems are described. some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.
Inventor(s): David Matthew Springberg of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: various embodiments enable a memory sub-system to perform a read operation based on consolidated memory region description data, which can be generated based on a memory region description data (e.g., sgl) provided by a host system for the read operation.
Inventor(s): Sharath Chandra Ambula of Mancherial (IN) for micron technology, inc., Sushil Kumar of Hyderabad (IN) for micron technology, inc., Venkata Kiran Kumar Matturi of Khammam (IN) for micron technology, inc.
IPC Code(s): G06F3/06, G06F1/3234
CPC Code(s): G06F3/0656
Abstract: methods, systems, and devices for write buffer extensions for storage interface controllers are described. apparatuses and methods are presented in which a buffer may be used to temporarily store data from an application if the memory device is in an inactive power mode. this may allow the memory device to remain asleep. the buffer may be positioned on the host device so that the power mode of the memory device may not affect it. that way, data may be stored in the buffer without waking up the memory device. if the memory device is in an active power mode, the data that has been temporarily stored in the buffer may be sent to the memory device for storage. during read operations, if the requested data is stored in the buffer, it may be used instead of data in the memory device.
Inventor(s): Scheheresade VIRANI of Frisco TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: implementations described herein relate to memory device operations for unaligned write operations. in some implementations, a memory device may receive, from a host device, a write command indicating data having a first size that corresponds to a first write unit and a first logical address. the memory device may allocate a set of buffers for the write command. the memory device may determine a set of physical addresses corresponding to a physical address that is associated with the second size, where the set of physical addresses are each associated with the first size. the memory device may merge stored data from the set of physical addresses to one or more buffers, from the set of buffers, that do not include the data to generate a data unit having the second size. the memory device may write the data unit to memory indicated by the set of physical addresses.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F9/455
CPC Code(s): G06F9/45558
Abstract: a memory system includes a memory device and a processing device coupled to the memory device, the processing device is to create a namespace by allocating a reclaim group, the reclaim group comprising a plurality of reclaim units; assign a reclaim unit handle to the namespace; receive, from a virtual machine running on a host computing system, a command to perform an operation associated with the namespace; identify a segment of the memory device based on the reclaim unit handle that is assigned to the namespace; and perform the operation on the segment of the memory device.
Inventor(s): Charles See Yeung Kwong of Redwood City CA (US) for micron technology, inc., Seungjune Jeon of Santa Clara CA (US) for micron technology, inc., Wei Wang of Dublin CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F11/07, G06F11/00
CPC Code(s): G06F11/076
Abstract: a first blocks of a set of blocks of a memory device is identified. a die on which the first block resides is identified among a plurality of dies of the memory device. a threshold value associated with the die is selected from a range associated with a projected reliability metric of the die. responsive to determining that an endurance metric value associated with the die matches the threshold value, a program operation is performed with respect to a second block of the set of blocks.
Inventor(s): Febin Sunny of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc., Saideep Tiku of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1044
Abstract: apparatuses and methods related to error correction via artificial intelligence (ai) are described. an augmented reality (ar) display can be coupled to a memory device. ai circuitry coupled to the memory device can receive an error correction model. prior to receipt of the error correction model by the ai circuitry, the error correction model can be trained, externally to the memory device and ai circuitry, to correct random errors introduced to execution of the ar ai workload in hazardous conditions. the ai circuitry can execute the model to perform error correction in association with execution of the ar ai workload.
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Aaron P. Boehm of Boise ID (US) for micron technology, inc., Scott D. Van De Graaff of Boise ID (US) for micron technology, inc., Mark D. Ingram of Boise ID (US) for micron technology, inc., Todd Jackson Plum of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F9/30, G06F11/07, G06F11/30
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for evaluation of memory device health monitoring logic are described. for example, a memory device may include health monitoring logic operable to activate certain internal health monitors of a set of multiple monitors and to communicate an output associated with the activated monitors. in a first mode of operation, the health monitoring logic may provide a single output that is generated from multiple outputs of the set of monitors. in a second mode of operation, the health monitoring logic may cycle through certain monitors (e.g., in a test mode), and may generate an output corresponding to respective active monitors as it cycles through the set of monitors. the health monitoring logic may communicate an output specific to each monitor to a host device such that the host device may evaluate an output from each monitor of the set of monitors.
Inventor(s): Hui Ye of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: memory systems and devices (and associated methods) with improved active performance loss (apl) completion detection are described herein. in one embodiment, a memory device comprises nonvolatile memory and logic configured to (i) write a first value to a first location in the nonvolatile memory, (ii) detect a power loss event corresponding to the memory device, and (iii) before powering down the memory device based at least in part on the detected power loss event, write a second value to a second location in the nonvolatile memory different from the first location. the first value and/or the second value can correspond to a current power cycle number of the memory device. after power is subsequently restored to the memory device, the logic can compare the first and second values and proceed with reconstructing the memory device using apl management data when the first value matches the second value.
Inventor(s): Akira Goda of Tokyo (JP) for micron technology, inc., Koichi Kawai of Yokohama (JP) for micron technology, inc., Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Yoshihiko Kamata of Yokohama (JP) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: memories might include a controller configured to cause the memory to apply a programming pulse to a memory cell, perform an analog verify phase on the memory cell, in response to the analog verify phase, apply a first voltage level to a corresponding data line of the memory cell that is selected from a group consisting of an inhibit voltage level, a full enable voltage level, and an analog enable voltage level, apply a subsequent programming pulse to the memory cell, perform a digital verify phase on the memory cell, in response to the digital verify phase, apply a second voltage level to the corresponding data line of the memory cell that is selected from a group consisting of the inhibit voltage level and a digital enable voltage level, and apply a next subsequent programming pulse to the memory cell.
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., David Aaron Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/0811, G06F11/10, G06F11/30, G06F12/0882, G06F12/0891
CPC Code(s): G06F12/0811
Abstract: methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. for a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. for a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. the memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.
Inventor(s): Jeremy BINFET of Boise ID (US) for micron technology, inc., Lance Walker DOVER of Fair Oaks CA (US) for micron technology, inc., Tommaso VALI of Sezze (IT) for micron technology, inc., Walter DI FRANCESCO of Avezzano (IT) for micron technology, inc.
IPC Code(s): G06F12/14, G11C16/04, G11C16/22
CPC Code(s): G06F12/1466
Abstract: in some implementations, a memory device may resolve a set of latches of a nand page buffer to a set of initialized values. the memory device may obtain a nand page buffer initialized data set from the set of initialized values of the set of latches. the memory device may generate a security key using the nand page buffer initialized data set.
Inventor(s): Nikesh AGARWAL of Boise ID (US) for micron technology, inc., Robert M. WALKER of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/16
CPC Code(s): G06F13/1668
Abstract: provided is a system comprising a communication interface between a host and a device, wherein the header of a first memory request transmitted on the forward link of the communication interface encodes, in a bit vector, addresses to be read for a plurality of second memory requests. combining one or more read requests with another request such that a single request header is transmitted for a plurality of respective requests provides for more efficient use of the forward link bandwidth. corresponding methods are also described.
Inventor(s): James S. Rehmeyer of Boise ID (US) for micron technology, inc., Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/16, G11C17/14, G11C17/18
CPC Code(s): G06F13/1689
Abstract: a timing of an execution of a command in a memory device can be affected delay elements. the delay elements of a unit of delay elements can cause variable delays of the command paths. the delay elements can be activated based on settings stored in a fuse array of a memory device. the delay elements can be used to change a timing of current draw of the memory devices.
Inventor(s): Nikesh AGARWAL of Boise ID (US) for micron technology, inc., Robert M. WALKER of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/40, G06F13/42
CPC Code(s): G06F13/4013
Abstract: a system comprising an interface between a host and a device, wherein the interface is configured to reorder messages to package flits to reduce or eliminate underutilized bandwidth in one or both directions of a bidirectional link. in one example, the interface is in accordance with the cxl specification, and the host and the device (e.g., a memory device) include cxl-compliant controllers to pack and unpack flits.
Inventor(s): Christian Stroemel of Wauwatosa WI (US) for micron technology, inc.
IPC Code(s): G06T5/60, G06T5/50
CPC Code(s): G06T5/60
Abstract: a system for providing efficient-hardware accelerated neural network convolution is disclosed. the system receives an input image for an artificial intelligence task for a deep learning accelerator. the system divides the image in to equally-sized partially overlapping image patches and applies a fast fourier transform to the image patches. a size of an image filter is padded to match a size of the image patches and a fast fourier transform to applied to the image filter. for each pixel in each patch, a matrix-vector product is computed between channels of each image patch and a matrix from a corresponding pixel location in the image filter. an inverse fast fourier transform is applied to the matrix-vector product to convert each image to the spatial domain. a convolved version of the image is reconstructed by summing overlapping edges of the patches or by discarding overlapping regions of the patches.
20240321327. PRE-DECODER CIRCUITRY_simplified_abstract_(micron technology, inc.)
Inventor(s): Byung S. Moon of Plano TX (US) for micron technology, inc., Ramachandra Rao Jogu of McKinney TX (US) for micron technology, inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1039
Abstract: the present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. an embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G06F12/06
CPC Code(s): G11C7/1039
Abstract: apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. a metadata column address generator, during a metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. a column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.
20240321329. SELECTIVE ACCESS FOR GROUPED MEMORY DIES_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C29/46
CPC Code(s): G11C7/1063
Abstract: methods, systems, and devices for selective access for grouped memory dies are described. a memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. the protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. the command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. when the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.
20240321332. DIVIDED CLOCK CONTROL_simplified_abstract_(micron technology, inc.)
Inventor(s): Jongtae Kwak of Allen TX (US) for micron technology, inc.
IPC Code(s): G11C8/18, G11C7/22, H03K19/20, H03L7/081
CPC Code(s): G11C8/18
Abstract: methods, systems, and devices for divided clock control are described. an even clock signal associated with transitioning edges of even-indexed pulses of a global clock signal and an odd clock signal associated with transitioning edges of odd-indexed pulses of a global clock signal may be received. an indication of whether a received command was received on a transitioning edge of an even-indexed pulse may be received. based on the indication, whether to enable a propagation of the even clock signal to a first delay logic associated with even-indexed pulses or a second delay logic associated with odd-indexed pulses may be determined. based on the determining, whether to delay a propagation of the command using the first delay logic and the even clock signal or the second delay logic and the odd clock signal may be determined.
20240321336. APPARATUS OPERATING IN GEARDOWN MODE_simplified_abstract_(micron technology, inc.)
Inventor(s): Navya Sri Sreeram of Plano TX (US) for micron technology, inc., Kallol Mazumder of Dallas TX (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/4072, G11C11/4076
CPC Code(s): G11C11/40615
Abstract: methods, apparatuses, and systems related to an apparatus implementing a geardown mode in a parallel pipeline configuration. the apparatus can include mechanisms to manage signal timing across multiple data processing pipelines for different communication speeds. while operating in a geardown mode, the apparatus can capture a sync pulse in two or more data pipelines. the apparatus can identify the pipeline that first captured the sync pulse and suppress the operation of the other pipelines.
Inventor(s): Martin Brox of Munich (DE) for micron technology, inc., Milena Tsvetkova Ivanov of Munich (DE) for micron technology, inc., Natalija Jovanovic of München (DE) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/4074, G11C11/4093
CPC Code(s): G11C11/4096
Abstract: methods, systems, and devices for techniques and devices to reduce bus cross talk are described. adjacent conductive lines in a bus of a memory system may be electrically coupled if both conductive lines are concurrently driven to a high-state. for example, the bus may include a logic circuit coupled between the adjacent conductive lines, which may selectively couple the conductive lines based on the voltage applied to each conductive line. in some examples, the logic circuit may include an input coupled to the control signals of the drivers associated with the adjacent conductive lines. if both control signals are concurrently high, the logic circuit may activate a transistor to couple the conductive lines. such electrical coupling may reduce or eliminate the capacitive coupling between the two conductive lines when both are driven to a high state, which may result in increased reliability of signals in the conductive lines.
20240321347. READING A MULTI-LEVEL MEMORY CELL_simplified_abstract_(micron technology, inc.)
Inventor(s): Mattia Robustelli of Milano (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc., Innocenzo Tortorelli of Cernusco Sul Naviglio (IT) for micron technology, inc., Agostino Pirovano of Milano (IT) for micron technology, inc.
IPC Code(s): G11C11/56, G11C7/10
CPC Code(s): G11C11/56
Abstract: methods, systems, and devices for reading a multi-level memory cell are described. the memory cell may be configured to store three or more logic states. the memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. the memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. the memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
Inventor(s): Christophe Vincent Antoine Laurent of Agrate Brianza (IT) for micron technology, inc., Andrea Martinelli of Bergamo (IT) for micron technology, inc., Efrem Bolandrina of Fiorano al Serio (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (IT) for micron technology, inc.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0023
Abstract: methods, systems, and devices for shared decoder architecture for three-dimensional memory arrays are described. a memory device may include pillars coupled to an access line using two transistors positioned between the pillar and the access line. the gates of the two transistors may be coupled with respective gate lines coupled with circuitry configured to bias the gate line as part of an access operation for a memory cell coupled with the pillar. in some cases, the circuitry may be positioned between tiles of the memory device, at an end of one or more tiles of the memory device, between word line combs of a tile of the memory device, or a combination thereof.
Inventor(s): Li-Te Chang of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C13/00, G11C11/56
CPC Code(s): G11C13/0033
Abstract: systems, methods, and apparatus related to memory devices. in one approach, a cross-point memory array includes memory cells. a media controller reads one or more first memory cells and determines a read status. the read status indicates an error when reading the first memory cells. in response to this error, the controller refreshes the first memory cells. the controller uses the read status to determine zero-to-one failures associated with the first memory cells. if a number of these failures exceeds a threshold, then a refresh is applied to neighboring memory cells of the first memory cells. the physical addresses for the neighboring memory cells are determined by the controller from the physical addresses for the first memory cells.
Inventor(s): John Christopher M. Sancon of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0035
Abstract: systems, methods, and apparatus related to memory devices. in one approach, a memory device includes a sense amplifier, a counter, and memory having memory cells. access lines are used to select the memory cells for performing write operations. the memory device includes a controller to control the applying of a voltage to the memory cell. the voltage is applied during a write operation using the access lines. the sense amplifier is used to determine whether the memory cell reaches a threshold state or snaps. in response to determining that the memory cell does not snap, a write error count is incremented using the counter. the controller reads the counter to determine the write error count, and based on the write error count, the controller performs one or more media management or memory device control actions.
Inventor(s): Andrea Ghetti of Concorezzo (MB) (IT) for micron technology, inc., Andrea Martinelli of Bergamo (BG) (IT) for micron technology, inc., Efrem Bolandrina of Fiorano al Serio (BG) (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc., Paolo Fantini of Vimercate (MB) (IT) for micron technology, inc.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0069
Abstract: systems, methods, and apparatus related to memory devices. in one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. two current limiters are each used on the digit line side of each memory cell. a negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. a negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. a positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. the current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.
Inventor(s): Tommaso Vali of Sezze (IT) for micron technology, inc., Agostino Macerola of San Benedetto dei Marsi (IT) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10
CPC Code(s): G11C16/3459
Abstract: a memory device includes a memory array comprising a plurality of wordlines, and control logic, operatively coupled with the memory array. the control logic causes a measurement programming pulse to be sequentially applied to each of the plurality of wordlines of the memory array and determines respective threshold voltages stored in a number of memory cells associated with each of the plurality of wordlines. the control logic further determines a difference in the respective threshold voltages based on a location of the number of memory cells within each wordline and determines a respective resistance-capacitance (rc) time constant for each of the plurality of wordlines in view of the difference in the respective threshold voltages.
20240321380. VOLTAGE DOMAIN BASED ERROR MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc., Leonid Minz of Beer Sheva (IL) for micron technology, inc.
IPC Code(s): G11C29/50, H03K3/037
CPC Code(s): G11C29/50004
Abstract: a method includes supplying, via a voltage regulator, a supply voltage to a first voltage domain and a second voltage domain, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the supply voltage to an altered supply voltage based on the change in the error characteristic.
Inventor(s): Michael E. Koltonski of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/67, F28D1/02, H01J37/32, H01L21/3065
CPC Code(s): H01L21/67069
Abstract: a system for fabricating a semiconductor device structure includes a tool comprising a chamber and a platform within the chamber configured to receive a semiconductor device structure thereon. the tool further includes a heating and cooling system in operable communication with the platform and configured to control a temperature of the platform. the heating and cooling system comprises a cooling system including a cold tank for containing a cold thermal transfer fluid, the cold tank configured to be in fluid communication with the platform, thermal transfer fluid supply piping, and thermal transfer fluid return piping, a heating system including a hot tank for containing a hot thermal transfer fluid having a higher temperature than the cold thermal transfer fluid, the hot tank configured to be in fluid communication with the platform, the thermal transfer fluid supply piping, and the thermal transfer fluid return piping, and at least one temporary storage tank configured to receive at least some of the cold thermal transfer fluid or the hot thermal transfer fluid from at least the thermal transfer fluid return piping after switching a thermal load from the platform from one of the cooling system or the heating system to the other of the cooling system or the heating system. related methods and tools are disclosed.
Inventor(s): Zhou Xuan of Singapore (SG) for micron technology, inc., Sijia Yu of Singapore (SG) for micron technology, inc., Biow Hiem Ong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/528, G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): H01L23/5283
Abstract: a microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers. each of the tiers individually comprise a conductive structure and an insulative structure. the microelectronic device comprises a staircase structure having steps comprising lateral ends of the tiers, and contacts overlying the steps at different elevations of the staircase structure. the contacts comprise a liner material. the microelectronic device comprises conductive plug structures underlying the liner material of the contacts and comprising lateral portions within voids in at least some of the conductive structures, and vertical portions overlying the lateral portions. related electronic systems and methods are also described.
20240321745. MEMORY DEVICES INCLUDING SLOT STRUCTURES_simplified_abstract_(micron technology, inc.)
Inventor(s): Adam W. Saxler of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L21/768, H01L23/522, H01L23/532, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): H01L23/5283
Abstract: a microelectronic device comprises a stack structure, and slot structures vertically extending through the stack structure and dividing the stack structure into block structures. each of the slot structures individually comprises an insulative liner material vertically extending through the slot structure and contacting sidewalls of the insulative levels and the conductive levels defining the slot structure, and grains of a material in contact with sidewalls of the insulative liner material. the grains of the material comprise first grains spanning an entire width between the sidewalls of the insulative liner material. related memory devices, electronic systems, and methods are also described.
Inventor(s): Owen R. Fay of Meridian ID (US) for micron technology, inc., Madison E. Wale of Boise ID (US) for micron technology, inc., James L. Voelz of Boise ID (US) for micron technology, inc., Dylan W. Southern of Meridian ID (US) for micron technology, inc., Dustin L. Holloway of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/82
Abstract: semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. in some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. the routing substrate includes an upper surface having a redistribution structure. the semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. the semiconductor assembly further includes a controller die mounted on the routing substrate. the controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.
Inventor(s): Keisuke Otsuka of Kasaoka (JP) for micron technology, inc.
IPC Code(s): H01G4/30, H01L21/311
CPC Code(s): H01L28/40
Abstract: a method that includes, forming a first insulating film, first etching the first insulating film to form a first cylinder having a first diameter, forming a second insulating film on the first insulating film, second etching the second insulating film to form a second cylinder overlapping the first cylinder and having a second diameter different from the first diameter, third etching the first insulating film overlapping the second cylinder, filling the first and second cylinders with a conductive material, and removing the first and second insulating films.
Inventor(s): Shyam Surthi of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Michael A. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/861, H01L21/265, H01L21/768, H01L23/00, H01L29/66, H10B80/00
CPC Code(s): H01L29/861
Abstract: a semiconductor device including a first semiconductor device that includes a substrate, a memory array disposed above the substrate and below a frontside surface of the first semiconductor device, a plurality of source region contact (src) nodes disposed under the memory array, and a plurality of high-voltage (hv) diodes disposed in the substrate, each of the plurality of hv diodes being connected to corresponding one of the plurality of src nodes; and a second semiconductor device including a plurality of complementary-metal-oxide semiconductor (cmos) devices, each of the plurality of cmos devices being connected to, through a backside surface of the second semiconductor device and the frontside surface of the first semiconductor device, corresponding bond pad of the memory array, wherein fusion bonding exists between the backside surface of the second semiconductor device and the frontside surface of the first semiconductor device.
20240322675. VOLTAGE DOMAIN BASED ERROR MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc., Leonid Minz of Beer Sheva (IL) for micron technology, inc.
IPC Code(s): H02M3/04, H03K3/037
CPC Code(s): H02M3/04
Abstract: a method includes supplying, via a first voltage regulator, a first supply voltage to a first voltage domain including circuitry configured to operate at the first supply voltage, supplying, via a second voltage regulator, a second supply voltage to a second voltage domain including circuitry configured to operate in a voltage zone, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the second supply voltage to an altered supply voltage based on the change in the error characteristic.
20240322841. COMMAND ADDRESS FAULT DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Aaron P. BOEHM of Boise ID (US) for micron technology, inc., Melissa I. URIBE of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): H03M13/11, G11C8/06, H03M13/09
CPC Code(s): H03M13/1174
Abstract: implementations described herein relate to command address fault detection. a memory device may receive, from a host device via a command address (ca) bus, a plurality of bits associated with a command signal or an address signal. the ca bus may be configured for communicating command signals and address signals between the memory device and the host device. the memory device may generate one or more parity bits based on the plurality of bits. the one or more parity bits may be generated using a parity generation process that is common to the memory device and the host device. the memory device may transmit, to the host device, the one or more parity bits.
Inventor(s): Paul Aerick Lambert of Mountain View CA (US) for micron technology, inc.
IPC Code(s): H04L9/30, H04L9/08, H04L9/14
CPC Code(s): H04L9/3073
Abstract: systems, apparatuses, and methods to verify or validate a public key. for example, a computing device computes an intermediate key from inputs known to both the computing device and a remote device, and combines the intermediate key and a first private key via an operation (e.g., summation or multiplication) to generate a second private key. a second public key computed for the second private key by the computing device can be transmitted to the remote device for verification or validation without the remote device having data to identify the private keys. for example, the remote device can separately compute the intermediate key from the inputs and then combine the intermediate key with a first public key of the first private key (e.g., via summation or multiplication) to generate a version of the second public key for comparison with the second public key received from the computing device.
Inventor(s): Kang-Yong Kim of Boise ID (US) for micron technology, inc., Hyun Yoo Lee of Boise ID (US) for micron technology, inc., Timothy M. Hollis of Meridian ID (US) for micron technology, inc., Dong Soon Lim of Boise ID (US) for micron technology, inc.
IPC Code(s): H04L25/03, H04L25/49
CPC Code(s): H04L25/03057
Abstract: described apparatuses and methods are directed to equalization with pulse-amplitude modulation (pam) signaling. as bus frequencies have increased, the time for correctly transitioning between voltage levels has decreased, which can lead to errors. symbol decoding reliability can be improved with equalization, like with decision-feedback equalization (dfe). dfe, however, can be expensive for chip area and power usage. therefore, instead of applying dfe to all voltage level determination paths in a receiver, dfe can be applied to a subset of such determination paths. with pam4 signaling, for example, a dfe circuit can be coupled between an output and an input of a middle slicer. in some cases, symbol detection reliability can be maintained even with fewer dfe circuits by compressing a middle eye of the pam4 signal. the other two eyes thus have additional headroom for expansion. encoding schemes, impedance terminations, or reference voltage levels can be tailored accordingly.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04N25/75, G06T9/00, H04N25/40
CPC Code(s): H04N25/75
Abstract: a method in an integrated circuit device to compress images, including: generating, by an image processing logic circuit and based on first data representative of an input image, input data; generating, by an inference logic circuit and based on the input data, a column of inputs; converting, by the inference logic circuit using voltage drivers connected to wordlines and memory cells storing a weight matrix, and into output currents of the memory cells summed in bitlines, results of bitwise multiplications of bits in the column of inputs and bits stored in the memory cells in a form of threshold voltages of the memory cells; digitizing currents summed in the bitlines to obtain column outputs; generating, by the inference logic circuit, output data based on the column outputs; and generating, using the output data, second data representative of an output image compressed from the input image.
Inventor(s): Giorgio SERVALLI of Fara Gera d’Adda (IT) for micron technology, inc., Marcello MARIANI of Milano (IT) for micron technology, inc., Antonino RIGANO of Cernusco sul Naviglio (IT) for micron technology, inc., Marcello CALABRESE of Monza (IT) for micron technology, inc.
IPC Code(s): H10B12/00, H01L25/065
CPC Code(s): H10B12/30
Abstract: implementations described herein relate to various structures, integrated assemblies, and memory devices. in some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. the integrated assembly includes a gate pair that includes a first gate and a second gate. the first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. the integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. some implementations include methods of forming the various structures, integrated assemblies, and memory devices.
Inventor(s): Giorgio Servalli of Fara Gera D'Adda (IT) for micron technology, inc., Marcello Mariani of Milano (IT) for micron technology, inc.
IPC Code(s): H10B51/50, H01L25/065, H01L29/786, H10B53/30
CPC Code(s): H10B51/50
Abstract: some embodiments include an integrated assembly having first and second pillars of semiconductor material. the first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. first and second bottom electrodes are coupled with the first and second source/drain regions, respectively. the first and second source/drain regions are spaced from one another by an intervening region. first and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. some embodiments include methods of forming integrated assemblies.
Micron Technology, Inc. patent applications on September 26th, 2024
- Micron Technology, Inc.
- G06F3/06
- G06F12/02
- CPC G06F3/0608
- Micron technology, inc.
- CPC G06F3/061
- CPC G06F3/0611
- CPC G06F3/0613
- CPC G06F3/0614
- CPC G06F3/0634
- CPC G06F3/064
- CPC G06F3/0655
- G06F1/3234
- CPC G06F3/0656
- CPC G06F3/0659
- G06F9/455
- CPC G06F9/45558
- G06F11/07
- G06F11/00
- CPC G06F11/076
- G06F11/10
- CPC G06F11/1044
- G06F9/30
- G06F11/30
- CPC G06F11/1068
- CPC G06F12/0246
- G06F12/0811
- G06F12/0882
- G06F12/0891
- CPC G06F12/0811
- G06F12/14
- G11C16/04
- G11C16/22
- CPC G06F12/1466
- G06F13/16
- CPC G06F13/1668
- G11C17/14
- G11C17/18
- CPC G06F13/1689
- G06F13/40
- G06F13/42
- CPC G06F13/4013
- G06T5/60
- G06T5/50
- CPC G06T5/60
- G11C7/10
- CPC G11C7/1039
- G06F12/06
- G11C29/46
- CPC G11C7/1063
- G11C8/18
- G11C7/22
- H03K19/20
- H03L7/081
- CPC G11C8/18
- G11C11/406
- G11C11/4072
- G11C11/4076
- CPC G11C11/40615
- G11C11/4096
- G11C11/4074
- G11C11/4093
- CPC G11C11/4096
- G11C11/56
- CPC G11C11/56
- G11C13/00
- CPC G11C13/0023
- CPC G11C13/0033
- CPC G11C13/0035
- CPC G11C13/0069
- G11C16/34
- G11C16/10
- CPC G11C16/3459
- G11C29/50
- H03K3/037
- CPC G11C29/50004
- H01L21/67
- F28D1/02
- H01J37/32
- H01L21/3065
- CPC H01L21/67069
- H01L23/528
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- CPC H01L23/5283
- H01L21/768
- H01L23/522
- H01L23/532
- H01L23/00
- CPC H01L24/82
- H01G4/30
- H01L21/311
- CPC H01L28/40
- H01L29/861
- H01L21/265
- H01L29/66
- H10B80/00
- CPC H01L29/861
- H02M3/04
- CPC H02M3/04
- H03M13/11
- G11C8/06
- H03M13/09
- CPC H03M13/1174
- H04L9/30
- H04L9/08
- H04L9/14
- CPC H04L9/3073
- H04L25/03
- H04L25/49
- CPC H04L25/03057
- H04N25/75
- G06T9/00
- H04N25/40
- CPC H04N25/75
- H10B12/00
- H01L25/065
- CPC H10B12/30
- H10B51/50
- H01L29/786
- H10B53/30
- CPC H10B51/50
