Micron Technology, Inc. patent applications on September 19th, 2024
Patent Applications by Micron Technology, Inc. on September 19th, 2024
Micron Technology, Inc.: 51 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (13), G11C16/04 (8), G11C16/10 (6), G11C16/26 (6), G11C16/34 (5) G11C29/52 (2), G06F11/1068 (2), H10B43/27 (2), G11C16/102 (2), G06F3/0655 (2)
With keywords such as: memory, device, data, array, material, block, cells, conductive, region, and blocks in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Vinay Vijendra Kumar Lakshmi of Karnataka (IN) for micron technology, inc., Vijaya Janarthanam of Karnataka (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: a system includes a memory device having a plurality of blocks. a first subset of the plurality of blocks is configured as single-level cell (slc) memory and a second subset of the plurality of blocks is configured as multi-level cell (mlc) memory. a processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device. the processing device converts a second block of the set of blocks to the mlc memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.
Inventor(s): Rohit Sehgal of San Jose CA (US) for micron technology, inc., Vishal Tanna of Santa Clara CA (US) for micron technology, inc., Eishan Mirakhur of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a system can include a first memory device including a persistent byte-addressable memory; a second memory device; and a processing device, operatively coupled with the first and second memory devices, to perform operations including: receiving a first host command to write or read user data; storing the user data in the persistent byte-addressable memory with a first data granularity; and transmitting the user data stored in the persistent byte-addressable memory to the second memory device. the operations can further include: responsive to determining that a power loss event has occurred during an operation to a particular data packet in a size of the first data granularity in the persistent byte-addressable memory, determining whether the first host command associated with the particular data packet is completely executed; and responsive to determining that the first host command is not completely executed, restoring the particular data packet in the persistent byte-addressable memory.
20240311029. DYNAMIC SUPERBLOCK CONSTRUCTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Kishore K. Muchherla of Fremont CA (US) for micron technology, inc., Jianmin Huang of San Carlos CA (US) for micron technology, inc., Xiangang Luo of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a method includes forming at least a portion of a first superblock using a first subset of blocks from at least one memory die of a memory sub-system and forming at least a portion of a second superblock using a second subset of blocks from the at least one memory die of the memory sub-system.
Inventor(s): Lei PAN of Shanghai (CN) for micron technology, inc., Qi DONG of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0644
Abstract: technologies for storing streaming data include, in some embodiments, in response to determining that the chunk size satisfies a chunk size threshold and the streaming data is sequential data of a size that satisfies a threshold sequential data size, writing the sequential data to a first file system partition of a file system comprising a plurality of file system partitions, and in response to determining that the chunk size does not satisfy the chunk size threshold or the chunk size satisfies the chunk size threshold and the streaming data is the first type of metadata, writing the streaming data to a second file system partition of the plurality of file system partitions.
Inventor(s): Daniel J. Hubbard of Boise ID (US) for micron technology, inc., Kishore K. Muchherla of San Jose CA (US) for micron technology, inc., Dave Ebsen of Minnetonka MN (US) for micron technology, inc., Akira Goda of Setagaya (JP) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0652
Abstract: an apparatus can comprise a memory array comprising a plurality of strings of memory cells. each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. the first erase block can be configured as a first zone of one or more zones corresponding to a namespace independently of the second erase block.
Inventor(s): Yue Wei of Shanghai (CN) for micron technology, inc., Dahai Tian of Shanghai (CN) for micron technology, inc., Meng Wei of Shanghai City (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a write operation initiated by a memory sub-system controller of a memory sub-system to write system metadata to one or more of a plurality of dies of the a memory sub-system is identified by a processing device. a redundancy die of a plurality of dies of the memory sub-system is identified. one or more first physical blocks of the redundancy die is identified. a first write operation to write the system metadata to the one or more first physical blocks is performed.
Inventor(s): Zhenming Zhou of San Jose CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a memory access operation on a set of cells associated with a wordline of the memory device; determining that a temperature associated with the memory device satisfies a threshold criterion; determining a memory access operation type of the memory access operation; and performing the memory access operation on the set of cells associated with the wordline using a first time sense parameter, wherein the first time sense parameter corresponds to the memory access operation type and the temperature associated with the memory device.
20240311045. CACHE MANAGEMENT IN A MEMORY SUBSYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Chinnakrishnan Ballapuram of San Jose CA (US) for micron technology, inc., Akhila Gundu of San Jose CA (US) for micron technology, inc., Taeksang Song of San Jose CA (US) for micron technology, inc., Kimberly Judy Lobo of San Jose CA (US) for micron technology, inc., Saira S. Malik of Lafayette IN (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: methods, systems, and devices for cache management in a memory subsystem are described. an interface controller may include a first buffer and a second buffer. the interface controller may use the first and second buffers to facilitate operating a volatile memory as a cache for a non-volatile memory. during an access operation, the interface controller may use the buffer to transfer data between the volatile memory, non-volatile memory, and another device. in response to the access operation, the interface controller may use the second buffer to transfer second data from the volatile memory to the non-volatile memory.
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for managing power consumption associated with communicating data in a memory system are described. a memory system may selectively reduce a periodicity of a clock signal for one or more types of write operations, which may improve power consumption associated with data transfer rates during the one or more types of write operations. for example, the memory system may modify the clock signal for triple-level cell (tlc) write operations. the memory system reduce a periodicity of the clock signal to improve performance for tlc write operations by trading communication speed for internal array performance. additionally, or alternatively, some media management operations performed by the memory system that involve transferring data to higher-density memory cells may trigger the memory system to modify the clock signal.
Inventor(s): Daniel J. Hubbard of Boise ID (US) for micron technology, inc., Kishore K. Muchherla of San Jose CA (US) for micron technology, inc., Hong Lu of San Jose CA (US) for micron technology, inc., Xiangang Luo of Fremont CA (US) for micron technology, inc., Akira Goda of Setagaya (JP) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0679
Abstract: a method can comprise receiving data corresponding to a sequence of write commands to write the data to a memory array comprising a plurality of strings of memory cells. each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block having a first programming characteristic; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block having a second programming characteristic. the method can further comprise writing data sequentially to the first erase blocks of the plurality of strings and the second erase blocks of the plurality of strings in an interleaved manner by: writing a first portion of the data to one or more first erase blocks of the plurality of strings; and writing, subsequent to writing the first portion of the data to the one or more first erase blocks, a second portion of the data to one or more second erase blocks of the plurality of strings.
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc., Scott Lynn Michaelis of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F7/58
CPC Code(s): G06F7/582
Abstract: various examples are directed to systems and methods for generating a set of pseudorandom numbers in a computing system comprising a compute element and a memory device. a memory controller of the memory device may receive, from the compute element, an indication to generate a set of pseudorandom numbers. the memory controller may generate the set of pseudorandom numbers and write the set of pseudorandom numbers to a memory array of the memory device for access by the compute element.
Inventor(s): Tony Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F9/30, G06F9/32, G06F9/46, G06F12/0815, G06F12/0875, G06F15/78
CPC Code(s): G06F9/3004
Abstract: disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. in order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. if the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Wesley W. Borie of Boise ID (US) for micron technology, inc., Dennis G. Montierth of Meridian ID (US) for micron technology, inc., Garth N. Grubb of Boise ID (US) for micron technology, inc., Mow Yiak Goh of Boise ID (US) for micron technology, inc., Anthony M. Geidl of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F12/02
CPC Code(s): G06F11/10
Abstract: an exemplary host includes a data mapping decoder configured to decode a swizzle mapping signal received from a memory module to provide a data mapping setting, a data input/output circuit configured to receive a plurality of data bits from the memory module via a data bus, and a data adjustment circuit configured to re-arrange an order of the plurality of data bits based on the data mapping setting to provide a plurality of adjusted data bits.
Inventor(s): Wesley W. Borie of Boise ID (US) for micron technology, inc., Dennis G. Montierth of Meridian ID (US) for micron technology, inc., Garth N. Grubb of Boise ID (US) for micron technology, inc., Mow Yiak Goh of Boise ID (US) for micron technology, inc., Anthony M. Geidl of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/16, G11C8/08, G11C17/16
CPC Code(s): G06F11/1068
Abstract: an exemplary memory includes a first sub-wordline (swl) driver configured to provide first data from a memory cell array, a second swl driver configured to provide second data from a memory cell array, and an input/output (i/o) circuit configured to receive the first data and the second data from the first and second swl drivers, respectively. the i/o circuit including a data terminal mapping circuit configured to selectively route the first data and the second data to different respective data terminal based on a data terminal mapping setting.
Inventor(s): Gil Golov of Backnang (DE) for micron technology, inc.
IPC Code(s): G06F11/10, G06F3/06, G06F11/07, G06F12/0804, G11C11/406, G11C29/42, G11C29/52, H03M13/09, H03M13/11
CPC Code(s): G06F11/1068
Abstract: a deferred error correction code (ecc) scheme for memory devices is disclosed. a disclosed method includes starting a deferred period of operation of a memory system in response to detecting the satisfaction of a condition; receiving an operation during the deferred period, the operation comprising a read or write operation access one or more memory banks of the memory system; deferring ecc operations for the operation; executing the operation; detecting an end of the deferred period of operation; and executing the ecc operations after the end of the deferred period.
20240311288. INTERNAL LOG MANAGEMENT IN MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Kyle Brock-Petersen of Boulder CO (US) for micron technology, inc., Scheheresade Virani of Frisco TX (US) for micron technology, inc., Steven Gaskill of Campbell CA (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/023
Abstract: described are systems and methods for internal log management in memory sub-systems. an example memory sub-system comprises a controller managing one or more memory devices. the controller is configured to perform operations, comprising: maintaining a write pointer referencing a next data item position within a log buffer residing on a memory device of the one or more memory devices; maintaining a log retrieval pointer referencing a data retrieval position within the log buffer; storing, at a log buffer position specified by the write pointer, a data item reflecting a state of the system; advancing the write pointer by a size of the data item; responsive to determining that the write pointer exceeds an end of the log buffer, wrapping the write pointer around the end of the log buffer; responsive to receiving, from a host, a log retrieval request, retrieving the log data starting from the position within the log buffer referenced by the log retrieval pointer; transmitting the retrieved log data to the host; advancing the log retrieval pointer by a size of the retrieved log data; responsive to determining that the log retrieval pointer exceeds the end of the log buffer, wrapping the log retrieval pointer around the end of the log buffer.
Inventor(s): Alex Frolikov of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F3/06
CPC Code(s): G06F12/0246
Abstract: a computer storage device having a host interface, a controller, non-volatile storage media, and firmware. the firmware instructs the controller to: store a namespace map to map blocks of logical addresses defined in a namespace to first blocks of logical addresses defined in a capacity of the non-volatile storage media; without changing a size of the namespace, adjust the namespace map to map the blocks of the logical addresses defined in the namespace to second blocks of the logical addresses defined in the capacity of the non-volatile storage media (e.g., to consolidate blocks for performance improvement); and translate the logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.
20240311295. SELECTIVE GARBAGE COLLECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Antonio Mauro of Giugliano in Campania (NA) (IT) for micron technology, inc., Luigi Costanzo of Trentola Ducenta (CE) (IT) for micron technology, inc., Nicola Colella of Capodrise (CE) (IT) for micron technology, inc.
IPC Code(s): G06F12/02, G06F1/3212
CPC Code(s): G06F12/0253
Abstract: methods, systems, and devices for selective garbage collection are described. a host system may determine that a battery level is below a threshold or determine whether a power parameter of a memory system that includes a memory device satisfies a criterion. the host system may set a value of a flag. the memory system may perform an access operation and identify the value of the flag. the memory system may determine whether performing a garbage collection procedure is permitted based on identifying the value of the flag.
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Xing Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0802
Abstract: a system includes a memory device comprising an array of memory cells coupled with a plurality of page buffers. at least a portion of the array is configured as single-level cell memory. a processing device is coupled to the memory device and includes cache. the processing device detects demand for the cache during a memory operation requiring access to the single-level cell memory. detecting the demand can include determining an amount of metadata required to be accessed or updated based on a type of the memory operation. the processing device causes, based on the demand, the metadata associated with the memory operation to be moved from one of the cache or the array of memory cells to one or more page buffers of the plurality of page buffers.
20240311306. VARIABLE EXECUTION TIME ATOMIC OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Dean E. Walker of Allen TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F12/084
CPC Code(s): G06F12/084
Abstract: system and techniques for variable execution time atomic operations are described herein. when an atomic operation for a memory device is received, the run length of the operation is measured. if the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. a result of the operation is queued until it can be written to the cache line. at that point, the cache line is unlocked.
Inventor(s): Sundararajan Sankaranarayanan of Fremont CA (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/084, G06F3/06, G06F12/0882, G11C16/04, G11C16/24, G11C16/26
CPC Code(s): G06F12/084
Abstract: a memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. the page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources are asynchronously and concurrently accessible by the first memory array and the second memory array, and wherein the at least one shared resource is accessible in a time-multiplexed fashion by the first memory array and the second memory array.
Inventor(s): Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G06F12/0891, G06F12/0831, G06F13/16
CPC Code(s): G06F12/0891
Abstract: a victim management unit (mu) for performing a media management operation is identified. the victim mu stores valid data in a first memory device of a plurality of memory devices. a cached data item on a second memory device of the plurality of memory devices is identified. a valid-to-invalid ratio of the victim mu is compared to a threshold value. in view of comparison, it is determined whether to pad the cached data item with at least a subset of the valid data stored at the victim mu or dummy data. based on the determination, the cached data item padded with one of at least a subset of the valid data stored at the victim mu or the dummy data is written to a target mu.
Inventor(s): Li-Te Chang of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/1027, G06F12/06, G11C16/04, G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G06F12/1027
Abstract: a block of a memory device is identified. a threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. the threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a difference between the wordline and a boundary wordline of the block. a read operations is performed on the block using a read level voltage modified by the threshold voltage offset, wherein the read level voltage is associated with the block.
Inventor(s): Shuai Xu of Santa Clara CA (US) for micron technology, inc., Michele Piccardi of Cupertino CA (US) for micron technology, inc., Arvind Muralidharan of Folsom CA (US) for micron technology, inc., June Lee of Sunnyvale CA (US) for micron technology, inc., Qisong Lin of El Dorado Hills CA (US) for micron technology, inc., Scott A. Stoller of Boise ID (US) for micron technology, inc., Jun Shen of Shanghai (CN) for micron technology, inc.
IPC Code(s): G11C5/14
CPC Code(s): G11C5/144
Abstract: in a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. in the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.
20240312498. SEMICONDUCTOR DEVICE HAVING OUTPUT BUFFER_simplified_abstract_(micron technology, inc.)
Inventor(s): Mieko Kojima of Hino (JP) for micron technology, inc., Kazuyuki Morishige of Sagamihara (JP) for micron technology, inc., Tetsuya Arai of Sagamihara (JP) for micron technology, inc., Guangcan Chen of Machida (JP) for micron technology, inc.
IPC Code(s): G11C7/10, G11C5/06, H03K19/017
CPC Code(s): G11C7/1057
Abstract: some embodiments provide an apparatus including a semiconductor substrate having source regions and regions alternately arranged in a first direction; gate electrodes between the source regions and the drain regions; a first wiring layer including first conductive patterns covering the source regions and second conductive patterns covering the drain regions; first via conductors between the first conductive patterns and the source regions; second via conductors between the second conductive patterns and the drain regions; a second wiring layer over the first wiring layer, including third conductive patterns covering the first conductive patterns and fourth conductive patterns covering the second conductive patterns; third via conductors between the third conductive patterns and the first conductive patterns; and fourth via conductors between the fourth conductive patterns and the second conductive patterns. the fourth via conductors are shifted from the third via conductors in a second direction perpendicular to the first direction.
Inventor(s): Hyunyoo Lee of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc., Yang Lu of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, H03K19/017, H03K19/173
CPC Code(s): G11C7/109
Abstract: the subject application is directed to die location detection for grouped memory dies are described. a memory device may include multiple memory die that are coupled with a shared bus. in some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. for example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.
Inventor(s): Guy S. Perry, IV of Boise ID (US) for micron technology, inc., Shinichi Miyatake of Sagamihara (JP) for micron technology, inc., Kyuseok Lee of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C8/08, G11C8/14
CPC Code(s): G11C8/08
Abstract: active materials for reducing hot electron-induced punch-through and related apparatuses and computing systems are disclosed. an apparatus includes a first active material, a second active material, a third active material, and a fourth active material. the first active material includes a first outside edge and a first inside edge. the first outside edge defines a first notch. the second active material is spaced at substantially a minimum tolerance distance from the first active material. the third active material is spaced at substantially the minimum tolerance distance from the second active material. the fourth active material includes a second outside edge and a second inside edge. the second inside edge is spaced at substantially the minimum tolerance distance from the third active material. the second outside edge defines a second notch. a computing system includes a memory device including a subwordline driver including the apparatus.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Randall J. Rooney of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4078, G06F13/16, G06F21/55
CPC Code(s): G11C11/4078
Abstract: memory devices, systems including memory devices, and methods of operating memory devices are described in which waterfall attacks can be prevented from degrading data by alerting a memory controller that the memory device requests time to perform internal management operations, and should not be sent any further commands (e.g., activate commands) for a predetermined amount of time. in one embodiment, a memory device includes an external pin, a mode register, a memory array including a plurality of rows of memory cells, and circuitry configured to: determine that a criterion to perform an internal management operation on a subset of the plurality of rows has been met, transmit, in response to determining the criterion has been met, a signal to the external pin, determine a duration corresponding to the internal management operation, and write a bit value indicative of the determined duration to the mode register.
Inventor(s): Innocenzo Tortorelli of Cernusco Sul Naviglio (IT) for micron technology, inc., Hari Giduturi of Folsom CA (US) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/56, G11C11/4074, G11C11/409, G11C29/50
CPC Code(s): G11C11/5642
Abstract: methods, systems, and devices for varying-polarity read operations for polarity-written memory cells are described. memory cells may be programmed to store different logic values based on applying write voltages of different polarities to the memory cells. a memory device may read the logic values based on applying read voltages to the memory cells, and the polarity of the read voltages may vary such that at least some read voltages have one polarity and at least some read voltages have another polarity. the read voltage polarity may vary randomly or according to a pattern and may be controlled by the memory device or by a host device for the memory device.
Inventor(s): Fabio Pellizzer of Boise ID (US) for micron technology, inc., Russell L. Meyer of Boise ID (US) for micron technology, inc., Stephen W. Russell of Boise ID (US) for micron technology, inc., Lorenzo Fratin of Buccinasco (MI) (IT) for micron technology, inc.
IPC Code(s): G11C16/04, H10B43/10, H10B43/20
CPC Code(s): G11C16/0483
Abstract: methods, systems, and devices for trench and multiple pier architecture for three-dimensional memory arrays are described. manufacturing operations for a memory device may include forming trenches, and subsequently forming multiple types of pier structures extending between the trenches in a first horizontal direction, in a second horizontal direction or both. for example, the trenches may be arranged in a grid-like structure extending in one or more rows and one or more columns. a set of a first type of pier may be formed along each of the trenches, a set of a second type of pier may be formed between adjacent trenches in the first horizontal direction, and a set of a third type of pier may be formed between adjacent trenches in the second horizontal direction.
Inventor(s): Eric N. Lee of San Jose CA (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., Alessio Urbani of Roma RM (IT) for micron technology, inc., Justin Bates of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08
CPC Code(s): G11C16/102
Abstract: a request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. a first drive operation is executed to load first data into a first select gate drain (sgd) associated with the first sub-block. following completion of the first drive operation, a second drive operation is executed to load second data into a second sgd associated with the second sub-block. following completion of the second drive operation, a third drive operation is executed to re-load the first data into the first sgd.
Inventor(s): Zhongguang Xu of San Jose CA (US) for micron technology, inc., Tingjun Xie of Milpitas CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/26, G11C16/32, G11C16/34
CPC Code(s): G11C16/102
Abstract: a processing device in a memory sub-system logically closes a block of a memory device to prevent additional program operations from being performed on the block. the processing device further causes one or more wordlines of the block to be programmed with padding data. the one or more wordlines are adjacent to a last wordline of the block programmed before the block was logically closed. in addition, the processing device causes a remaining set of wordlines of the block to be concurrently programmed to a single program state.
Inventor(s): Karan Banerjee of Singapore (SG) for micron technology, inc., Waing Pyie Soe of Singapore (SG) for micron technology, inc., Shyam Sunder Raghunathan of Singapore (SG) for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/04, G11C16/08
CPC Code(s): G11C16/26
Abstract: control logic in a memory device receives a request to perform a corrective read operation on one or more memory cells associated with a selected wordline of a memory array of a memory device and determines whether one or more memory cells associated with an adjacent wordline of the memory array are in an erased state. responsive to determining that the one or more memory cells associated with the adjacent wordline are in the erased state, the control logic identifies a partial block read voltage offset value and causes a read voltage modified according to the partial block read voltage offset value to be applied to the selected wordline to perform the corrective read operation on the one or more memory cells associated with the selected wordline.
Inventor(s): Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Patrick Robert Khayat of San Diego CA (US) for micron technology, inc., AbdelHakim S. Alhussien of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/26, G06F9/30, G06F9/38, G06F18/243, H03M13/00, H03M13/01
CPC Code(s): G11C16/26
Abstract: a memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.
20240312534. MULTI-STATE PROGRAMMING OF MEMORY CELLS_simplified_abstract_(micron technology, inc.)
Inventor(s): Jeremy M. Hirst of Orangevale CA (US) for micron technology, inc., Shanky K. Jain of Folsom CA (US) for micron technology, inc., Hernan A. Castro of Shingle Springs CA (US) for micron technology, inc., Richard K. Dodge of Santa Clara CA (US) for micron technology, inc., William A. Melton of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G06F16/21, G06F16/587, G11C11/56, G11C13/00, G11C16/12, G11C16/26
CPC Code(s): G11C16/34
Abstract: the present disclosure includes apparatuses, methods, and systems for multi-state programming of memory cells. an embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of a plurality of possible data states by applying a voltage pulse to the memory cell, determining the memory cell snaps back in response to the applied voltage pulse, turning off a current to the memory cell upon determining the memory cell snaps back, and applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell.
Inventor(s): Aaron S. Yip of Los Gatos CA (US) for micron technology, inc., Paolo Tessariol of Arcore (IT) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10
CPC Code(s): G11C16/3404
Abstract: control logic in a memory device causes a plurality of source control signals to be applied to a plurality of deintegrated source segments of a first block of a plurality of blocks of a memory array of a memory device to selectively activate a plurality of sub-blocks of the first block and programs a plurality of select gate devices in a plurality of logical select gate layers spanning the plurality of sub-blocks and positioned at a drain-side of the first block of the memory array with a threshold voltage pattern.
Inventor(s): Eric N. Lee of San Jose CA (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., Alessio Urbani of Roma RM (IT) for micron technology, inc., Justin Bates of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10
CPC Code(s): G11C16/3427
Abstract: a request to execute a programming operation to program multiple sub-blocks including a first sub-block and a second sub-block of a memory device is identified. a first drive operation is executed to load first data into a first select gate drain (sgd) associated with the first sub-block. one or more program bias disturb mitigation operations are executed in association with a second drive operation to load second data into a second sgd associated with the second sub-block.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/18, G11C29/42, G11C29/44
CPC Code(s): G11C29/18
Abstract: per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. in some examples, baseline error information may be stored in a fuse array. in some examples, the baseline error information may be loaded from the fuse array to a memory array. in some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/42
CPC Code(s): G11C29/42
Abstract: per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. in some examples, baseline error information may be stored in a fuse array. in some examples, the baseline error information may be loaded from the fuse array to a memory array. in some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/52
CPC Code(s): G11C29/52
Abstract: per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. in some examples, baseline error information may be stored in a fuse array. in some examples, the baseline error information may be loaded from the fuse array to a memory array. in some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.
20240312554. EFFICIENT READ DISTURB SCANNING_simplified_abstract_(micron technology, inc.)
Inventor(s): Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Deping He of Boise ID (US) for micron technology, inc., Zhongyuan Lu of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C11/406, G11C29/02
CPC Code(s): G11C29/52
Abstract: methods, systems, and devices for efficient read disturb scanning are described. a memory system may limit a quantity of word lines scanned as part of a read disturb scan. for example, the memory system may select a threshold quantity of word lines of a block for the read disturb scan based on a characterization of the word lines, such as selecting one or more word lines having higher bit error rates than other word lines of the block. the memory system may perform the read disturb scan on the selected one or more word lines to determine respective failure bit counts of the selected word lines and exclude unselected word lines of the block from the read disturb scan. the memory system may determine whether to perform a refresh operation on the block based on whether a respective failure bit count satisfies a threshold failure bit count.
Inventor(s): Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/498, H01L23/00, H01L23/31, H01L25/00, H01L25/065
CPC Code(s): H01L23/49838
Abstract: at least one embodiment of a semiconductor device assembly include a cross-stack substrate can comprise an assembly substrate including an upper surface, a first and second die stack at the upper surface, and a cross-stack substrate spaced from the upper surface. the first and second die stacks can each include multiple semiconductor dies in electric communication with the assembly substrate, and the cross-stack substrate can be coupled to and extending between a first and a second semiconductor die of the first and second die stacks, respectively. a passive semiconductor component can be carried by the cross-stack substrate, and can be in electric communication with the assembly substrate. further, the passive semiconductor component can be in electric communication with the first semiconductor die of the first die stack exclusively via the assembly substrate.
Inventor(s): James Brian Johnson of Boise ID (US) for micron technology, inc., Brent Keeth of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Eiichi Nakano of Boise ID (US) for micron technology, inc., Amy Rae Griffin of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/775, H01L23/00, H01L25/065, H01L27/088, H01L29/423, H01L29/66, H01L29/786, H10B12/00
CPC Code(s): H01L29/775
Abstract: methods, systems, and devices for transistor architectures in coupled semiconductor systems are described. a memory system may be formed from multiple semiconductor components (e.g., multiple dies, multiple wafers) that are coupled together, with different semiconductor components implementing different techniques for transistor formation. for example, a first die may include a memory array and first circuitry configured to access the memory array, and a second die coupled with the first die may include second circuitry configured to access the memory array. the first circuitry may include transistors formed in accordance with a first fabrication technique (e.g., to form a first type of transistors) and the second circuitry may include transistors formed in accordance with a second fabrication technique (e.g., to form a second type of transistors). the dies may be coupled in a manner that provides an electrical coupling between the first circuitry and the second circuitry.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/786, H01L29/66
CPC Code(s): H01L29/78696
Abstract: a microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. the transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. the microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. related microelectronic devices, electronic devices, and related methods are also disclosed.
Inventor(s): Eric J. Stave of Meridian ID (US) for micron technology, inc.
IPC Code(s): H05K9/00, G11C11/408
CPC Code(s): H05K9/0071
Abstract: this disclosure is directed to circuitry for inducing jitter to clock signal of an electronic device to reduce undesired electromagnetic emissions of the electronic device during operation. the electronic device may include a jitter generator to induce the jitter to the clock signal. in some embodiments, the electronic device may also include a multiplexer outputting either of the clock signal or the jittered clock signal for latching the output signals. as such, the output signals may have a baseline margin based on the clock signal while the electronic device may operate using the jittered clock signal. the jittered clock signal may spread the undesired electromagnetic emissions of the electronic device and therefore reduce interference.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., David Daycock of Boise ID (US) for micron technology, inc., Albert Liao of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. the memory cells individually comprising a transistor comprise a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. a gate is operatively-proximate the channel region. a capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. the first capacitor electrode is directly electrically coupled to the first source/drain region. the second capacitor electrode of multiple of the capacitors is directly electrically coupled with one another. digitlines extend elevationally through the vertically-alternating tiers. individual of the second source/drain regions of individual of the transistors that are in different memory-cell tiers are directly electrically coupled to individual of the digitlines. a wordline is in individual of the memory-cell tiers that comprises the gate of multiple of the individual transistors in the individual memory-cell tiers. the wordline in a lower of the memory-cell tiers has a greater minimum width than a minimum width of the wordline in a higher of the memory-cell tiers that is directly above the lower memory-cell tier. methods are also disclosed.
Inventor(s): Justin B. Dorhout of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Martin C. Roberts of Boise ID (US) for micron technology, inc., Mohd Kamran Akhtar of Boise ID (US) for micron technology, inc., Chet E. Carter of Boise ID (US) for micron technology, inc., David Daycock of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B41/35, H01L21/033, H01L21/308, H01L21/311, H01L21/3215, H01L21/67, H01L21/768, H10B20/00, H10B41/20, H10B41/23, H10B41/27, H10B43/27, H10B43/35
CPC Code(s): H10B41/35
Abstract: some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. the more-heavily-doped region and the less-heavily-doped region have the same majority carriers. the integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. the gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. the interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. some embodiments include methods of forming integrated assemblies.
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc., Collin Howder of Boise ID (US) for micron technology, inc., Matthew J. King of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/35, H10B43/35
CPC Code(s): H10B43/27
Abstract: memory circuitry comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. the stack comprises laterally-spaced memory blocks. the memory blocks individually comprise sub-blocks in an upper portion thereof. strings of memory cells are included and that comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. a conductive-material tier is included and that comprises conductive material in the upper portions. the conductive material extends downwardly from the conductive-material tier to below the conductive-material tier. sub-block trenches in the upper portions are individually between immediately-laterally-adjacent of the sub-blocks and extend through the conductive-material tier. select gates of select-gate transistors are in individual of the sub-blocks operatively alongside channel material of the select-gate transistors. the select gates comprise the conductive material of the conductive-material tier and the conductive material extending downwardly from the conductive-material tier to below the conductive-material tier alongside the channel material of the select-gate transistors. methods are also disclosed.
Inventor(s): Paolo Tessariol of Arcore (IT) for micron technology, inc., Aaron S. Yip of Los Gatos CA (US) for micron technology, inc., Giovanni Mazzone of Villasanta (IT) for micron technology, inc., Matthew King of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, G11C16/04, G11C16/10, H10B41/27
CPC Code(s): H10B43/27
Abstract: a system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars, wherein respective subsets of the memory array pillars correspond to respective sub-blocks of a block of the memory array, and forms a plurality of deintegrated source segments adjacent to the memory array, wherein the source segments of the plurality of deintegrated source segments are associated with respective sub-blocks and are physically segregated from one another.
Inventor(s): James Lattin of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/35, H10B41/27, H10B41/35, H10B43/27
CPC Code(s): H10B43/35
Abstract: a method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. the stack comprises laterally-spaced memory blocks an upper portion of which individually comprise sub-blocks. the conductive tiers of the sub-blocks individually comprise select-gate tiers that individually comprise select gates. sub-block trenches are in the upper portion of the memory blocks and are individually between immediately-laterally-adjacent of the sub-blocks. the sub-block trenches individually extend through and horizontally-along the select-gate tiers and the insulative tiers of the sub-blocks. in the sub-block trenches, conducting material of the select-gate tiers is recessed laterally-outward relative to sub-block trench sidewalls of insulative material of the insulative tiers of the sub-blocks to form lateral recesses in the select-gate tiers. insulating material is formed in the sub-block trenches and in the lateral recesses. other aspects, including structure independent of method, are disclosed.
Inventor(s): Lorenzo Fratin of Buccinasco (MI) (IT) for micron technology, inc., Enrico Varesi of Milano (MI) (IT) for micron technology, inc., Paolo Fantini of Vimercate (IT) for micron technology, inc.
IPC Code(s): H10N70/20, H10B63/00, H10N70/00
CPC Code(s): H10N70/231
Abstract: methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in vertical structures are described. a memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. the bulk region may extend between the first electrode and the sidewall region. the bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. also, the sidewall region may separate the bulk region from the second electrode.
Micron Technology, Inc. patent applications on September 19th, 2024
- Micron Technology, Inc.
- G06F3/06
- CPC G06F3/0608
- Micron technology, inc.
- CPC G06F3/0619
- CPC G06F3/064
- CPC G06F3/0644
- CPC G06F3/0652
- CPC G06F3/0655
- CPC G06F3/0656
- CPC G06F3/0659
- CPC G06F3/0679
- G06F7/58
- CPC G06F7/582
- G06F9/30
- G06F9/32
- G06F9/46
- G06F12/0815
- G06F12/0875
- G06F15/78
- CPC G06F9/3004
- G06F11/10
- G06F12/02
- CPC G06F11/10
- G06F11/16
- G11C8/08
- G11C17/16
- CPC G06F11/1068
- G06F11/07
- G06F12/0804
- G11C11/406
- G11C29/42
- G11C29/52
- H03M13/09
- H03M13/11
- CPC G06F12/023
- CPC G06F12/0246
- G06F1/3212
- CPC G06F12/0253
- G06F12/0802
- CPC G06F12/0802
- G06F12/084
- CPC G06F12/084
- G06F12/0882
- G11C16/04
- G11C16/24
- G11C16/26
- G06F12/0891
- G06F12/0831
- G06F13/16
- CPC G06F12/0891
- G06F12/1027
- G06F12/06
- G11C16/10
- G11C16/34
- CPC G06F12/1027
- G11C5/14
- CPC G11C5/144
- G11C7/10
- G11C5/06
- H03K19/017
- CPC G11C7/1057
- H03K19/173
- CPC G11C7/109
- G11C8/14
- CPC G11C8/08
- G11C11/4078
- G06F21/55
- CPC G11C11/4078
- G11C11/56
- G11C11/4074
- G11C11/409
- G11C29/50
- CPC G11C11/5642
- H10B43/10
- H10B43/20
- CPC G11C16/0483
- G11C16/08
- CPC G11C16/102
- G11C16/32
- CPC G11C16/26
- G06F9/38
- G06F18/243
- H03M13/00
- H03M13/01
- G06F16/21
- G06F16/587
- G11C13/00
- G11C16/12
- CPC G11C16/34
- CPC G11C16/3404
- CPC G11C16/3427
- G11C29/18
- G11C29/44
- CPC G11C29/18
- CPC G11C29/42
- CPC G11C29/52
- G11C29/02
- H01L23/498
- H01L23/00
- H01L23/31
- H01L25/00
- H01L25/065
- CPC H01L23/49838
- H01L29/775
- H01L27/088
- H01L29/423
- H01L29/66
- H01L29/786
- H10B12/00
- CPC H01L29/775
- CPC H01L29/78696
- H05K9/00
- G11C11/408
- CPC H05K9/0071
- CPC H10B12/30
- H10B41/35
- H01L21/033
- H01L21/308
- H01L21/311
- H01L21/3215
- H01L21/67
- H01L21/768
- H10B20/00
- H10B41/20
- H10B41/23
- H10B41/27
- H10B43/27
- H10B43/35
- CPC H10B41/35
- CPC H10B43/27
- CPC H10B43/35
- H10N70/20
- H10B63/00
- H10N70/00
- CPC H10N70/231
