Micron Technology, Inc. patent applications on September 12th, 2024
Patent Applications by Micron Technology, Inc. on September 12th, 2024
Micron Technology, Inc.: 40 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (11), G11C16/10 (6), G11C16/04 (5), G11C16/26 (4), G06F11/10 (3) G11C16/102 (5), G06F7/523 (3), G06F11/1068 (2), G06F3/0611 (2), G06F3/064 (2)
With keywords such as: memory, device, cells, data, die, systems, signed, semiconductor, methods, and output in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20240302433. APPARATUS AND TEST ELEMENT GROUP_simplified_abstract_(micron technology, inc.)
Inventor(s): FUMIE UCHIDA of Kyoto-shi (JP) for micron technology, inc.
IPC Code(s): G01R31/3187, G01R31/28
CPC Code(s): G01R31/3187
Abstract: according to one or more embodiments of the disclosure, an apparatus comprising a plurality of active regions on a semiconductor substrate, an active bridge region connecting two active regions among the plurality of active regions, and a plurality of test circuit elements on the active bridge region and the two active regions.
Inventor(s): Tao Xiong of Shanghai (CN) for micron technology, inc., Guang Chng Ye of Shanghai (CN) for micron technology, inc., Jizhe Xing of Shanghai (CN) for micron technology, inc., Jun Shen of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F1/3234, G06F1/3225, G11C5/14
CPC Code(s): G06F1/3275
Abstract: various embodiments described herein provide for a method for reduced power consumption by a memory system. a memory system of some embodiments monitors power state change requests received by the memory system from a host system, and determines a pattern of power state change requests received from the host system. based on the determined pattern, the memory system can decide to activate or deactivate a reduced power consumption mode on the memory system. a reduced power consumption mode can comprise a first set of operation parameters that cause a memory system to operate with lower power consumption than a second set of operation parameters associated with a current operation mode, where the current operation mode is associated with a current power state set or last requested by the host system.
20240302958. MEMORY MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Horia C. Simionescu of Foster City CA (US) for micron technology, inc., Chung Kuang Chin of Saratoga CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0802, G06F12/10, G06F12/123
CPC Code(s): G06F3/0604
Abstract: managed units (mus) of data can be stored on a memory device according to a slice-based layout. a slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective mus of data. a subset of the stripes each include a quantity of partitions and a first quantity of mus of data. another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of mus of data.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: methods, systems, and apparatuses include receiving a command directed to a portion of memory. a cycle number for the portion of memory is determined. a group to which the portion of memory belongs is determined. a sensing time is determined using the cycle number and the group. the command is executed using the sensing time.
Inventor(s): Jay Sarkar of San Jose CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Ipsita Ghosh of New Garia, Kolkata (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations including sending, to a device that provides error-handling flow optimization, an ordered set of error-handling operations to be performed to recover data residing in a segment of the memory device; receiving, from the device that provides the error-handling flow optimization, a reordered set of error-handling operations, wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations, wherein the reordered set is obtained by applying the ordered set of error-handling operations to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations, and wherein the latency data for the previously-performed error-handling operations depends on a workload of the segment of the memory device; and performing one or more error-handling operations of the reordered set of error-handling operations to the data residing in the segment of the memory device.
Inventor(s): Christopher Joseph BUEB of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0616
Abstract: a system includes a non-volatile memory configured with a wear-leveling media pool, and a controller. the wear-leveling media pool has an initial endurance limit and is divided into a plurality of virtual partitions. each virtual partition is assigned a respective endurance threshold. the controller is configured to monitor a first endurance parameter for each virtual partition based on the first endurance parameter for a respective virtual partition satisfying or not satisfying the respective endurance threshold of the respective virtual partition, evaluate a second endurance parameter of the wear-leveling media pool, determine to increase the initial endurance limit of the wear-leveling media pool by an additional endurance amount based on the second endurance parameter satisfying a parameter threshold, and allocate the additional endurance amount among one or more virtual partitions of the plurality of virtual partitions to increase the respective endurance threshold of the one or more virtual partitions.
Inventor(s): Oyvind Hachre of Loveland CO (US) for micron technology, inc., Nathaniel Wessel of Longmont CO (US) for micron technology, inc., Byron Harris of Mead CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. in particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.
Inventor(s): Johnny Au LAM of Firestone CO (US) for micron technology, inc., Nathaniel WESSEL of Longmont CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: implementations described herein relate to memory devices including a single-level cell (slc) block storing data for migration to multiple multi-level cell (mlc) blocks. in some implementations, a memory device includes multiple mlc blocks that include mlcs, with each mlc being capable of storing at least four bits of data, and multiple slc blocks that can store data prior to the data being written to one of the mlc blocks. each slc block may be capable of storing different data sets that are destined for storage in different mlc blocks. the memory device may include a mapping component that can store a mapping table that includes multiple entries, in which an entry indicates a mapping between a memory location in the slc blocks and a corresponding mlc block for which data stored in the memory location is destined. numerous other implementations are described.
20240302991. PLANE BALANCING IN A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): John J. Kane of Westminster CO (US) for micron technology, inc., Byron D. Harris of Mead CO (US) for micron technology, inc., Vivek Shivhare of Milpitas CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: methods, systems, and devices for plane balancing in a memory system are described. a memory system may select a memory die for writing a set of data. the memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. the memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.
20240302998. MANAGING ADDRESS ACCESS INFORMATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Keun Soo Song of Meridian ID (US) for micron technology, inc., Hyunyoo Lee of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for managing address access information are described. a device may receive a command for an address of a memory array. based on or in response to the command, the device may read a first set of tag bits from the memory array. the first set of tag bits may indicate access information for a set of addresses that includes the address. the device may determine a second set of tag bits based on the command and the address. the second set of tag bits may indicate updated access information for the address. the device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Lakshmi Kalpana Vakati of San Jose CA (US) for micron technology, inc., Dave Scott Ebsen of Minnetonka MN (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc., Sanjay Subbarao of Irvine CA (US) for micron technology, inc., Vivek Shivhare of Milpitas CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and apparatuses include receiving a write command including user data. the write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. temporary parity data is generated using the first and second user data portions. the temporary parity data and the first and second user data portions are stored in a buffer. portions of the first and second block are programmed with two programming passes. the first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. the temporary parity data is maintained in the buffer until a second programming pass of the first and second block.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G06F7/523
CPC Code(s): G06F7/523
Abstract: systems, methods, and apparatus related to memory devices that perform multiplication using memory cells. in one approach, a first integrated circuit die has a memory cell array. the memory cell array includes memory cells programmable to store weights (e.g., representing synapses of a neural network). a second integrated circuit die has logic circuitry that performs multiplication of the stored weights by an input pattern. the second die is connected to the first die by hybrid bonding. multiplication results are determined by the logic circuitry based on accumulation of output currents from at least a portion of the memory cells.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G06F7/523
CPC Code(s): G06F7/523
Abstract: systems, methods, and apparatus related to memory devices that perform multiplication using sets of four memory cells. in one approach, memory cells in a memory cell array are programmed so that each set stores a signed weight. voltages are applied to the sets of memory cells. the voltages represent signed inputs to be multiplied by the signed weights. output currents from the memory cells in each set are summed in first and second lines. a sum of the output currents in each line is digitized to provide first and second results. the first and second results are combined to provide a signed result for each set.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G06F7/523
CPC Code(s): G06F7/523
Abstract: systems, methods, and apparatus related to memory devices that perform multiplication using logic states of memory cells. in one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. voltage drivers apply different voltages to the memory cells during multiplication. the magnitudes of the different voltages correspond to a significance of the bit stored by the respective memory cell. one or more inputs are applied to the memory cells to multiply the inputs by the multi-bit weight. output currents from the memory cells are summed on a common line. the sum of the output currents is used to provide at least one result from the multiplication.
20240303087. DATA CACHING FOR FAST SYSTEM BOOT-UP_simplified_abstract_(micron technology, inc.)
Inventor(s): Francesco Basso of Portici (IT) for micron technology, inc., Giuseppe Ferrari of Napoli (IT) for micron technology, inc., Francesco Falanga of Quarto (IT) for micron technology, inc., Massimo Iaculo of San Marco Evangelista (IT) for micron technology, inc.
IPC Code(s): G06F9/4401, G06F12/0871
CPC Code(s): G06F9/4406
Abstract: methods, systems, and devices for data caching for fast system boot-up are described. a memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. the linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. the linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. the memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Paul A. Laberge of Shoreview MN (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for memory die fault detection using a calibration pin are described. a memory device may perform a calibration procedure on a first resistor of each of a set of memory dies of a memory module using a pin coupled with the memory module. the memory device may couple the pin to a second resistor of a memory die of the set of memory dies based on the memory die identifying a fault condition for the memory die executing one or more of multiple commands from the host device. the memory device may receive, from the host device, a command to read a register of one or more memory dies of the set of memory dies and may output, to the host device, an indication of the memory die that identified the fault condition based on coupling the pin to the second resistor.
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Aaron P. Boehm of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F3/06, G06F11/20, G06F13/00, G11C7/10, G11C11/22, G11C11/4093, G11C29/52, H03M13/00, H03M13/19, H03M13/45
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. for example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. if the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. during a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. the memory device may, in some cases, store error detection or correction information generated by the host device.
20240303159. DATA PROTECTION AND RECOVERY_simplified_abstract_(micron technology, inc.)
Inventor(s): Joseph M. McCrate of Boise ID (US) for micron technology, inc., Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Brian M. Twait of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1076
Abstract: a redundant array of independent disks (raid) protection can be provided along with other types of error correction code (ecc) schemes that can correct residual bit errors. the bit errors correctable by the ecc schemes not only include those errors that have been existing in input data used for the raid process, but also those bit errors may have been propagated due to the existing errors.
Inventor(s): Pitamber Shukla of Boise ID (US) for micron technology, inc., Ryan Hrinya of Boise ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc., Scott A. Stoller of Boise ID (US) for micron technology, inc., Tyler Betz of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: apparatuses and methods for determining performing read operations on a partially programmed block are provided. one example apparatus can include a controller configured to apply a read voltage to a word line in an array of memory cells during a read operation on the word line, apply a first pass voltage to a number of programmed word lines in the array of memory cells during the read operation, and apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells during the read operation.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G06F17/16
CPC Code(s): G06F17/16
Abstract: systems, methods, and apparatus related to memory devices that perform signed multiplication using sets each containing two memory cells. in one approach, sets organized as pairs of memory cells in a memory cell array are programmed so that each set stores a signed weight. voltages are applied to the sets of memory cells at first and second times. the voltages represent signed inputs to be multiplied by the signed weights. output currents from the memory cells in each set are accumulated at the first and second times in a respective common line for each set. a signed result for each set is provided based on digitizing sums of the output currents accumulated at the first and second times.
20240304227. TECHNIQUES TO CONFIGURE DRIVERS_simplified_abstract_(micron technology, inc.)
Inventor(s): Martin Bach of Munich (DE) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/14, H03K19/017
CPC Code(s): G11C7/106
Abstract: methods, systems, and devices for techniques to configure drivers are described. a memory device may calibrate a set of drivers at multiple reference voltages corresponding to different signal values of the drivers. in some examples, a driver associated with transmitting data may include an inductor and the memory device may include a calibration circuit to identify one or more configurations for a set of pull-up circuits and a set of pull-down circuits of the driver both with and without the inductor. the calibration circuit may compare an output of a first pull-up circuit isolated from the inductor with one or more reference voltages, compare an output of a second pull-up circuit coupled with the inductor with the one or more reference voltages, and compare an output of a pull-down circuit isolated from the inductor to the one or more reference voltages.
20240304233. PRE-DECODER CIRCUITRY_simplified_abstract_(micron technology, inc.)
Inventor(s): Jin Seung Son of McKinney TX (US) for micron technology, inc., Mingdong Cui of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C11/4074, G11C11/4093, G11C11/4096
CPC Code(s): G11C11/4087
Abstract: the disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. an embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuity to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. the bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. the pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.
Inventor(s): Paolo Fantini of Vimercate (IT) for micron technology, inc., Andrea Martinelli of Bergamo (IT) for micron technology, inc., Maurizio Rizzi of Cologno Monzese (IT) for micron technology, inc.
IPC Code(s): G11C16/04, G11C16/08, G11C16/24, G11C16/30, G11C16/34
CPC Code(s): G11C16/0433
Abstract: methods, systems, and devices for techniques for parallel memory cell access are described. a memory device may include multiple tiers of memory cells. during a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. during a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. during a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.
Inventor(s): Phong Sy Nguyen of Livermore CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G06F3/06, G11C11/56, G11C16/04, G11C16/26
CPC Code(s): G11C16/10
Abstract: a memory system to store multiple bits of data in a memory cell. a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. the threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. a group identification of a first group, among the groups, containing the first level is determined for the memory cell. the memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. the data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/24, G11C16/26
CPC Code(s): G11C16/102
Abstract: systems, methods, and apparatus related to memory devices that perform signed multiplication using logical states of memory cells. in one approach, a memory device has a memory array including sets of memory cells programmed to store a signed weight in each set (e.g., four cells in a set store a signed weight of +1, 0, or −1). voltages that represent signed inputs (e.g., +1, 0, or −1) are applied to the memory cells to perform the multiplication. a result from the multiplication is determined based on summing of output currents from the memory cells.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/26
CPC Code(s): G11C16/102
Abstract: systems, methods, and apparatus related to memory devices that perform multiplication using sets of memory cells. in one approach, memory cells in the sets are programmed so that each set stores a signed weight. voltage drivers apply voltages to the memory cells in each set. the voltages correspond to signed inputs to multiply by the signed weights in the sets. one or more common lines (e.g., bitlines) are coupled to each set for summing output currents from the sets. a digitizer provides a signed result based on summing the output currents from the sets.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G06F7/544, G11C16/04
CPC Code(s): G11C16/102
Abstract: systems, methods, and apparatus related to memory devices that perform signed multi-bit to multi-bit multiplication using sets of memory cells. in one approach, a memory cell array has sets of memory cells. each set is programmable to store a multi-bit signed weight. voltage drivers apply voltages to each set. the voltages correspond to multi-bit signed inputs. one or more common lines are coupled to each set for summing output currents from the sets during the multiplication. a digitizer provides signed results based on summing the output currents. the signed results are added with adjustment for the bit significance of each signed result to provide a final accumulation result for the multiplication.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08
CPC Code(s): G11C16/102
Abstract: systems, methods, and apparatus related to memory devices that perform multiplication using memory cells programmed to have different thresholds based on bit significance. in one approach, a memory cell array has memory cells that are each programmed to store one bit of a multi-bit weight. voltage drivers apply voltages to the memory cells. the applied voltages represent inputs to be multiplied by the weights. a common line is coupled each of the memory cells to accumulate output currents from the cells. the output currents each have a magnitude corresponding to the significance of the bit stored by the respective memory cell. a digitizer uses the summed output currents as an input and provides a digital result as an output.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/26, G11C16/32
CPC Code(s): G11C16/102
Abstract: a system includes a memory device and a processing device operatively coupled to the memory device. the processing device is to receive a programming command with respect to a set of memory cells. the processing device is further to determine a value of a metric reflecting reliability of a subset of the set of memory cells. the processing device is further to determine a delay based on the value of the metric. the processing device is further to perform a two-pass programming operation with respect to the subset of memory cells. the two-pass programming operation includes the delay.
Inventor(s): Dustin L. Holloway of Meridian ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): H01F27/28, H01F27/02, H01F27/26, H01F41/04, H01L25/16
CPC Code(s): H01F27/2804
Abstract: a semiconductor assembly is provided. the assembly includes a substrate and an inductor. the inductor includes a magnetic core with a first row of first bond pads on a first side and a second row of second bonds pads on a second side, the second side being opposite to the first side. the inductor further includes a plurality of wire bonds, each wire bond connecting a topside of one of the first bond pads to a topside of one of the second bond pads by running over the magnetic core, and a plurality of electrical traces connecting an underside of one of the first bond pads to an underside of one of the second bond pads by running under the magnetic core and through the substrate.
Inventor(s): Owen R. Fay of Meridian ID (US) for micron technology, inc., Chan H. Yoo of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/56, H01L21/78, H01L23/29, H01L23/31
CPC Code(s): H01L21/56
Abstract: methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. in one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. the semiconductor die can include a first surface facing the redistribution structure and a second surface spaced apart from the redistribution structure. the method also includes reducing a thickness of the semiconductor die to no more than 10 �m. the method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.
Inventor(s): Chin Hui Chong of Singapore (SG) for micron technology, inc., Seng Kim Dalson Ye of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/065, H10B80/00
CPC Code(s): H01L25/0657
Abstract: a microelectronic device includes a controller device, a first die vertically overlying the controller device, a second die vertically overlying the first die, and a wire. the first die includes a first pad horizontally separated from a horizontal center of the controller device by a first distance. the second die includes a second pad horizontally separated from the horizontal center of the controller device by a second distance larger than the first distance. the wire contacts the first pad of the first die and the second pad of the second die. memory device packages and electronic systems are also disclosed.
Inventor(s): MOEKO KAWANA of Hiroshima (JP) for micron technology, inc., YOSHIKAZU MORIWAKI of Hiroshima (JP) for micron technology, inc.
IPC Code(s): H01L29/417, H01L29/40
CPC Code(s): H01L29/41775
Abstract: an example apparatus includes a semiconductor substrate having first and second diffusion regions and a channel region arranged between the first and second diffusion regions; a gate electrode covering the channel region with a gate insulating film interposed therebetween; and first and second contact plugs connected to the first and second diffusion regions, respectively. each of the first and second contact plugs includes an upper section and a lower section arranged between the upper section and an associated one of the first and second diffusion regions. the lower section has a smaller diameter than the upper section at a boundary cross-section between the lower and upper sections.
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc., Roger W. Lindsay of Boise ID (US) for micron technology, inc., Martin J. Barclay of Middleton ID (US) for micron technology, inc.
IPC Code(s): H01L29/78, H10B41/27, H10B43/27
CPC Code(s): H01L29/7827
Abstract: a microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, a staircase structure comprising steps comprising horizontal edges of the tiers, each of the steps comprising multiple tiers, and conductive contact structures vertically extending from a vertically upper surface of the stack structure to the conductive structures of the steps, the conductive structures defining each of the steps individually in contact with a conductive contact structure. related memory devices and electronic systems are also described.
Inventor(s): Mark A. Tverdy of Boise ID (US) for micron technology, inc., Kaleb A. Wilson of Caldwell ID (US) for micron technology, inc.
IPC Code(s): H01R12/73, H01R12/70, H01R25/00, H05K7/02, H05K7/10
CPC Code(s): H01R12/73
Abstract: various embodiments described herein provide a connector assembly with integrated data and backup energy connections, which can be used to electrically couple together two or more printed circuit boards and electrically couple at least one of those printed circuit boards to a backup energy source. for example, a connector assembly of an embodiment can be used to implement a memory sub-system by coupling together two or more printed circuit boards of the memory sub-system and coupling the memory sub-system to a backup energy source, such as a set of capacitors or a set of batteries, which can be used to power the memory sub-system in the event of a main power loss.
Inventor(s): Olivier Duval of Pacifica CA (US) for micron technology, inc.
IPC Code(s): H04L9/08, G06F11/32, G06Q50/10, H04L9/32, H04L67/306, H04L67/51
CPC Code(s): H04L9/0825
Abstract: various examples are directed to a system for configuring a host device. the host device may comprise a memory system and may be programmed to receive subscriber software for interfacing the host device to a subscription service. the host device may also be programmed to receive from a first assembler secure appliance, first trace data based at least in part on the subscriber software and generate trace-derived data using the first trace data and the memory system identification key. the host device may also be programmed to send a subscription request to a subscription server associated with the subscription service. the subscription request may comprise the trace-derived data. the host device may also be programmed to receive, from the subscription server, subscription data for accessing the subscription service.
Inventor(s): Chulkyu Lee of Meridian ID (US) for micron technology, inc., Timothy M. Hollis of Meridian ID (US) for micron technology, inc.
IPC Code(s): H04L25/03, G06F13/16
CPC Code(s): H04L25/03267
Abstract: methods, apparatuses, and systems related to an apparatus for managing on-die inter-symbol interference (isi) are described. the apparatus may include (1) a single communication path with a set of drivers and (2) an on-die isi prevention circuit coupled to the communication path in parallel. the single communication path may be used to propagate a slower speed signal and a higher speed signal. the on-die isi prevention circuit may be configured to adjust the propagated signal for one of the speeds to reduce the isi in the communicated signal.
Inventor(s): Anthony D. Veches of Boise ID (US) for micron technology, inc.
IPC Code(s): H05K5/02, H01R12/70, H05K1/14, H05K7/20
CPC Code(s): H05K5/026
Abstract: this disclosure relates generally to interfaces between memory modules and circuit boards. more specifically, this disclosure relates to interfaces for coupling a memory module to a circuit board such that the memory module is arranged in a plane that is substantially parallel with a plane of the circuit board. various embodiments disclosed herein include interfaces, memory modules including interfaces or portions of interfaces, and/or circuit boards including interfaces and/or portions of interfaces. associated devices and systems are also disclosed.
Inventor(s): Scott J. Derner of Boise ID (US) for micron technology, inc., Charles L. Ingalls of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B53/30, H01L23/528, H01L27/02, H01L29/08, H01L29/78, H10B12/00, H10B53/20
CPC Code(s): H10B53/30
Abstract: some embodiments include an integrated assembly. the integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. the capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. the first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. a digit line is electrically connected with the second source/drain region. a conductive structure is electrically connected with the fourth source/drain region.
20240306403. STACKED SEMICONDUCTOR DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Yeon Seung Jung of Hwaseong (KR) for micron technology, inc.
IPC Code(s): H10B80/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: a semiconductor device is provided that can include a substrate and a first and second stack of semiconductor dies coupled to the substrate. the first stack of semiconductor dies and the second stack of semiconductor dies are staggered such that the first stack of semiconductor dies has a first footprint and the second stack of semiconductor dies has a second footprint that partially overlaps the first footprint. the first stack of semiconductor dies and the second stack of semiconductor dies are alternated such that each semiconductor die of the first stack of semiconductor dies is vertically mounted to a respective semiconductor die of the second stack of semiconductor dies. conductive structures extend between portions of the first and second stacks of semiconductor dies exposed beyond the second footprint and the first footprint, respectively, to electrically couple the semiconductor dies.
Micron Technology, Inc. patent applications on September 12th, 2024
- Micron Technology, Inc.
- G01R31/3187
- G01R31/28
- CPC G01R31/3187
- Micron technology, inc.
- G06F1/3234
- G06F1/3225
- G11C5/14
- CPC G06F1/3275
- G06F3/06
- G06F12/0802
- G06F12/10
- G06F12/123
- CPC G06F3/0604
- CPC G06F3/0611
- CPC G06F3/0616
- CPC G06F3/064
- CPC G06F3/0655
- CPC G06F3/0659
- G06F7/523
- CPC G06F7/523
- G06F9/4401
- G06F12/0871
- CPC G06F9/4406
- G06F11/10
- G06F11/07
- CPC G06F11/1068
- G06F11/20
- G06F13/00
- G11C7/10
- G11C11/22
- G11C11/4093
- G11C29/52
- H03M13/00
- H03M13/19
- H03M13/45
- CPC G06F11/1076
- G06F12/02
- CPC G06F12/0246
- G06F17/16
- CPC G06F17/16
- G11C7/14
- H03K19/017
- CPC G11C7/106
- G11C11/408
- G11C11/4074
- G11C11/4096
- CPC G11C11/4087
- G11C16/04
- G11C16/08
- G11C16/24
- G11C16/30
- G11C16/34
- CPC G11C16/0433
- G11C16/10
- G11C11/56
- G11C16/26
- CPC G11C16/10
- CPC G11C16/102
- G06F7/544
- G11C16/32
- H01F27/28
- H01F27/02
- H01F27/26
- H01F41/04
- H01L25/16
- CPC H01F27/2804
- H01L21/56
- H01L21/78
- H01L23/29
- H01L23/31
- CPC H01L21/56
- H01L25/065
- H10B80/00
- CPC H01L25/0657
- H01L29/417
- H01L29/40
- CPC H01L29/41775
- H01L29/78
- H10B41/27
- H10B43/27
- CPC H01L29/7827
- H01R12/73
- H01R12/70
- H01R25/00
- H05K7/02
- H05K7/10
- CPC H01R12/73
- H04L9/08
- G06F11/32
- G06Q50/10
- H04L9/32
- H04L67/306
- H04L67/51
- CPC H04L9/0825
- H04L25/03
- G06F13/16
- CPC H04L25/03267
- H05K5/02
- H05K1/14
- H05K7/20
- CPC H05K5/026
- H10B53/30
- H01L23/528
- H01L27/02
- H01L29/08
- H10B12/00
- H10B53/20
- CPC H10B53/30
- H01L25/00
- H01L25/18
- CPC H10B80/00
