Micron Technology, Inc. patent applications on October 17th, 2024
Patent Applications by Micron Technology, Inc. on October 17th, 2024
Micron Technology, Inc.: 57 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (15), G06F12/02 (8), G11C7/10 (5), H01L23/00 (4), G11C11/406 (3) G06F12/0246 (4), G06F3/0659 (3), G06F3/0611 (3), G11C29/52 (2), G06F11/1068 (2)
With keywords such as: memory, device, data, based, methods, block, described, systems, command, and devices in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20240345727. DATA COMPRESSION FOR MAPPING TABLES_simplified_abstract_(micron technology, inc.)
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Wenjun Wu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0608
Abstract: methods, systems, and devices for data compression for mapping tables are described. a memory system may store a table that includes mappings between a set of logical block addresses and a set of physical block addresses. the table may be stored to volatile memory of the memory system and each entry may include a subset of physical block addresses and one or more logical block addresses that correspond to the subset of physical block addresses. in some implementations, a quantity of the entries that each include the subset of physical block addresses and the one or more logical block addresses may be determined based on dividing the set of physical block addresses by a factor. similarly, a size of the entries may be determined based on dividing the set of physical block addresses by the factor.
20240345730. MEMORY DEVICE LOG DATA STORAGE_simplified_abstract_(micron technology, inc.)
Inventor(s): Scheheresade VIRANI of Frisco TX (US) for micron technology, inc., Jeffrey Lee MUNSIL of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: implementations described herein relate to memory device log data storage. in some implementations, a memory device may store a first data stream associated with a first type of log data in a circular buffer. the memory device may store a second data stream associated with a second type of log data in another memory location. the memory device may detect an event included in the second data stream that is associated with an attribute level that satisfies a threshold. the memory device may write data stored in the circular buffer after a time at which the event is detected to a non-volatile memory based on the attribute level satisfying the threshold, wherein the data stored in the circular buffer is stored in the non-volatile memory in connection with data associated with the event.
20240345731. DYNAMIC WRITE SPEEDS FOR DATA PROGRAMMING_simplified_abstract_(micron technology, inc.)
Inventor(s): Jameer Mulani of Bangalore (IN) for micron technology, inc., Amiya Banerjee of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: methods, systems, and devices for dynamic write speeds for data programming are described. a memory system controller may transfer first data from a first portion of a memory system to a second portion of the memory system according to a first set of parameters based on determining that a first quantity of unavailable data blocks of the first portion satisfies a first threshold. the memory system controller may receive one or more commands to write second data and may write the second data to one or more data blocks of the first portion. the memory system controller may transfer third data from the first portion to the second portion according to a second set of parameters and based on determining that a second quantity of unavailable data blocks of the first portion (and based on writing the second data) satisfies a second threshold.
Inventor(s): Yanhua Bi of Shanghai (CN) for micron technology, inc., Luca Porzio of Casalnuovo (IT) for micron technology, inc., Hao Yu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: methods, systems, and devices for detection and latency reduction of write-intensive procedures in a memory system are described. a memory system may determine that a set of write commands share a group identifier associated with a writeback procedure or target a swap area of the non-volatile memory associated with a swap procedure. the memory system may determine that the writeback procedure or the swap procedure has been. the memory system may write, based on determining that the writeback procedure or the swap procedure has been initiated, data associated with the set of write commands to the non-volatile memory using a first type of write operation that has lower latency than a second type of write operation.
Inventor(s): Yanhua Bi of Shanghai (CN) for micron technology, inc., Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc., Hao Yu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: methods, systems, and devices for checkpoint procedure detection and latency reduction are described. a memory system may determine that a checkpoint procedure has been initiated. based on determining that the checkpoint procedure has been initiated, the memory system may write metadata associated with the checkpoint procedure to a non-volatile memory using a first type of write operation that has lower latency than a second type of write operation supported by the non-volatile memory. the memory system may also write checkpoint information about the metadata to the non-volatile memory using the first type of write operation.
Inventor(s): Jameer Mulani of Bangalore (IN) for micron technology, inc., Nitul Gohain of Bangalore (IN) for micron technology, inc., Amiya Banerjee of Bangalore (IN) for micron technology, inc., Rakeshkumar Dayabhai Vaghasiya of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: methods, systems, and devices for adaptive polling for higher density storage are described. a controller of a memory system may identify a temperature of the memory device and select one or more polling parameters that are associated with identifying a status of the memory device based on a temperature of a memory system. in some cases, the controller may perform a polling operation according to the one or more polling parameters based on selecting the one or more polling parameters.
Inventor(s): Ferdinando Bedeschi of Biassono (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: methods, systems, and devices for transistor configurations for vertical memory arrays are described. a memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. for example, a memory device may include a conductive pillar that extends through levels of a memory array. the pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. to access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.
20240345750. HOST RECOVERY FOR A STUCK CONDITION_simplified_abstract_(micron technology, inc.)
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F1/3234, G06F1/3296
CPC Code(s): G06F3/0634
Abstract: methods, systems, and devices for host recovery for a stuck condition of a memory system are described. the host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). in some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. the host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. in some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.
Inventor(s): Lei Pan of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: exemplary methods, apparatuses, and systems include a performance mode manager for controlling performance of a wireless update by selecting a performance mode using rations of allocation. the performance mode manager receives a request to initialize a file transfer from a host using wireless communication. in response to the request, the performance mode manager identifies a size of the file transfer by the memory subsystem. the performance mode manager selects a performance mode from a plurality of performance modes and allocates the available set of memory pages using the performance mode. the performance mode manager receives a file of the file transfer. the performance mode manager programs a first portion of the file at the default bit density to the first portion of memory and a second portion of the file at the reduced bit density to the second portion of memory.
20240345755. DYNAMICALLY ADJUSTING DATA READ SIZE_simplified_abstract_(micron technology, inc.)
Inventor(s): Wenjun Wu of Shanghai (CN) for micron technology, inc., Feng Xu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: methods, systems, and devices for dynamically adjusting data read size are described. a memory system controller may be configured to dynamically adjust a size of data transmitted to a host system based on determining a quantity of data requested by the host system. the memory system controller may support receiving a read command of a first data size, incrementing a counter by the first data size, requesting the data from a memory device according to a second data size, and transmitting the data from the memory device according to a third data size based on the counter. the memory system controller may determine the counter does not satisfy a threshold and configure the third data size as a relatively small quantity of data. however, the memory system controller may determine the counter satisfies the threshold and configure the third data size as a relatively large quantity of data.
20240345759. IMPLICIT ORDERED COMMAND HANDLING_simplified_abstract_(micron technology, inc.)
Inventor(s): Huachen Li of Shanghai (CN) for micron technology, inc., Zhou Zhou of Shanghai (CN) for micron technology, inc., Chaofeng Zhang of Shanghai (CN) for micron technology, inc., Jianfeng Li of Shanghai (CN) for micron technology, inc., Chen Huang of Shanghai (CN) for micron technology, inc., Lin Huang of Shanghai (CN) for micron technology, inc., Wei Li of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0652
Abstract: methods, systems, and devices for improved implicit ordered command handling are described. for instance, a memory device may receive, from a host device, a first command and a second command. the memory device may determine whether a first memory operation associated with the first command and a second memory operation associated with the second command are to be performed in an order relative to each other based on a first time when the first command is received relative to a second time when the second command is received. the memory device may select whether to perform a first memory access procedure or a second memory access procedure based on whether the first memory operation and the second memory operation are a same type of memory operation and on whether the first memory operation and the second memory operation are to be performed in the order relative to each other.
Inventor(s): Roberto Izzi of Caserta (IT) for micron technology, inc., Reshmi Basu of Boise ID (US) for micron technology, inc., Luca Porzio of Casalnuovo (IT) for micron technology, inc., Christian M. Gyllenskog of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0655
Abstract: methods, systems, and devices for memory operations are described. a host system may obtain data for writing to a memory system. the host system may send, to the memory system, an indication that the data is to be written to the memory system, and the memory system may remove invalid data at the memory system until the memory system has sufficient resources to store the data. based on the memory system having sufficient resources, the memory system may delay background operations at the memory system until the data has been written to the memory system. the memory system may also create a restore point based on the memory system having sufficient resources and receiving the data. in other examples, the removal of invalid data at the memory system may be delayed until after the data is written to the memory system.
Inventor(s): Roberto Izzi of Caserta (CE) (IT) for micron technology, inc., Nicola Colella of Capodrise (CE) (IT) for micron technology, inc., Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc., Marco Onorato of Villasanta (MB) (IT) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices are described to indicate, in an entry of logical to physical (l2p) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. each entry may have a third field, which may indicate whether the data is sequential. based on the third field, the host system may determine whether data to be read from a memory system is sequential. the host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an l2p entry associated with the data. similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.
Inventor(s): Zhengbo Wang of Shanghai (CN) for micron technology, inc., Jia Sun of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for pre-operation for application to boost firmware performance are described. a host system may notify a memory system of a logical block address range corresponding to an upcoming access operation. the memory system may use the logical block address range to load an associated portion of a logical-to-physical mapping from a non-volatile memory device to a volatile memory device prior to receiving a command to perform the access operation. accordingly, after the host system issues the command for the memory system to perform the access operation, the memory system may perform the access operation faster as the memory system has already loaded relevant portions of the logical-to-physical mapping associated with the access operation.
20240345775. DYNAMIC STATUS REGISTERS ARRAY_simplified_abstract_(micron technology, inc.)
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc., Reshmi Basu of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for dynamic status registers array are described. an apparatus may include one or more memory dice coupled with a data bus. the apparatus may further include a controller coupled with each of the memory dice via the data bus that is configured to transmit a first command associated with a first operation to a first memory die. the first command may assign an associated operation (e.g., the first operation) to a queue slot of a status bank that is associated with at least the first memory die. the controller may further transmit second command to the first memory die to request a status of the first operation. the controller may receive a status of the first operation via a channel (e.g., a first channel) of the data bus that is based on the assigned queue slot of the status bank.
Inventor(s): Ryan G. Fisher of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1048
Abstract: exemplary methods, apparatuses, and systems include performing an initial data integrity scan of a subset of memory at an initial time to determine an initial error rate for the subset of memory. the initial error rate and the initial time are stored. a subsequent integrity scan of the subset of memory is performed at a second time to determine a subsequent error rate for the subset of memory. a difference between the initial error rate and the subsequent error rate is determined. a difference between the initial time and the subsequent time is determined. a remedial action is selected using the difference between the initial error rate and the subsequent error rate and the difference between the initial time and the subsequent time and the remedial action is performed.
Inventor(s): Joseph M. MCCRATE of Boise ID (US) for micron technology, inc., Kirthi SHENOY of Boise ID (US) for micron technology, inc., Marco SFORZIN of Boise ID (US) for micron technology, inc., Brian M. TWAIT of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1068
Abstract: provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ecc words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ecc words within the set responsive to the valid sequence.
20240345921. DYNAMIC PARITY SCHEME_simplified_abstract_(micron technology, inc.)
Inventor(s): Gennaro Schettino of Casamicciola Terme (NA) (IT) for micron technology, inc., Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for a dynamic parity scheme are described. a memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. in some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. for example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.
Inventor(s): Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc., Ferdinando Pascale of Ottaviano (NA) (IT) for micron technology, inc., Roberto Izzi of Caserta (IT) for micron technology, inc., Marco Onorato of Villasanta (MB) (IT) for micron technology, inc., Erminio Di Martino of Quarto (NA) (IT) for micron technology, inc.
IPC Code(s): G06F11/14, G06F1/24, G06F9/4401
CPC Code(s): G06F11/1417
Abstract: methods, systems, and devices for hardware reset management for universal flash storage (ufs) are described. a ufs device may initiate a boot-up procedure that includes multiple phases. the ufs device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. the ufs device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. the ufs device may receive the second reset command during the second phase after initiating the portion of the second reset operation. the ufs device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.
20240345932. MEMORY DEVICE HEALTH MONITORING LOGIC_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Aaron P. Boehm of Boise ID (US) for micron technology, inc., Todd Jackson Plum of Boise ID (US) for micron technology, inc., Mark D. Ingram of Boise ID (US) for micron technology, inc., Scott D. Van De Graaff of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/30
CPC Code(s): G06F11/3034
Abstract: methods, systems, and devices for memory device health monitoring logic are described. in accordance with examples as disclosed herein, a memory device may include health monitoring logic configured to monitor a degradation level of the memory device. further, the health monitoring logic may include a self-check logic to monitor the degradation level of the health monitoring logic. using the health monitoring logic, the memory device may evaluate and store a health state of the memory device, which may be used to flag a fault in the memory device, among other responsive operations. additionally, using the self-check logic, the memory device may evaluate and store a health state of the health monitoring logic, which may be used to flag a fault of the previously evaluated health state of the memory device. based on the self-check flag, a host device may halt or adjust the response operations associated with the memory device.
20240345946. MEMORY SUB-SYSTEM LUN BYPASSING_simplified_abstract_(micron technology, inc.)
Inventor(s): Meng Wei of Pudong New District (CN) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a method includes assigning a respective initial credit value to each lun of a block stripe; performing an erase operation across the block stripe; reducing, in response to the erase operation, each respective initial credit value by a unit increment to provide a respective reduced credit value; refraining from programming to each lun of the block stripe having a respective reduced credit value equal to zero; and programming to each lun of the block stripe having a respective reduced credit value greater than zero.
20240345947. VIRTUAL INDEXING IN A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Xiangang Luo of Fremont CA (US) for micron technology, inc., Jianmin Huang of San Carlos CA (US) for micron technology, inc., Xiaolai Zhu of Shanghai (CN) for micron technology, inc., Deping He of Boise ID (US) for micron technology, inc., Kulachet Tanpairoj of San Mateo CA (US) for micron technology, inc., Hong Lu of Boise ID (US) for micron technology, inc., Chun Sum Yeung of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (l2p) data structure that maps a plurality of logical block addresses (lbas) associated with the l2p data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the lbas is written, and refraining from rewriting particular entries in the l2p table that correspond to lbas whose index in the first data structure is a particular value during performance of the media management operation.
Inventor(s): Daming Liu of Shanghai (CN) for micron technology, inc., Qingyuan Wang of Shanghai (CN) for micron technology, inc., Lei Cui of Shanghai (CN) for micron technology, inc., Wenjun Wu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for techniques for logical-to-physical information compression are described. in some cases, a memory system may compress a logical-to-physical (l2p) mapping to expand the quantity of physical addresses mapped by the l2p mapping. for example, if a set of consecutive entries of an uncompressed l2p mapping includes consecutive physical addresses, the memory system may compress the consecutive entries into a single entry which includes a starting physical address of the consecutive physical addresses. additionally, the memory system may include an indication of a starting logical address corresponding to the starting physical address in the compressed entry. to identify a physical address within the compressed entry, the memory system may determine an offset between a logical address corresponding to the physical address and the starting physical address using the indication, and may apply the offset to the starting physical address to determine the physical address.
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for wear leveling techniques using data characteristics are described. the described techniques provide for wear leveling across blocks of a memory system. a controller of the memory system may include additional criteria for determining a destination block for an operation, which may include a characteristic of data associated with the operation. the controller may select a destination block according to both an age of the block and the characteristic of the data. for example, the controller may select a relatively young block for data having a first characteristic and may select a relatively old block for data having a second characteristic. in some cases, the controller may partition free blocks into sub-pools based on an average age of virtual blocks (vbs) associated with each free block.
Inventor(s): Kenneth Marion Curewitz of Cameron Park CA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Samuel E. Bradshaw of Sacramento CA (US) for micron technology, inc., Sean Stephen Eilert of Penryn CA (US) for micron technology, inc., Dmitri Yudanov of Sacramento CA (US) for micron technology, inc.
IPC Code(s): G06F12/0837, G06F9/38, G06F11/14, G06F12/1009, G06F12/1027, G06N3/02
CPC Code(s): G06F12/0837
Abstract: systems, methods and apparatuses to intelligently migrate content involving borrowed memory are described. for example, after the prediction of a time period during which a network connection between computing devices having borrowed memory degrades, the computing devices can make a migration decision for content of a virtual memory address region, based at least in part on a predicted usage of content, a scheduled operation, a predicted operation, a battery level, etc. the migration decision can be made based on a memory usage history, a battery usage history, a location history, etc. using an artificial neural network; and the content migration can be performed by remapping virtual memory regions in the memory maps of the computing devices.
Inventor(s): Steven Jeffrey Wallach of Dallas TX (US) for micron technology, inc.
IPC Code(s): G06F12/0864, G06F9/30, G06F9/38, G06F13/16
CPC Code(s): G06F12/0864
Abstract: a cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. when a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. and, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Federica Cresci of Milano (IT) for micron technology, inc.
IPC Code(s): G06F12/14, G06F12/02, G06F17/16
CPC Code(s): G06F12/1441
Abstract: methods, systems, and devices for address scrambling by linear maps in galois fields are described. for instance, a device may determine a bijective matrix based on a power up condition. in some examples, the device may determine the bijective matrix based on a seed value and/or may select the matrix from among a set of bijective matrices. in some examples, the bijective matrix may have at least one column and/or one row that has at least two non-zero elements. the device may generate a first address of a first address space based on applying the matrix (e.g., each column of the matrix) to at least a portion of a second address of a second address space and may access a memory array of the device based on generating the first address.
Inventor(s): Nikesh AGARWAL of Boise ID (US) for micron technology, inc., Chandana MANJULA LINGANNA of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/42, G06F13/16
CPC Code(s): G06F13/4221
Abstract: a memory device comprises a plurality of backend interfaces that are each configured to connect to a respective media device (e.g., ddr, lpddr dram), a plurality of reliability, availability and serviceability (ras) channel datapaths with each ras channel datapath connected to one or more backend interfaces, one or more caches that are each connected to at least one ras channel datapath, and control circuitry. the control circuitry is configured to: in response to receiving a memory access request for a memory location, search a cache of the one or more caches for the requested memory location; and when, in response to the search, the requested memory location is not found in the cache, obtain the requested memory location from a media device connected to the at least one ras channel datapath. corresponding methods are also described.
Inventor(s): Walter Andrew Hubis of Westminster CO (US) for micron technology, inc.
IPC Code(s): G06F21/79, G06F21/60, G06F21/80, G06F21/10
CPC Code(s): G06F21/79
Abstract: a command to perform a data operation at a memory device is received. the command includes an encryption key tag. a first key table is accessed from local memory. the first key table includes a first set of key entries corresponding to a first set of encryption keys. the first key table is searched to determine whether it includes an entry corresponding to the encryption key tag. based on determining the first key table does not include an entry corresponding to the tag, a second key table is accessed from ram. the second key table includes a second set of key entries corresponding to a second set of encryption keys. a key entry corresponding to the encryption key tag is identified from the second key table. the key entry includes an encryption key corresponding to the encryption key tag. the command is processed using the encryption key.
Inventor(s): Febin Sunny of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc., Saideep Tiku of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06N3/084
CPC Code(s): G06N3/084
Abstract: training an artificial neural network (ann) can include receiving device design parameters corresponding to a device and operation parameters corresponding to the device. device throughput characteristics can also be received from a physics solver. device throughput predictions can be generated utilizing the device design parameters, the operation parameters, and an artificial neural network. a loss gradient can be generated utilizing the device throughput characteristics and the device throughput predictions. the ann can be trained, utilizing the loss gradient, to generate different device throughput predictions.
Inventor(s): Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Pavana Prakash of Houston TX (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06N3/098, G06Q30/04, G06V20/52
CPC Code(s): G06N3/098
Abstract: network video recorders (nvrs) can be configured to receive video data from operation in a location, train an artificial neural network (ann) surveillance model with the video data, and provide updates to the ann surveillance model to a server. the server can be configured to aggregate the updates into a federated ann surveillance model. the server can deploy the federated ann surveillance model to the nvrs. the server can train, via transfer learning based on the federated ann surveillance model, a different ann surveillance model for a different nvr in a different location. the server can deploy the different ann surveillance model to the different nvr.
20240347081. PULSE BASED MULTI-LEVEL CELL PROGRAMMING_simplified_abstract_(micron technology, inc.)
Inventor(s): Hernan A. Castro of Shingle Springs CA (US) for micron technology, inc., Mattia Boniardi of Cormano (IT) for micron technology, inc., Innocenzo Tortorelli of Cernusco Sul Naviglio (IT) for micron technology, inc.
IPC Code(s): G11C7/10, G11C16/34
CPC Code(s): G11C7/1039
Abstract: methods, systems, and devices for pulse based multi-level cell programming are described. a memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. the memory device may apply a first pulse with a first polarity to the memory cell to store a set or reset state to the memory cell based on identifying the intermediate logic state. as such, the memory device may identify a threshold voltage of the memory cell that stores the set or reset state. the memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the set or reset state. in some examples, the quantity of pulses may have a second polarity different than the first polarity.
Inventor(s): Jie Yang of Shanghai (CN) for micron technology, inc., Xu Zhang of Shanghai (CN) for micron technology, inc., Bin Zhao of Shanghai (CN) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/14
CPC Code(s): G11C7/1084
Abstract: methods, systems, and devices for mitigating memory die misalignment are described. a memory system may receive a command to write data to a memory device including a memory die. the memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. if the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. for example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. to mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.
Inventor(s): Robert W. Mason of Boise ID (US) for micron technology, inc., Pitamber Shukla of Boise ID (US) for micron technology, inc., Steven Michael Kientz of Westminster CO (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/22
CPC Code(s): G11C7/1096
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations including initializing the memory device; selecting at least one sample management unit on the memory device; performing a calibration operation on the sample management unit to determine a duration value reflecting a duration during which the memory device was powered down; adjusting an accumulator value based on the duration value; determining a read voltage value based on the accumulator value; and performing a read operation using the read voltage value.
20240347088. VARIABLE PAGE SIZE ARCHITECTURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Corrado Villa of Sovico (MB) (IT) for micron technology, inc.
IPC Code(s): G11C8/16, G11C7/04, G11C7/10, G11C8/10, G11C29/18
CPC Code(s): G11C8/16
Abstract: methods, systems, and devices for operating a memory array with variable page sizes are described. the page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. a memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. the addressing scheme may be modified based on the page size. the logic row address may identify the memory sections to be accessed in parallel. the memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.
20240347096. Usage-Based Disturbance Counter Clearance_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Mark Kalei Hadrick of Boise ID (US) for micron technology, inc., HyunYoo Lee of Boise ID (US) for micron technology, inc., KeunSoo Song of Meridian ID (US) for micron technology, inc., John Christopher Sancon of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/4096
CPC Code(s): G11C11/40615
Abstract: apparatuses and techniques for implementing usage-based disturbance counter clearance are described. in example implementations, a memory device includes a memory array having multiple rows. the memory device also includes multiple usage-based disturbance counters that are associated with the memory array. the memory device further includes logic that performs a refresh operation on a row of the multiple rows responsive to a refresh command. the logic also clears a usage-based disturbance counter of the multiple usage-based disturbance counters responsive to the refresh command. here, the usage-based disturbance counter stores a quantity of accesses to the row of the multiple rows. this can reduce a frequency of performing usage-based disturbance mitigation procedures that would otherwise be applied to the multiple usage-based disturbance counters, thereby saving power and avoiding denial-of-service periods with the memory array.
20240347098. Usage-Based Disturbance Mitigation_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/4093
CPC Code(s): G11C11/40618
Abstract: apparatuses and techniques for implementing usage-based disturbance mitigation are described. in some examples, a total mitigation pump pair (tmpp) queue and a dynamic mitigation threshold (mt) can improve the mitigation efficiency of usage-based disturbances while reducing power requirements and increasing performance impact. in various aspects, the tmpp queue is a first-in first out (fifo) queue useful to implement the described disturbance mitigation techniques.
Inventor(s): Yuan He of Boise ID (US) for micron technology, inc., Yang Lu of Boise ID (US) for micron technology, inc., Dong Pan of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4076, G11C11/406, G11C11/408
CPC Code(s): G11C11/4076
Abstract: a value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. a timer may provide a periodic signal that increments a counter to update the value. the updated value may then be written back to the word line. in some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.
Inventor(s): William Chad Waldrop of Allen TX (US) for micron technology, inc., Ki-Jun Nam of Allen TX (US) for micron technology, inc., Won Joo Yun of Boise ID (US) for micron technology, inc., Shingo Mitsubori of Inagi (JP) for micron technology, inc.
IPC Code(s): G11C11/4093
CPC Code(s): G11C11/4093
Abstract: systems and methods are provided for a memory device that includes a decision feedback equalizer (dfe) reset generator configured to transmit a dfe reset signal to reset taps of a dfe. the memory device also includes an input buffer. the input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. the input buffer also includes a dfe reset branch configured to reset the taps for the dfe based on the dfe reset signal. moreover, resetting the taps using the dfe reset branch does not reset output data of the data branch.
20240347107. SOCKET DESIGN FOR A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Amitava Majumdar of Boise ID (US) for micron technology, inc., Radhakrishna Kotti of Boise ID (US) for micron technology, inc., Rajasekhar Venigalla of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C13/00, H01L23/522, H01L23/528, H10B63/00, H10N70/00, H10N70/20
CPC Code(s): G11C13/0028
Abstract: methods, systems, and devices supporting a socket design for a memory device are described. a die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. the word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. for example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.
Inventor(s): Jian Huang of Union City NJ (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/26, G11C29/44, G11C29/12
CPC Code(s): G11C16/102
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits programmed in the first logical level fails to satisfy a threshold criterion, performing a write operation on the second wordline to program second data.
Inventor(s): Wei Wang of Fremont CA (US) for micron technology, inc., Seungjune Jeon of Santa Clara CA (US) for micron technology, inc., Yang Liu of San Jose CA (US) for micron technology, inc., Charles See Yeung Kwong of Redwood City CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04
CPC Code(s): G11C16/3431
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations comprising identifying one or more valid pages of a first block, the first block being associated with a first management unit of the memory device; responsive to determining that a data integrity metric value associated with the first block satisfies a threshold criterion, causing the memory device to copy data from the one or more valid pages to a destination set of pages associated with a second block of a second management unit; marking each page of the one or more valid pages as invalid; and performing an error correcting operation, using one or more invalid pages of the first block, on a third block of the first management unit.
Inventor(s): Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10
CPC Code(s): G11C16/3459
Abstract: embodiments disclosed can include identifying wordline groups where each wordline group is associated with a corresponding default program verify (pv) voltage for each programming level, and determining, for each wordline group, a maximum read window budget (rwb) increase. they can further include defining a target aggregate rwb increase amount based on the maximum rwb increase, and determining, for each wordline group, a minimum number of memory cell programming level groups with corresponding pv voltage offsets sufficient to reach the target aggregate rwb increase amount. the embodiments can also include grouping the programming levels of a specified memory cell into the minimum number of programming level, and applying, based on the specific programming level group containing a target programming level, a corresponding pv voltage offset during a memory cell access operation.
20240347123. CENTRALIZED ERROR CORRECTION CIRCUIT_simplified_abstract_(micron technology, inc.)
Inventor(s): Taeksang Song of San Jose CA (US) for micron technology, inc., Saira Samar Malik of Lafayette IN (US) for micron technology, inc., Hyunyoo Lee of Boise ID (US) for micron technology, inc., Chinnakrishnan Ballapuram of San Jose CA (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C29/12, G11C29/44
CPC Code(s): G11C29/42
Abstract: methods, systems, and devices for centralized error correction circuit are described. an apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). the apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). the interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.
Inventor(s): Scott E. SCHAEFER of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/46, G11C7/10, G11C29/12
CPC Code(s): G11C29/46
Abstract: implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. a memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. the memory device may identify a first data mask inversion (dmi) bit of the memory device that is associated with a first rank of the memory device and a second dmi bit of the memory device that is associated with a second rank of the memory device. the memory device may set the first dmi bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. the memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first dmi bit to the first value.
Inventor(s): Akira Goda of Setagaya (JP) for micron technology, inc., Kishore K. Muchherla of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/50
CPC Code(s): G11C29/50004
Abstract: an apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. a controller is configured to: apply a first read pass voltage to unselected access lines of the first group of access lines in association with performing a sensing operation on a selected access line of the first group of access lines; and determine a second read pass voltage to be applied to the second group of access lines in association with performing the sensing operation on the selected access line of the first group. the second read pass voltage is determined by: determining an amount of time that the second group of memory cells has been in a programmed state; or performing a scan to determine a threshold voltage (vt) characteristic corresponding to the second group of memory cells; or both.
Inventor(s): Dongxiang Liao of Cupertino CA (US) for micron technology, inc., Tomer Tzvi Eliash of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/02
CPC Code(s): G11C29/52
Abstract: a method for monitoring health of a die in a memory device and dynamically adjusting a device parameter. the method includes receiving a request for performing a memory access operation on a first data unit of a memory device, and determining a value of a media state metric of the first data unit. the method further includes modifying a device parameter of the first data unit to form a modified device parameter in response to determining that the value of the media state metric of the first data unit is greater than a predetermined threshold value, and performing, using the modified device parameter, the memory access operation on the first data unit.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Dave Scott Ebsen of Minnetonka MN (US) for micron technology, inc., Lakshmi Kalpana Vakati of San Jose CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc., Sanjay Subbarao of Irvine CA (US) for micron technology, inc., Vivek Shivhare of Milpitas CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/02
CPC Code(s): G11C29/52
Abstract: methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. a deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. the current block is composed of multiple decks. the deck programming order is an order in which the multiple decks are programmed. the multiple decks programmed according to the determined deck programming order.
20240347413. THERMALLY REGULATED SEMICONDUCTOR DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Chen Yu Huang of Taichung (TW) for micron technology, inc., Chong Leong Gan of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/373, H01L23/00, H01L23/31, H01L23/498, H01L25/10, H10B80/00
CPC Code(s): H01L23/373
Abstract: a semiconductor device assembly is provided. the semiconductor device assembly can include a substrate and one or more semiconductor dies. the semiconductor device assembly can further include a thermally conductive material (e.g., carbon nanotubes, graphene) capable of dissipating heat from the semiconductor device assembly. in doing so, a thermally regulated semiconductor device can be assembled.
Inventor(s): Pengyuan Zheng of Boise ID (US) for micron technology, inc., David Ross Economy of Boise ID (US) for micron technology, inc., Yongjun J. Hu of Boise ID (US) for micron technology, inc., Kent H. Zhuang of Boise ID (US) for micron technology, inc., Robert K. Grubbs of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/373, H01L21/02, H01L21/768, H01L23/535
CPC Code(s): H01L23/3736
Abstract: methods, systems, and devices related to a memory device with a thermal barrier are described. the thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. the thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. the thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.
Inventor(s): Lingyu Kong of Singapore (SG) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc., Indra V. Chary of Boise ID (US) for micron technology, inc., Shuangqiang Luo of Boise ID (US) for micron technology, inc., Sok Han Wong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/535, H01L21/768, H01L23/00, H01L23/528, H10B41/27, H10B43/27
CPC Code(s): H01L23/535
Abstract: a microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. related memory devices, electronic systems, and methods are also described.
Inventor(s): Chen-Yu HUANG of Taichung City (TW) for micron technology, inc., Chong Leong GAN of Butterworth (MY) for micron technology, inc.
IPC Code(s): H01L23/556, H01L23/00, H01L23/31, H01L23/498, H01L25/065, H10B80/00
CPC Code(s): H01L23/556
Abstract: implementations described herein relate to various semiconductor device assemblies. in some implementations, a semiconductor device assembly may include a substrate, a plurality of electrical contacts disposed on an outer surface of the substrate, a solder resist disposed on the outer surface of the substrate and including an opening defined by a plurality of edges and exposing the plurality of electrical contacts, and an alpha particle shield disposed proximate to at least one edge, of the plurality of edges.
Inventor(s): Jaspreet S. Gandhi of San Jose CA (US) for micron technology, inc., Michel Koopmans of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L21/768, H01L23/00, H01L23/367, H01L23/48, H01L25/00
CPC Code(s): H01L25/0657
Abstract: systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. in one embodiment, the thermal pads may be in direct contact with the semiconductor dies. heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). in some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (ubm) structures.
20240347525. APPARATUS INCLUDING STANDARD CELL_simplified_abstract_(micron technology, inc.)
Inventor(s): Takamitsu Onda of Tokyo (JP) for micron technology, inc., Tomohiro Kitano of Tokyo (JP) for micron technology, inc.
IPC Code(s): H01L27/02, H01L23/522, H01L27/092
CPC Code(s): H01L27/0207
Abstract: according to one or more embodiments of the disclosure, an apparatus comprises: a semiconductor substrate including a first region, a second region, and a third region between the first region and the second region; and a plurality of wiring layers, at least in part, above the third region. the first region includes first transistors of first conductivity-type. the second region includes second transistors of second conductivity-type. the wiring layers include a lower wiring layer, a middle wiring layer, and an upper wiring layer. one or more wirings in the middle wiring layer elongate through the third region in a first direction to connect ones of sources and drains of the first transistors and corresponding ones of sources and drains of the second transistors. one or more wirings in the lower wiring layer elongate in the third region in a second direction perpendicular to the first direction to connect ones of the wirings of the middle wiring layer and corresponding ones of the wirings of the middle wiring layer.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Scott L. Light of Boise ID (US) for micron technology, inc., Efe S. Ege of Boise ID (US) for micron technology, inc., Chunhua Yao of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/0335
Abstract: a method of forming a microelectronic device includes forming a first dielectric stack over a semiconductor base structure including pillar structures separated by filled isolation trenches. digit line contacts are formed to partially vertically extend through the first dielectric stack and into digit line contact regions of the pillar structures. digit lines are formed over and in contact with the digit line contacts, and partially vertically extend through the first dielectric stack. a second dielectric stack is formed over the digit lines and the first dielectric stack. storage node contacts are formed to vertically extend partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions of the pillar structures. redistribution layer structures are formed over and in contact with the storage node contacts, and partially vertically extend through the second dielectric stack. microelectronic devices, memory devices, and electronic systems are also described.
Inventor(s): Naokazu Murata of Higashihiroshima (JP) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/09
Abstract: an apparatus includes: a semiconductor substrate having a first region, a second region and a third region; a first wiring above the first region of the semiconductor substrate; a second wiring above the second region of the semiconductor substrate; a third wiring above the third region of the semiconductor substrate; and a first insulating film on each of the first, second and third wirings. a height of an upper surface of the first wiring is lower than a height of an upper surface of the second wiring; wherein the height of an upper surface of the second wiring is lower than a height of an upper surface of the third wiring each of portions of the first insulating film disposed above the first, second and third wirings has an equal film thickness.
Inventor(s): Yiping Wang of Boise ID (US) for micron technology, inc., Collin Howder of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. the insulative tiers comprise a first silicon oxide. the insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. the stair-step region comprises a flight of stairs. the stairs individually comprise a tread comprising conductive material of one of the conductive tiers. individual of the treads comprise a second silicon oxide directly above the conductive material of the one conductive tier. the second silicon oxide comprises one or more of boron and phosphorus at a total concentration that is greater than a total concentration of one or more of boron and phosphorus, if any, that is in the first silicon oxide that is directly below the second silicon oxide. a conductive-via construction extends downwardly from and directly below the conductive material of the individual treads to circuitry that is directly below the stack. the conductive-via construction comprises conductor material that directly electrically couples together the conductive material of one of the individual treads and the circuitry that is directly below the stack. methods are disclosed.
Micron Technology, Inc. patent applications on October 17th, 2024
- Micron Technology, Inc.
- G06F3/06
- G06F12/02
- CPC G06F3/0608
- Micron technology, inc.
- CPC G06F3/0611
- CPC G06F3/0625
- G06F1/3234
- G06F1/3296
- CPC G06F3/0634
- CPC G06F3/0647
- CPC G06F3/0652
- CPC G06F3/0655
- CPC G06F3/0659
- G06F11/10
- G06F11/07
- CPC G06F11/1048
- CPC G06F11/1068
- G06F11/14
- G06F1/24
- G06F9/4401
- CPC G06F11/1417
- G06F11/30
- CPC G06F11/3034
- CPC G06F12/0246
- G06F12/0837
- G06F9/38
- G06F12/1009
- G06F12/1027
- G06N3/02
- CPC G06F12/0837
- G06F12/0864
- G06F9/30
- G06F13/16
- CPC G06F12/0864
- G06F12/14
- G06F17/16
- CPC G06F12/1441
- G06F13/42
- CPC G06F13/4221
- G06F21/79
- G06F21/60
- G06F21/80
- G06F21/10
- CPC G06F21/79
- G06N3/084
- CPC G06N3/084
- G06N3/098
- G06Q30/04
- G06V20/52
- CPC G06N3/098
- G11C7/10
- G11C16/34
- CPC G11C7/1039
- G11C7/14
- CPC G11C7/1084
- G11C7/22
- CPC G11C7/1096
- G11C8/16
- G11C7/04
- G11C8/10
- G11C29/18
- CPC G11C8/16
- G11C11/406
- G11C11/4096
- CPC G11C11/40615
- G11C11/4093
- CPC G11C11/40618
- G11C11/4076
- G11C11/408
- CPC G11C11/4076
- CPC G11C11/4093
- G11C13/00
- H01L23/522
- H01L23/528
- H10B63/00
- H10N70/00
- H10N70/20
- CPC G11C13/0028
- G11C16/10
- G11C16/08
- G11C16/26
- G11C29/44
- G11C29/12
- CPC G11C16/102
- G11C16/04
- CPC G11C16/3431
- CPC G11C16/3459
- G11C29/42
- CPC G11C29/42
- G11C29/46
- CPC G11C29/46
- G11C29/50
- CPC G11C29/50004
- G11C29/52
- G11C29/02
- CPC G11C29/52
- H01L23/373
- H01L23/00
- H01L23/31
- H01L23/498
- H01L25/10
- H10B80/00
- CPC H01L23/373
- H01L21/02
- H01L21/768
- H01L23/535
- CPC H01L23/3736
- H10B41/27
- H10B43/27
- CPC H01L23/535
- H01L23/556
- H01L25/065
- CPC H01L23/556
- H01L23/367
- H01L23/48
- H01L25/00
- CPC H01L25/0657
- H01L27/02
- H01L27/092
- CPC H01L27/0207
- H10B12/00
- CPC H10B12/0335
- CPC H10B12/09
- CPC H10B43/27
