Micron Technology, Inc. patent applications on May 30th, 2024
Patent Applications by Micron Technology, Inc. on May 30th, 2024
Micron Technology, Inc.: 48 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (19), G06F3/0679 (11), G06F3/0659 (9), G06F3/0604 (8), G06F3/0655 (6)
With keywords such as: memory, data, device, material, portion, cells, host, include, based, and systems in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20240176491.ERASE OPERATION FOR A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Sridhar Prudviraj Gunda of Bangalore (IN) for micron technology, inc., Amiya Banerjee of Bangalore (IN) for micron technology, inc., Ritesh Tiwari of Bangalore (IN) for micron technology, inc., Shreesha Prabhu of Singapore (SG) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for an erase operation for a memory system are described. the memory system may perform, on a block of memory cells, a first portion of an erase operation. after performing the first portion of the erase operation, the memory system may receive a write command to write data to the block of memory cells. in response to receiving the write command, the memory system may determine whether a threshold voltage of the block of memory cells satisfies a threshold. in response to determining the that the threshold voltage satisfies the threshold, the memory system may perform a second portion of the erase operation on the block of memory cells. as such, the memory system may write the data to the block of memory cells in response to performing the second portion of the erase operation.
Inventor(s): Zhongguang XU of San Jose CA (US) for micron technology, inc., Ronit Roneel PRAKASH of Hiratsuka (JP) for micron technology, inc., Murong LANG of San Jose CA (US) for micron technology, inc., Ching-Huang LU of Fremont CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. the portion of memory is erased in response to determining that the portion of memory is invalid. a request to move an additional portion of memory to a free pool from the garbage pool is received. a free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. the erased portion of memory is moved from the garbage pool to the free pool.
Inventor(s): Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: implementations described herein relate to host device initiated low temperature thermal throttling. a memory device may receive, from a host device, a low temperature thermal throttling command that indicates for the memory device to initiate a thermal throttling operation based on a temperature of the memory device not satisfying a temperature threshold. the low temperature thermal throttling command may indicate an amount of dummy data to be moved from the host device to a particular location of the memory device associated with the thermal throttling operation. the memory device may perform the thermal throttling operation based on moving the dummy data from the host device to the particular location of the memory device. the memory device may complete the thermal throttling operation based on moving the amount of data from the host device to the particular location of the memory device.
20240176507.TWO-STAGE EMERGENCY DATA STORING OPERATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Steffen BUCH of Taufkirchen (DE) for micron technology, inc., Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: implementations described herein relate to a two-stage emergency data storing operation. in some implementations, a memory device may detect a power loss notification signal that indicates a power loss condition of the memory device. the memory device may read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage. the first data storing stage may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss. the memory device may initiate the data storing operation and may selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhongguang Xu of San Jose CA (US) for micron technology, inc., Ronit Roneel Prakash of Kanagawa Prefecture (JP) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system with a memory device and a processing device operatively coupled with the memory device, to perform operations including identifying a lifecycle state associated with a segment of the memory device, selecting, based on the lifecycle state, an erase policy for performing an erase operation with respect to the segment, and causing the erase operation to be performed with respect to the segment in accordance with the erase policy.
Inventor(s): Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Eyal En Gad of Highland CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a of bit flipping (bf) decoder decodes codewords using a first set of bf thresholds. a first minimum number of iterations of decoding performed on the codewords is determined to achieve a first target decoding rate. codewords are decoded using a second set of bf thresholds. the first set of bf thresholds are more likely to cause bit flips than the second set of bf thresholds. a second minimum number of iterations of decoding performed on the codewords is determined to achieve a second target decoding rate. bits in a codeword are flipped using the first set of bf thresholds for the first minimum number of iterations. bits are flipped in the codeword using the second set of bf thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.
Inventor(s): Gregory Alan BECKER of Austin TX (US) for micron technology, inc., Alexander TOMLINSON of Austin TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: in some implementations, a memory device may identify a key-value pair set associated with a root node, wherein the key-value pair set includes a plurality of key-value pairs, and wherein the root node is associated with a log-structured merge-tree. the memory device may determine that a plurality of keys in the key-value pair set are associated with a leaf node based on the plurality of keys corresponding to an edge key associated with the leaf node, wherein the leaf node is associated with the log-structured merge-tree. the memory device may associate the key-value pair set with the leaf node based on a metadata update of the key-value pair set, wherein the key-value pair set becomes decoupled from the root node.
Inventor(s): Gregory Alan BECKER of Austin TX (US) for micron technology, inc., Alexander TOMLINSON of Austin TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: in some implementations, a memory device may determine, from a list of key-value pair sets, a key-value pair set. the memory device may identify, from the key-value pair set selected from the list of key-value pair sets, a first key that is included in at least one other key-value pair set from the list of key-value pair sets. the memory device may identify, from the key-value pair set selected from the list of key-value pair sets, a second key that is not included in at least one other key-value pair set from the list of key-value pair sets. the memory device may form a new key-value pair set that excludes the first key and includes the second key. the memory device may replace the key-value pair set selected from the list of key-value pair sets with the new key-value pair set.
Inventor(s): Binbin Huo of Taufkirchen (DE) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for parameter table protection for a memory system are described. upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. the error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.
Inventor(s): James Brian Johnson of Boise ID (US) for micron technology, inc., Brent Keeth of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Eiichi Nakano of Boise ID (US) for micron technology, inc., Amy Rae Griffin of Boise ID (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F1/06
Abstract: methods, systems, and devices for techniques for coupled host and memory dies are described. for example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of the circuitry configured to access the set of memory arrays, and a second die may include a second portion of the circuitry configured to access the set of memory arrays. the first portion and the second portion of the circuitry configured to access a set of memory arrays may be communicatively coupled between the dies using various interconnection techniques, such as a fusion of conductive contacts of the respective memory dies. in some examples, the second die may also include the host itself (e.g., a host processor).
Inventor(s): Eldhose PETER of Bengaluru (IN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and apparatuses include receiving a lifetime hint for a zone, where the lifetime hint is an estimation of a length of time user data for the zone will be valid. it is determined that the zone has been fully written to a source memory region. a destination memory region is determined to store the user data for the zone using the lifetime hint. the user data for the zone is moved from the source memory region to the destination memory region.
Inventor(s): Michael Winterfeld of Firestone CO (US) for micron technology, inc., Guanying Wu of Longmont CO (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/06
Abstract: quad-to-single (q2s) data structure comprising a plurality of entries maintained on a volatile memory device. each q2s mapping entry, identified by a physical address of a quad-level cell (qlc) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. responsive to programming at least one single-level cell (slc) block stripe of a plurality of slc block stripes with data to be programmed to a qlc block stripe, an entry for an identification of the qlc block stripe to be programmed and an entry for each physical address of the at least one slc block stripe of the plurality of slc block stripes programmed with data to be programmed to the qlc block stripe is appended to a linked list corresponding to a q2s mapping entry associated with the qlc block stripe to be programmed.
Inventor(s): David Aaron Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for techniques for improved write performance modes are described. a memory system and a host system may support a high performance mode to write data to the memory system. for example, the host system may provision a dedicated logical unit of the memory system. upon detecting an urgent situation, the host system may transmit a command to the memory system to enter the high performance mode. in response to the command, the memory system may abort ongoing operations, such as internal memory management operations. additionally, the host system and the memory system may configure operational parameters to increase the speed of write operations, such as a trim set for writing data to the logical unit, a bit rate of data transfer between the host system and the memory system, clock speeds of the memory system, or a combination thereof.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a method to provide network storage services to a remote host system, including: generating, from packets received from the remote host system, first control messages and first data messages; buffering, in a random-access memory of a memory sub-system, the first control messages for a local host system to fetch the first control messages, process the first control messages, and generate second control messages; sending the first data messages to a storage device of the memory sub-system without the first data messages being buffered in the random-access memory; communicating the second control messages generated by the local host system to the storage device of the memory sub-system; and processing, within the storage device, the second control messages and the first data messages to provide the network storage services.
20240176536.PARTITIONS WITHIN BUFFER MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Minjian Wu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: partitions within buffer memory, such as may be used as a cyclic buffer for caching or storage of time based telemetric sensor data, can be operated with different programming characteristics to provide a balance between total memory sub-system capacity and endurance. received first time based telemetric sensor data can be written to one or more partitions or sub-partitions with different programming characteristics. one programming characteristic can provide a lesser data density and greater data endurance than another programming characteristic. the programming characteristic can be data density per memory cell. the different partitions or sub-partitions can be written to randomly, with equal probability, or another metric.
20240176547.ACCESS TRACKING IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Cagdas Dirik of Indianola WA (US) for micron technology, inc., Robert M. Walker of Raleigh NC (US) for micron technology, inc., Elliott C. Cooper-Balis of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02, G06F12/12
Abstract: an access tracker configured to receive a request to access a page, determine whether a page identification (id) associated with the page is in the access tracker, increment an access count of the page in response to determining the page id is in the access tracker, sort a number of page ids based on an access count of each page id, and determine whether a different page is hot or cold in response to sorting the number of page ids.
20240176548.EMERGENCY DATA STORING OPERATION SELECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco REDAELLI of Munich (DE) for micron technology, inc., Steffen BUCH of Taufkirchen (DE) for micron technology, inc.
IPC Code(s): G06F3/06, G06F1/30
Abstract: implementations described herein relate to emergency data storing operation selection. in some implementations, a memory device may be configured to receive a peripheral component interconnect power loss notification (pln) signal and a peripheral component interconnect express reset (perst) signal. the memory device may be configured to determine whether to initiate a first data storing operation or a second data storing operation based on the perst signal state based on a falling edge of the pln signal. the memory device may be configured to selectively initiate the first data storing operation or the second data storing operation. the first data storing operation may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing operation may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss.
Inventor(s): Roberto Izzi of Caserta (IT) for micron technology, inc., Luca Porzio of Casalnuovo (IT) for micron technology, inc., Sean L. Manion of Boise ID (US) for micron technology, inc., Massimo Zucchinali of Torre Boldone (IT) for micron technology, inc., Bryan D. Butler of Boise ID (US) for micron technology, inc., Andrea Vigilante of Milano (IT) for micron technology, inc., Marco Onorato of Villasanta (IT) for micron technology, inc., Alfredo Palazzo of Monza (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for latency reduction of boot procedures for memory systems are described. a memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. the memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. upon completing the initialization process, the flag may be set to the first value. parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. the memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.
Inventor(s): Gowrishankar Gajendiran of Bangalore (IN) for micron technology, inc., Amiya Banerjee of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for transferring valid data using a system latch are described. the operations described herein may include sensing valid data across a first set of planes associated with a first set of memory blocks of a non-volatile memory system. in response to sensing the valid data, the valid data may be stored to a latch of the non-volatile memory system based on an order of sensing the valid data across the first set of planes. the valid data may be written across a second set of planes associated with a second set of memory blocks of the non-volatile memory system based on the order of sensing the valid data across the first set of planes. in some cases, writing the valid data from the latch may be based on determining that a threshold associated with a duration corresponding to sensing the valid data has been satisfied.
20240176697.Controller-Level Memory Repair_simplified_abstract_(micron technology, inc.)
Inventor(s): Smruti Subhash Jhaveri of Boise ID (US) for micron technology, inc., Hyun Yoo Lee of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F13/42
Abstract: described apparatuses and methods facilitate sharing redundant memory portions at a controller-level to enable memory repair between two or more memory blocks. each memory die of multiple memory dies can include, for instance, multiple spare rows for use if a row of a memory array has a faulty bit. if a memory die has more faults than spare rows, the memory die cannot repair the additional faults. this document describes a controller that can inventory unrepaired faults and available spare rows across multiple memory dies. the controller can then “borrow” a spare row from a second memory die that has an available one and “share” the spare row with a first memory die that has a fault than it cannot repair. the controller can remap a memory access request targeting the row with the unrepaired fault in the first memory die to a spare row in the second memory die.
Inventor(s): Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Patrick Khayat of San Diego CA (US) for micron technology, inc., Sampath Ratnam of San Jose CA (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Jiangang Wu of Milpitas CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Scott E. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
Abstract: apparatuses, systems, and methods for enhanced metadata information. the memory array includes a number of column planes and an extra column plane. a memory device is set in an �4 single-pass operational mode. in this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. an error correction code circuit (ecc) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. in this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Jameer Mulani of Mulani (IN) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
Abstract: methods, systems, and devices to enhance read performance for memory data word decoding using power allocation based on error pattern detection in both qlc and tlc in both qlc and tlc products are described. a plurality of data words may be processed using a first decoder engine of a decoder of a memory device according to a first power setting. the decoder may detect a pattern of errors in the plurality of data words. the decoder may further communicate a status signal based on detecting the pattern of errors. the resource manager may allocate based on the status signal, a second amount of power credits to the decoder. the decoder may process a portion of the plurality of data words using a second decoder engine according to the second amount of power credits.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/0815
Abstract: a host system connected to a memory sub-system via a connection to configure memory services provided by the memory sub-system to the host system over the connection. the memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. in response to a request from the host system over the connection, the memory sub-system can update configuration data of the memory services and provide the memory services according to the parameters specified by the request. the request can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access. the request can be implemented via a store instruction, a write command, or another command having another command identifier.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/0871, G06F12/0815
Abstract: a host system connected to a memory sub-system via a connection to query memory attachment capabilities of the memory sub-system in providing memory services over the connection. the memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. in response to the query, the memory sub-system can provide a response containing data indicative of memory attachment capabilities of the memory sub-system. the host system can configure the memory services of the memory sub-system, such as a solid-state drive, based on the data received as a response to the query. the query and response can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access.
Inventor(s): David A. Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/1009, G06F12/0846
Abstract: an apparatus can include a memory device and a controller coupled thereto. the controller can be configured to maintain a logical-to-physical (l2p) table including logical block addresses (lbas). the lbas are organized as partitions of the l2p table. each partition of the l2p table includes a respective subset of the lbas. the controller can be configured to monitor, for each partition of the lba, a quantity of read/modify/write (r/m/w) operations and a quantity of read operations performed on the memory device at the respective subset of the lbas. the controller can be configured to for each partition of the l2p table and based on the quantities of r/m/w operations and read operations performed on the memory device at the respective subset of the lbas, adjust a value of respective granularities of the l2p table.
Inventor(s): Olivier Duval of Pacifica CA (US) for micron technology, inc.
IPC Code(s): G06F21/33, G06F8/65, G06F9/54, G06F21/12, G06F21/44, H04L9/32, G06F21/10
Abstract: methods, systems, and devices for authenticating a device using a remote host are described. in some systems, a management server may identify a software update for a device and transmit a notification that the software update is sent to the device. in some cases, the system may also include a field server. the field server may receive the notification and set a flag, in a memory, that indicates an association between the device and the software update. the field server may receive, from the device, a connection request that includes a certificate associated with a key for authenticating the device and accept the key as valid based on the flag indicating the update to the software.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): G06F21/78, G06F21/54, G06F21/60
Abstract: the disclosed embodiments relate to detecting malicious data and in particular to a method that includes loading data from a storage device; loading secure identifying data (sid) associated with the data from a write-protected region of the storage device, the sid including a digest and at least one metadata field; comparing the at least one metadata field in the sid to a corresponding metadata field of the data; computing a current digest of the data; comparing the current digest to the digest in the sid; and validating the data when the at least one metadata field in the sid matches the corresponding metadata field of the data and the current digest matches the digest in the sid.
Inventor(s): JEREMY CHRITZ of SEATTLE WA (US) for micron technology, inc., DAVID HULTON of SEATTLE WA (US) for micron technology, inc.
IPC Code(s): G06F21/79, G06F12/14, G06F13/16, G06F21/31, G06F21/60, H04L9/06
Abstract: examples of systems and method described herein or generating, in a memory controller and/or memory device, access codes for memory regions of the memory device using authentication logic, and for accessing the memory device using the access codes. for example, a memory controller and/or a coupled memory device may generate access codes that a host computing device may include in a memory access request to access one or more memory regions of the memory device. data read or written at the memory device may in some examples only be accessed in accordance with the access codes for memory regions of the memory device. accordingly, the systems and methods described herein may provide security for specific memory regions of a memory device because the access code are updated periodically (e.g., based on obtained reset indication) or in accordance with an updated count value from a counter.
Inventor(s): James S. Rehmeyer of Boise ID (US) for micron technology, inc., Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C5/02, G11C5/04, G11C29/50
Abstract: methods of optimizing the placement of memories in a memory device including a substrate and an electrical component, and associated devices and systems, are disclosed herein. a representative method includes first testing the memories to determine at least one parameter for each of the memories indicating an ability of the memory to process signals from the electrical component. the method can further include labeling each memory with a label based on the parameter, the labels including at least a first label and a second label. the first label can indicate that the memories with the first label are better able to process signals from the electrical component than the memories with the second label. the method can further include electrically coupling the memories to the substrate such that the memories with the second label are positioned closer to the electrical component than the memories with the first label.
Inventor(s): Hirokazu Ato of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C7/08, G11C7/02, G11C7/10
Abstract: apparatuses and methods including circuits in gap regions of a memory array are disclosed. an example apparatus includes first and second memory mats adjacent along a first direction, and further includes a region between the first and second memory mats along the first direction. the region includes a local input/output (lio) line that extends along a second direction perpendicular to the first direction through the region, and further includes a lio driver and a lio precharge circuit coupled to the lio line. the lio driver is configured to drive the lio line to data voltage levels based on data read from memory cells or based on data to be written to memory cells, and the lio precharge circuit is configured to provide a lio precharge voltage to the lio lines.
20240177745.Sharable Usage-Based Disturbance Circuitry_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Yuan He of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/08, G11C7/10, G11C29/52
Abstract: apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. in example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. with the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.
20240177755.VOLATILE DATA STORAGE IN NAND MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., Sheyang Ning of San Jose CA (US) for micron technology, inc., Lawrence Celso Miranda of San Jose CA (US) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C11/00, G06F12/02, G11C16/04
Abstract: memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells
Inventor(s): Robert Winston MASON of Boise ID (US) for micron technology, inc., Phani Raghavendra Yasasvi GANGAVARAPU of Bengaluru (IN) for micron technology, inc., Pitamber SHUKLA of Boise ID (US) for micron technology, inc., Qun SU of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C29/02
Abstract: methods, systems, and apparatuses include determining a read counter for a portion of memory of a memory device satisfies a read threshold. a weighted subportion identifier for the portion of memory is selected in response to the read counter satisfying the threshold. the weighted subportion identifier is selected probabilistically, a probability of selection based on defectivity information for subportions of memory of the portion of memory. a subportion of memory is determined using the weighted subportion identifier. a data validity scan is performed on the subportion of memory.
20240177762.SELECTABLE MEMORY SYSTEM ERASE FUNCTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Frank F. Ross of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406
Abstract: methods, systems, and devices for selectable memory system erase function are described. a user of a multitenancy memory system may request to vacate the memory system. a multitenancy controller may transmit an indication to erase data from a memory region associated with the user to a controller of the memory system. the controller may set bits of a mode register corresponding to the memory region to an erase value and other bits of the mode register corresponding to other memory regions to a normal value. the data may be erased from the memory region during the refresh cycle, while data from the other memory regions may be normally refreshed, according to the value of the bits in the mode register. the controller may indicate to the multitenancy controller that the data has been erased, and the multitenancy controller may enable the user to vacate from the memory system.
Inventor(s): Hernan Castro of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G11C13/00, G06F7/544, G11C19/36
Abstract: systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. in one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. voltages are applied to the memory cells. each voltage represents one or more input bits to be multiplied by one of the weights. output currents from the memory cells are accumulated in a common bitline. a sum of the output currents is digitized to provide a digital result. the digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Jun Wan of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/28, G11C16/08, G11C16/24
Abstract: a method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. the method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. it can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.
Inventor(s): Riccardo Muzzetto of Arcore (MB) (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc., Umberto Di Vincenzo of Capriate San Gervasio (BG) (IT) for micron technology, inc.
IPC Code(s): G11C29/46, G11C29/12, G11C29/42
Abstract: methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. the counter-based read algorithm may comprise the following phases:
20240177795.DYNAMIC READ CALIBRATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Li-Te Chang of San Jose CA (US) for micron technology, inc., Aaron Lee of Sunnyvale CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C16/08, G11C16/28, G11C16/34
Abstract: a system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. the operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. the operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.
Inventor(s): Kimball Davis LOWRY of Boise ID (US) for micron technology, inc., Avishesh DHAKAL of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L23/538, H01L25/065, H10B80/00
Abstract: implementations described herein relate to a semiconductor substrate assembly and methods of manufacturing. the substrate assembly may include a top insulator layer and a conductive layer below the top insulator layer. the conductive layer may include an end of a conductive structure. the substrate assembly may include a bottom insulator layer below the conductive layer. the substrate assembly may include a protective fill structure. the protective fill structure may be adjacent to the end of the conductive structure and pass at least partially through the top insulator layer to the bottom insulator layer.
Inventor(s): Scott R. Cyr of Boise ID (US) for micron technology, inc., David P. Gooch of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L23/538, G11C11/408, H01L25/18, H10B80/00
Abstract: methods, systems, and devices for chip select wiring for a dual device package are described. a circuit board includes a plurality of layers, the plurality of layers including a first outer layer, a second inner layer, and a third outer layer. the circuit board also includes first and second chip select (cs) signal lines routed through the second inner layer of the circuit board, first and second memory devices coupled with the first outer layer and the third outer layer, respectively, a first via coupling the first cs signal line with a first upper memory die of the first memory device and a second lower memory die of the second memory device, and a second via coupling the second cs signal line with a second upper memory die of the second memory device and a first lower memory die of the first memory device.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. in an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. the first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. the first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. in some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. in some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.
Inventor(s): Shing-Yih Shih of New Taipei City (TW) for micron technology, inc.
IPC Code(s): H01L25/065, H01L21/48, H01L23/00, H01L23/14, H01L23/498, H01L23/538
Abstract: a semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side rdl structure, and a back-side rdl structure. a bridge tsv interconnect component is embedded in the resin molded core. the bridge tsv interconnect component has a silicon substrate portion, an rdl structure integrally constructed on the silicon substrate portion, and tsvs in the silicon substrate portion. a first semiconductor die and a second semiconductor die are mounted on the front-side rdl structure. the first semiconductor die and the second semiconductor die are coplanar.
Inventor(s): Yenting Lin of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/06, H01L21/02, H01L21/308, H01L21/768
Abstract: methods, apparatuses, and systems related to semiconductor structure with curved surfaces are described. an example apparatus includes a semiconductor structure comprising a patterned material comprising active areas, a first conductive material on a surface of each active area, and a first metal material on a surface of each first conductive material. the patterned material further includes a second and third conductive material, a first nitride material, and a second nitride material separating each active area, first conductive material, and first metal material from each second and third conductive material, and first nitride material. the apparatus includes a curved surface formed on a portion of the first metal material and second nitride material. the apparatus further includes a first layer comprising an oxide material and a second metal material on the patterned material, where the oxide material contacts the curved surface.
20240178297.SEMICONDUCTOR STRUCTURE WITH NITRIDE CAPS_simplified_abstract_(micron technology, inc.)
Inventor(s): Yenting Lin of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/45, H01L29/40, H01L29/49
Abstract: methods, apparatuses, and systems related to semiconductor structure with nitride caps are described. an example apparatus includes a semiconductor structure comprising a patterned material comprising active areas, a metal material on a surface of each active area. the patterned material further includes a second conductive material, a third conductive material, and a first dielectric material, and a nitride material adjacent each vertical side of the second conductive material, the third conductive material, and the first dielectric material. the apparatus includes a second nitride material on a first horizontal surface of each nitride material and each first dielectric material, and a second metal material.
Inventor(s): Fa-Long Luo of San Jose CA (US) for micron technology, inc., Tamara Schmitz of Scotts Valley CA (US) for micron technology, inc., Jeremy Chritz of Seattle WA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): H04L7/04, H04L27/00, H04L27/26
Abstract: examples described herein include systems and methods which include wireless devices and systems with examples of cross correlation including symbols indicative of radio frequency (rf) energy. an electronic device including a statistic calculator may be configured to calculate a statistic including the cross-correlation of the symbols. the electronic device may include a comparator configured to provide a signal indicative of a presence or absence of a wireless communication signal in the particular portion of the wireless spectrum based on a comparison of the statistic with a threshold. a decoder/precoder may be configured to receive the signal indicative of the presence or absence of the wireless communication signal and to decode the symbols responsive to a signal indicative of the presence of the wireless communication signal. examples of systems and methods described herein may facilitate the processing of data for wireless communications in a power-efficient and time-efficient manner.
Inventor(s): Ravi Kumar Kollipara of Puppalaguda (IN) for micron technology, inc., Deepu Narasimiah Subhash of Yeshwanthpur (IN) for micron technology, inc., Suresh Reddy Yarragunta of RR Nagar (IN) for micron technology, inc.
IPC Code(s): H05K7/20
Abstract: a system with a circuit with components, an enclosure with a top and a bottom, and a heat transfer device. the heat transfer device has an exterior surface with a first portion, a second portion, and a third portion, where the first portion faces opposite the second portion; and an interior surface with a fourth portion, a fifth portion, and a sixth portion, where the fourth portion faces the fifth portion. the first portion configured to thermally couple to the top of the enclosure. the second portion configured to thermally couple to the bottom of the enclosure. the fourth portion configured to couple to a component mounted on a primary side of the circuit board. the fifth portion configured to face a secondary side of the circuit board. the first heat transfer device configured to distribute thermal energy generated from a component to the top and bottom of the enclosure.
20240179894.METAL SENSE LINE CONTACT_simplified_abstract_(micron technology, inc.)
Inventor(s): Ping Chieh Chiang of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, H01L29/40, H01L29/49
Abstract: methods, apparatuses, and systems related to a metal sense line contact are described. an example apparatus includes a sense line pillar comprising a barrier material over a semiconductor substrate. the sense line pillar further includes a liner material adjacent the barrier material. the sense line pillar further includes a first metal material over the barrier material. the sense line pillar further includes a second metal material over the first metal material. the sense line pillar further includes a cap material over the second metal material. the apparatus further cell contacts between a plurality of sense line pillars.
Micron Technology, Inc. patent applications on May 30th, 2024
- Micron Technology, Inc.
- G06F3/06
- Micron technology, inc.
- G06F1/06
- G06F12/06
- G06F12/02
- G06F12/12
- G06F1/30
- G06F11/10
- G06F13/42
- G06F11/07
- G06F12/0815
- G06F12/0871
- G06F12/1009
- G06F12/0846
- G06F21/33
- G06F8/65
- G06F9/54
- G06F21/12
- G06F21/44
- H04L9/32
- G06F21/10
- G06F21/78
- G06F21/54
- G06F21/60
- G06F21/79
- G06F12/14
- G06F13/16
- G06F21/31
- H04L9/06
- G11C5/02
- G11C5/04
- G11C29/50
- G11C7/08
- G11C7/02
- G11C7/10
- G11C29/52
- G11C11/00
- G11C16/04
- G11C11/406
- G11C29/02
- G11C13/00
- G06F7/544
- G11C19/36
- G11C16/28
- G11C16/08
- G11C16/24
- G11C29/46
- G11C29/12
- G11C29/42
- G11C16/34
- H01L23/538
- H01L25/065
- H10B80/00
- G11C11/408
- H01L25/18
- H01L23/00
- H01L21/48
- H01L23/14
- H01L23/498
- H01L29/06
- H01L21/02
- H01L21/308
- H01L21/768
- H01L29/45
- H01L29/40
- H01L29/49
- H04L7/04
- H04L27/00
- H04L27/26
- H05K7/20
- H10B12/00
- G06F3/0679
- G06F3/0659
- G06F3/0604
- G06F3/0655
