Micron Technology, Inc. patent applications on May 16th, 2024
Patent Applications by Micron Technology, Inc. on May 16th, 2024
Micron Technology, Inc.: 48 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (8), G11C7/10 (7), G06F3/0679 (7), G11C5/06 (7), G11C29/42 (6)
With keywords such as: memory, device, data, column, host, array, cells, methods, value, and access in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Curtis W. Egan of Brighton CO (US) for micron technology, inc.
IPC Code(s): G06F1/30, G06F11/14
Abstract: a block storing corrupt data is detected. based on detecting the block storing corrupt data, threshold voltage (v) distribution data corresponding to the block is accessed. the vdistribution data comprises one or more vdistribution measurements corresponding to the block. the vdistribution data corresponding to the block is compared with reference vdistribution data. the reference vdistribution data comprises one or more reference vdistributions. based on a result of the comparison, it is determined whether to perform one or more heroic data recovery processes on the block.
Inventor(s): Jonathan D. Harms of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F1/3234, G06F1/08, G06F1/3206, G06F1/324, G06F11/00, G06F11/30, G06F11/34
Abstract: methods and apparatus for using characterized devices such as memories. in one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. the characterized memories can be used in conjunction with a solution density function to optimize memory searching. in one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (pow). the results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. in one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).
20240160288.NEURONAL TO MEMORY DEVICE COMMUNICATION_simplified_abstract_(micron technology, inc.)
Inventor(s): John D. Hopkins of Milpitas CA (US) for micron technology, inc., Mohad Baboli of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/01, G06F21/31, G06F21/84
Abstract: methods, systems, and apparatus for neuronal to memory device communication are described. an apparatus can include a memory device and a processing device communicatively coupled to the memory device. the processing device can receive neuronal map data associated with at least one image, determine that the neuronal map data is associated with the at least one image, and display the at least one image in response to the determination.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Scott E. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. a memory array is divided into column planes and an extra column plane. in some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. the extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). in an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.
Inventor(s): Ritesh Tiwari of Bangalore (IN) for micron technology, inc., Sridhar Prudviraj Gunda of Bangalore (IN) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/1009
Abstract: methods, systems, and devices for memory cell folding operations using host system memory are described. a memory system may temporarily store data to host system memory as part of a data transfer operation. for example, the memory system may transfer respective portions of data from a first non-volatile memory device to a first volatile memory device of the memory system and transfer the respective portions of data to a second volatile memory device of the host system based on a storage capacity of the first volatile memory device. the second volatile memory device may accumulate the portions of data until an aggregate size of the data satisfies a threshold, and the host system may transmit the aggregate data to be written to a second non-volatile memory device of the memory system.
Inventor(s): Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Nicola Ciocchini of Boise ID (US) for micron technology, inc., Animesh Roy Chowdhury of Boise ID (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Jung Sheng Hoei of Newark CA (US) for micron technology, inc., Niccolo’ Righetti of Boise ID (US) for micron technology, inc., Ugo Russo of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. the processing device is to receive a first read command at a first time. the processing device is further to receive a second read command at a second time. the processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. the processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.
Inventor(s): Patrick Robert Khayat of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F9/30
Abstract: a memory device configured to descramble scrambled composite data. in one approach, the scrambled composite data is provided by an xor (exclusive or operation) of more than one data set scrambled with non-linear scramblers. a memory device is configured to receive scramble codes generated by non-linear scramblers and perform an xor of the scrambled composite data with the scramble codes to remove scrambling from the composite data. in one example, the scrambled data sets are data to be written to a nand device at more than one bit per cell density (e.g., mlc, tlc, qlc, plc, etc.). for example, the scrambled data sets may be written to the nand device in more than one programming pass. in one example, the scrambled composite data is used to read the scrambled data sets that have been written in a first programming pass.
Inventor(s): Kai Wen Wu of Shanghai (CN) for micron technology, inc., Yue Wei of Shanghai (CN) for micron technology, inc., Peng Fei of Shanghai (CN) for micron technology, inc., Donghua Zhou of Suzhou City (CN) for micron technology, inc., Shao Chun Shi of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations comprising receiving, from a host system, a memory access command; responsive to determining that the memory access command is a program command, incrementing a consecutive counter value; determining whether the consecutive counter value satisfies a threshold criterion; responsive to determining that the consecutive counter value satisfies a threshold criterion, and setting an initial polling timer to a value associated the consecutive counter value satisfying the threshold criterion.
Inventor(s): Olivier Duval of San Jose CA (US) for micron technology, inc., Christopher Joseph Bueb of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for techniques for temperature-based access operations are described. a memory system may be configured to write temperature information to metadata during a write operation. the temperature information may indicate a temperature range within which the memory system may be during the write operation. the memory system may perform a corresponding read operation based on the temperature information written to the metadata and a temperature of the memory system during the read operation. a server may determine and indicate parameters associated with writing the temperature information to the metadata. additionally, or alternatively, the server may indicate trim parameters for use in performing read operations based on temperature information received from the memory system. in some examples, the memory system may perform targeted refresh operations at locations based on temperature information stored associated with the locations.
20240160386.VARIABLE DENSITY STORAGE DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Christopher Joseph Bueb of Folsom CA (US) for micron technology, inc., Aravind Ramamoorthy of Rocklin CA (US) for micron technology, inc., Anand Mudlapur of Folsom CA (US) for micron technology, inc., Zheng Wang of Louisville CO (US) for micron technology, inc., Olivier Duval of Pacifica CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for variable density storage device are described. a memory system may receive a write command to write data to the memory system. the memory system may write the data to a first set of memory cells of the memory system using a first write operation based on receiving the write command. the first set of memory cells store three or fewer bits of information in a single memory cell. the memory system may identify whether to transfer the data to a second set of memory cells on one or more parameters associated with the data. the second set of memory cells may store more bits of information in a single memory cell than the first set of memory cells. the memory system may transfer the data to the second set of memory cells based on identifying that the data is to be transferred.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc., Saideep Tiku of Folsom CA (US) for micron technology, inc., Wilbert Justino C. Florentino of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F9/50, G06F13/36
Abstract: a computing system, having: a plurality of components operable to perform computing tasks; a plurality of memory devices operable to provide memory and storage services to the computing tasks; a network of physical connections configured between the components and the memory devices to form a bus for the computing tasks to access the memory and storage services; and a network manager configured to allocate virtual channels, through the bus, for the computing tasks to access the memory and storage services with deterministic timing.
Inventor(s): Shawn Storm of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/07
Abstract: information corresponding to a health of a memory device or a functional state of the memory device, or both, is written to the memory device. radio frequency (rf) signaling is used to provide power to certain components of the memory device. information corresponding to the health of the memory device or the functional state of the memory device, or both, is retrieved from the memory device over-the-air in response to the rf signaling.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Scott E. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
Abstract: apparatuses, systems, and methods for single-pass access of ecc information, metadata information, or combinations thereof. the memory array includes a number of column planes and an extra column plane. a memory device may be set in an �4 single-pass operational mode. in this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. an error correction code circuit (ecc) may store parity bits associated with the data and metadata in non-selected ones of the column planes. in this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.
20240160526.DATA RECOVERY USING ORDERED DATA REQUESTS_simplified_abstract_(micron technology, inc.)
Inventor(s): Tal Sharifie of Lehavim (IL) for micron technology, inc., Chandrakanth Rapalli of Hyderabad (IN) for micron technology, inc., Yoav Weinberg of Toronto (CA) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
Abstract: methods, systems, and devices for data recovery using ordered data requests are described. in some examples, a memory system may receive data units from a host device. a first controller of the memory system may generate a protocol unit using the data units. a second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. the memory system may perform error detection operations using respective sets of parity bits for each of the units. upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Scott E. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
Abstract: apparatuses, systems, and methods for an enhanced ecc mode. the memory array includes a number of data column planes and an extra column plane. when the memory device is set in an enhanced ecc mode, data is stored in a subset of the data column planes, and an error correction code circuit (ecc) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. in this manner, memory may be capable of performing single error correction or single error correction with double error detection (secded) depending on the mode selected.
Inventor(s): Raja V.S. Halaharivi of Gilroy CA (US) for micron technology, inc., Prateek Sharma of San Jose CA (US) for micron technology, inc., Horia C. Simionescu of Foster City CA (US) for micron technology, inc.
IPC Code(s): G06F11/34
Abstract: a memory system includes a memory device and a processing device coupled to the memory device, the processing device is to present a plurality of physical or virtual functions (pfs/vfs) to a host computing system; set, for each of the plurality of pfs/vfs, a value of a credit counter to an initial value associated with a quality of service (qos) parameter of a respective pf/vf; responsive to fetching an original command received from the host computing system associated with a specified pf/vf, decrement the value of the credit counter associated with the specified pf/vf; responsive to receiving a reintroduced command associated with the specified pf/vf after the original command, increment the value of the credit counter; determine whether the value of the credit counter is not higher than a threshold value; and responsive to determining that the value of the credit counter is higher than the threshold value, continue fetching a subsequent command associated with the specified pf/vf.
Inventor(s): Marco Redaelli of München (DE) for micron technology, inc.
IPC Code(s): G06F12/02, G06F11/07
Abstract: a memory sub-system with multiple flash translation layer (ftl) tables is disclosed. a host system can utilize a memory sub-system that includes one or more memory components. the host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. the ftl provides several services, including translating logical addresses used by the host to physical addresses used to access physical memory. if one ftl table is corrupted, the logical-to-physical mapping of another ftl table may be used, allowing the device to continue to provide read-write access to at least a portion of the memory sub-system. thus, by use of a secondary ftl table, the reliability of the memory sub-system is improved.
20240160567.ARRAY ACCESS WITH RECEIVER MASKING_simplified_abstract_(micron technology, inc.)
Inventor(s): Natalija Jovanovic of München (DE) for micron technology, inc., Andrea Sorrentino of München (DE) for micron technology, inc., Marcos Alvarez Gonzalez of München (DE) for micron technology, inc.
IPC Code(s): G06F12/06, G06F12/02
Abstract: methods, systems, and devices for array access with receiver masking are described. a first device may issue to a second device a first sequence of write commands for a set of data. the first sequence of write commands may indicate different memory addresses in an order. after issuing the first sequence of write commands, the first device may issue to the second device a second sequence of read commands for the set of data. the second sequence of read commands may indicate the different memory addresses in the same order as the first sequence of write commands based on issuing the second sequence of read commands, the first device may receive the set of data from the second device.
Inventor(s): Raja V. S. Halaharivi of Gilroy CA (US) for micron technology, inc., Prateek Sharma of San Jose CA (US) for micron technology, inc., Sumangal Chakrabarty of Campbell CA (US) for micron technology, inc., Venkat R. Gaddam of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F12/1009, G06F12/123
Abstract: a processing device includes host interface circuitry to interact with a host system and an address translation circuit to handle address translation requests to the host system from host interface circuits. the address translation circuit includes a cache to store address translations associated with the address translation requests for future access by host interface circuits. a page request interface (pri) handler tracks translation miss messages received from the host interface circuits, each translation miss message including a virtual address of a miss at the cache. the pri handler removes duplicate translation miss messages having an identical virtual address and creates page miss requests from non-duplicate translation miss messages that are categorized into page request groups, each page request group corresponding to a host interface circuit of the host interface circuits. the pri handler queues the page request groups to be sent to a translation agent of the host system.
Inventor(s): Won Joo Yun of Boise ID (US) for micron technology, inc., Sang-Hoon Shin of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F15/78, G11C7/10
Abstract: an apparatus including reconfigurable interface circuits and associated systems and methods are disclosed herein. a reconfigurable interface circuit may include an output buffer and an input buffer coupled to a connector for respectively generating and receiving signals. the reconfigurable interface circuit may include a control circuit configured to control operation of the input and output buffers along with additional circuits to selectively implement one or more from a set of selectable communication settings.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F21/56, B60W50/14, G06N3/0442
Abstract: a device to detect attacks on a memory system in an advanced driver-assistance system (adas) of a vehicle. the device has an interface operable on a memory channel, a random access memory, a non-volatile memory cell array, and a controller configured to detect a trigger event, and in response: identify a sequence of commands received in the interface from the memory channel to access memory services provided via at least the random access memory during adas operations; perform operations of multiplication and accumulation using the non-volatile memory cell array to implement computations of an artificial neural network responsive to the sequence of commands as an input to generate a classification of the sequence as an output; and provide the classification via the interface.
Inventor(s): Libo WANG of Boise ID (US) for micron technology, inc., Ying ZHANG of Boise ID (US) for micron technology, inc., Soo Koon NG of Boise ID (US) for micron technology, inc.
IPC Code(s): G06Q30/0601, G06F40/279, G06N20/00
Abstract: in some implementations, a device may obtain an input that identifies a device type. the device may obtain, based on the input, information indicating a configuration associated with the device type. the device may determine, using a plurality of machine learning models respectively associated with a plurality of memory types, compatibilities between the plurality of memory types and the device type based on the configuration associated with the device type. each of the plurality of machine learning models may be trained to determine a compatibility of a respective memory type, of the plurality of memory types, with a given configuration. the device may determine a recommendation of one or more memory types for the device type based on the compatibilities between the plurality of memory types and the device type. the device may transmit an indication of the recommendation of the one or more memory types.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06T5/50, G06T3/40, G06T9/00
Abstract: a method to generate a series of previews of an image with low latency, includes: retrieving, from a storage device in a first pass, first portions of image data representative of an image; generating, based on the first portions and without at least second portions of the image data, a first preview of the image; presenting the first preview; retrieving, from the storage device in a second pass, the second portions of the image data; generating, based on the first portions and the second portions of the image data, a second preview of the image; and presenting the second preview.
Inventor(s): Nagasubramaniyan Chandrasekaran of Eagle ID (US) for micron technology, inc.
IPC Code(s): G06T7/00, G06V10/25, G06V10/40, G06V10/764, G06V10/77, G06V10/774
Abstract: a system includes a memory and a processing device, operatively coupled with the memory, to perform operations including: receiving an image of a substrate of an electronic device; extracting, by a feature extraction model processing the image, a plurality of visual features from the image; and identifying, by a trainable feature classifier processing the plurality of visual features, a region of interest corresponding to an electronic circuit associated with performance of the electronic circuit.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06V10/82, G06F7/544, G06T11/00, G06V10/22, G06V10/24, G06V10/94, G06V20/20
Abstract: a pair of smart glasses having: a digital camera configured to capture an image of a field of view; and a processing device configured to perform an analysis of the image using an artificial neural network having weight data. the processing device can apply different quantization levels to data from different regions of the image, and apply the different quantization levels to the weight data in weighing on the data from the different regions respectively. for example, weighing image data from a peripheral region of the image with the weight data can be performed with a lower level of accuracy than weighing image data from a center region of the image with the weight data to reduce energy consumption. based on an output of the artificial neural network responsive to the image, the glasses can present virtual content superimposed on a view of reality seen through the glasses.
Inventor(s): KOHEI NAKAMURA of Tokyo (JP) for micron technology, inc., SHUICHI TSUKADA of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/02, G11C7/14
Abstract: apparatuses, systems, and methods for input buffer data feedback equalization (dfe). an input buffer includes a dfe circuit which adjusts a threshold voltage of the input buffer based on a previously latched data bit. the dfe circuit includes a number of dfe legs coupled in parallel to a node of the input buffer. each dfe leg is selectively activated by a dfe code. each dfe leg includes a capacitance (e.g., a field effect transistor) which is coupled to the node in an active leg based on the previously latched data bit. the previously latched data bit may also be used to generate a reset signal which couples the capacitors to ground. each dfe leg may also include a transistor coupled to a bias voltage, which is stable across a range of pvt variations.
Inventor(s): Kang-Yong Kim of Boise ID (US) for micron technology, inc., Hyunyoo Lee of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10
Abstract: some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. the memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. the external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.
20240161796.Programmable Memory Timing_simplified_abstract_(micron technology, inc.)
Inventor(s): Kang-Yong Kim of Boise ID (US) for micron technology, inc., Hyun Yoo Lee of Boise ID (US) for micron technology, inc., Timothy M. Hollis of Meridian ID (US) for micron technology, inc., Dong Soon Lim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G06F3/06, G06F13/16, G11C7/22, G11C11/4093, G11C29/02, G11C29/10
Abstract: described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. if data signals propagate along a bus with the same timing, simultaneous switching output (sso) and crosstalk can adversely impact channel timing budget parameters. an example system includes an interconnect having multiple data lines that couple the host device to the memory device. in example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. the memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. the host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. lengths of the offsets can vary. further, a system can activate the phase offsets based on frequency.
20240161801.DECODING ARCHITECTURE FOR WORD LINE TILES_simplified_abstract_(micron technology, inc.)
Inventor(s): Paolo Fantini of Vimercate (IT) for micron technology, inc., Lorenzo Fratin of Buccinasco (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc., Enrico Varesi of Milano (IT) for micron technology, inc.
IPC Code(s): G11C8/08, G11C5/06, G11C5/14, G11C8/10, G11C8/14
Abstract: methods, systems, and devices for a decoding architecture for memory devices are described. word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. each word line plate may be coupled with a corresponding word line driver via a respective electrode. a memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.
20240161812.Integrated Assemblies_simplified_abstract_(micron technology, inc.)
Inventor(s): Yuan He of Boise ID (US) for micron technology, inc., Beau D. Barry of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/4074, G11C11/4094, G11C11/4097
Abstract: some embodiments include an integrated assembly having a memory array over a base. first sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.
Inventor(s): Shantilal Rayshi Doru of San Diego CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Steven Michael Kientz of Westminster CO (US) for micron technology, inc., Sampath K. Ratnam of San Jose CA (US) for micron technology, inc., Dung Viet Nguyen of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G06F12/02
Abstract: described are systems and methods for memory read threshold tracking based on memory device-originated metrics characterizing voltage distributions. an example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. the controller is to perform operations including: receiving a first value of a metric characterizing threshold voltage distributions of a subset of a set of the plurality of memory cells; determining a first voltage threshold adjustment value; receiving a second value of the metric; determining a second voltage threshold adjustment value; and applying the second voltage threshold adjustment value for reading the set of the plurality of memory cells.
Inventor(s): Nicola Ciocchini of Boise ID (US) for micron technology, inc., Animesh Roy Chowdhury of Boise ID (US) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Jung Sheng Hoei of Newark CA (US) for micron technology, inc., Niccolo’ Righetti of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Ugo Russo of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C7/04, G11C16/32
Abstract: a system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.
Inventor(s): Aswin Thiruvengadam of Folsom CA (US) for micron technology, inc., Daniel L. Lowrance of El Dorado Hills CA (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/02, G06F12/02, G11C16/10
Abstract: the present disclosure includes apparatuses and methods related to a memory system including a controller and an array of memory cells. an example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
Inventor(s): Melissa I. Uribe of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C7/10, G11C29/44
Abstract: methods, systems, and devices for read command fault detection in a memory system are described. for example, a memory device may be configured to set a field of a register with a first value, corresponding to a state where a read command has not been decoded. if the memory device receives and decodes a read command from a host device, the memory device may set the field with a second value. the memory device indicate a value of the field of the register to the host device, which may be used to evaluate whether to process information interpreted over an interface between the host device and the memory device. for example, if the host device receives an indication of the second value, the host device may proceed with processing and, if the host device receives an indication of the first value, the host device may refrain from processing.
Inventor(s): Scott E. Smith of Boise ID (US) for micron technology, inc., Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/42
Abstract: apparatuses, systems, and methods for enhanced metadata information. the memory array includes a number of column planes and an extra column plane. a memory device is set in an x4 single-pass operational mode. in this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. an error correction code circuit (ecc) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. in this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.
Inventor(s): Scott E. Smith of Boise ID (US) for micron technology, inc., Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C29/12
Abstract: apparatuses, systems, and methods for single-pass access of ecc information, metadata information, or combinations thereof. the memory array includes a number of column planes and an extra column plane. a memory device may be set in an �4 single-pass operational mode. in this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. an error correction code circuit (ecc) may store parity bits associated with the data and metadata in non-selected ones of the column planes. in this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Scott E. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C7/10, G11C7/12, G11C29/00
Abstract: apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. a memory array is divided into column planes and an extra column plane. in some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. the extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). in an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.
20240162154.SEMICONDUCTOR DEVICE HAVING CONTACT PLUG_simplified_abstract_(micron technology, inc.)
Inventor(s): KEIICHI TSUCHIYA of Higashihiroshima (JP) for micron technology, inc., KEIZO KAWAKITA of Higashihiroshima (JP) for micron technology, inc.
IPC Code(s): H01L23/535, H01L21/768, H01L23/528, H01L23/532
Abstract: an apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction crossing the first direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. the contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. a maximum width of the upper conductive section in the first direction is smaller than a maximum width of the lower conductive section in the first direction.
Inventor(s): Lei Wei of Boise ID (US) for micron technology, inc., Adam Thomas Barton of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/538, G11C5/06, G11C7/10, H01L21/768
Abstract: methods, systems, and devices for reduced resistivity for access lines in a memory array are described. a first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. the first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. one or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.
Inventor(s): Seng Kim YE of Singapore (SG) for micron technology, inc., Hong Wan NG of Singapore (SG) for micron technology, inc., Kelvin Aik Boo TAN of Singapore (SG) for micron technology, inc., See Hiong LEOW of Singapore (SG) for micron technology, inc., Ling PAN of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/16, H01L23/00, H01L25/00, H10B80/00
Abstract: implementations described herein relate to various semiconductor device assemblies. in some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. the semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. the load switch may include multiple second electrical contacts disposed on the second outer surface. the semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.
Inventor(s): Kelvin Aik Boo TAN of Singapore (SG) for micron technology, inc., Hong Wan NG of Singapore (SG) for micron technology, inc., See Hiong LEOW of Singapore (SG) for micron technology, inc., Seng Kim YE of Singapore (SG) for micron technology, inc., Ling PAN of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/16, H01L23/00
Abstract: implementations described herein relate to various semiconductor device assemblies. in some implementations, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate, and a passive electronic component disposed on the semiconductor die.
Inventor(s): Michael A. Lindemann of Boise ID (US) for micron technology, inc., Collin Howder of Boise ID (US) for micron technology, inc., Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc., Richard J. Hill of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/45, H01L21/28, H01L29/417, H01L29/792, H10B43/27, H10B43/35
Abstract: electronic devices comprising a doped dielectric material adjacent to a source contact, tiers of alternating conductive materials and dielectric materials adjacent to the doped dielectric material, and pillars extending through the tiers, the doped dielectric material, and the source contact and into the source stack. related methods and electronic systems are also disclosed.
Inventor(s): Robert Richard Noel Bielby of Placerville CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04B1/69
Abstract: a device having a plurality of pins configured to connect circuits within an integrated circuit package to circuits outside of the integrated circuit package. a driver enclosed within the package is programmable to generate a spread spectrum signal to represent data being transmitted from a pin of the device. frequency distribution of the signal spreading over a bandwidth in a frequency domain can be programmed to customize the electromagnetic emission caused by the communication of data through the pin. the frequency spreading can be programmed to reduce energy consumption, electromagnetic interference, and/or errors in receiving the data transmitted via the pin. the settings can be programmed into registers enclosed in the integrated circuit package to control the driver and/or dynamically adjusted using an artificial intelligent engine to optimize a cost function.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04L9/40, G06N3/08, H04L9/00
Abstract: a device to detect anomalous communications on a communication channel. the device has: an interface to receive from the communication channel, encrypted communications transmitted among a plurality of components; and a non-volatile memory cell array having memory cells programmed in a first mode according to weight matrices of an artificial neural network trained to classify sequences of encrypted communications generated according to an encryption configuration. a controller of the device is configured to: identify a sequence of encrypted communications according to the encryption configuration; perform, using the memory cells programmed in the first mode to facilitate multiplication and accumulation, operations of multiplication and accumulation; and determine, without decryption of the sequence of encrypted communications, whether the sequence of encrypted communications is anomalous, based on an output of the artificial neural network responsive to the sequence of encrypted communications as an input.
Inventor(s): Yuichi Yokoyama of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/108
Abstract: a microelectronic device comprises a stack structure comprising an array region comprising first conductive structures vertically spaced from one another, and a staircase region horizontally neighboring the array region and comprising second conductive structures vertically spaced from one another and coupled to the first conductive structures. the second conductive structures individually comprise portions extending in a first horizontal direction, and additional portions extending in a second horizontal direction transverse to the first horizontal direction. the staircase region comprises staircase structures having steps partially defined by edges of the second conductive structures. some of the steps extend in the first horizontal direction and some others of the steps extend in the second horizontal direction. related memory devices, electronic systems, and methods are also described.
Inventor(s): Jordan D. Greenlee of Boise ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc., John D. Hopkins of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B41/27, G11C5/06, H10B43/27
Abstract: some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. a source structure is coupled to lower regions of the channel-material-pillars. a panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. rings laterally surround lower regions of the conductive posts. the rings are between the conductive posts and the doped-semiconductor-material. the rings include laminates of two or more materials, with at least one of said two or more materials being insulative. some embodiments include methods for forming integrated assemblies.
20240164113.MEMORY STRUCTURES WITH VOIDS_simplified_abstract_(micron technology, inc.)
Inventor(s): Alessandro Calderoni of Boise ID (US) for micron technology, inc., Kamal Karda of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B53/20, G11C5/06, H01L21/28, H01L29/51, H01L29/66, H01L29/78, H10B51/10, H10B51/20, H10B53/10
Abstract: methods, systems, and devices for memory structures with voids are described. a memory architecture may include voids between adjacent columns of memory cells. for example, a memory array may be manufactured by forming one or more sacrificial structures, as well as a liner material on sidewalls of the sacrificial structures, extending in the column direction. memory cells may be formed on the sacrificial structures by patterning a conductive material to form bottom electrodes, forming a ferroelectric material adjacent to the bottom electrodes, and forming a set of plate lines over the ferroelectric material. the sacrificial structures may then be removed to form voids between at least some adjacent columns of memory cells.
Inventor(s): Hung-Wei Liu of Meridian ID (US) for micron technology, inc., Vassil N. Antonov of Boise ID (US) for micron technology, inc., Ashonita A. Chavan of Boise ID (US) for micron technology, inc., Darwin Franseda Fan of Boise ID (US) for micron technology, inc., Jeffery B. Hull of Boise ID (US) for micron technology, inc., Anish A. Khandekar of Boise ID (US) for micron technology, inc., Masihhur R. Laskar of Boise ID (US) for micron technology, inc., Albert Liao of Boise ID (US) for micron technology, inc., Xue-Feng Lin of Boise ID (US) for micron technology, inc., Manuj Nahar of Boise ID (US) for micron technology, inc., Irina V. Vasilyeva of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B53/20, H01L21/223, H01L29/10, H01L29/66, H01L29/78, H10B51/20, H10B51/30, H10B53/30
Abstract: a method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. the multiple time-spaced microwave annealing steps reduce average concentration of elemental-form h in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. the reduced average concentration of elemental-form h is 0.005 to less than 1 atomic percent. structure embodiments are disclosed.
Micron Technology, Inc. patent applications on May 16th, 2024
- Micron Technology, Inc.
- G06F1/30
- G06F11/14
- Micron technology, inc.
- G06F1/3234
- G06F1/08
- G06F1/3206
- G06F1/324
- G06F11/00
- G06F11/30
- G06F11/34
- G06F3/01
- G06F21/31
- G06F21/84
- G06F3/06
- G06F12/1009
- G06F9/30
- G06F9/50
- G06F13/36
- G06F11/07
- G06F11/10
- G06F12/02
- G06F12/06
- G06F12/123
- G06F15/78
- G11C7/10
- G06F21/56
- B60W50/14
- G06N3/0442
- G06Q30/0601
- G06F40/279
- G06N20/00
- G06T5/50
- G06T3/40
- G06T9/00
- G06T7/00
- G06V10/25
- G06V10/40
- G06V10/764
- G06V10/77
- G06V10/774
- G06V10/82
- G06F7/544
- G06T11/00
- G06V10/22
- G06V10/24
- G06V10/94
- G06V20/20
- G11C7/02
- G11C7/14
- G06F13/16
- G11C7/22
- G11C11/4093
- G11C29/02
- G11C29/10
- G11C8/08
- G11C5/06
- G11C5/14
- G11C8/10
- G11C8/14
- G11C11/4091
- G11C11/4074
- G11C11/4094
- G11C11/4097
- G11C16/34
- G11C7/04
- G11C16/32
- G11C16/10
- G11C29/42
- G11C29/44
- G11C29/12
- G11C29/52
- G11C7/12
- G11C29/00
- H01L23/535
- H01L21/768
- H01L23/528
- H01L23/532
- H01L23/538
- H01L25/16
- H01L23/00
- H01L25/00
- H10B80/00
- H01L29/45
- H01L21/28
- H01L29/417
- H01L29/792
- H10B43/27
- H10B43/35
- H04B1/69
- H04L9/40
- G06N3/08
- H04L9/00
- H01L27/108
- H10B41/27
- H10B53/20
- H01L29/51
- H01L29/66
- H01L29/78
- H10B51/10
- H10B51/20
- H10B53/10
- H01L21/223
- H01L29/10
- H10B51/30
- H10B53/30
- G06F3/0679
