Micron Technology, Inc. patent applications on March 6th, 2025
Patent Applications by Micron Technology, Inc. on March 6th, 2025
Micron Technology, Inc.: 41 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (8), G06F12/02 (4), G11C7/10 (3), G11C29/52 (3), G11C11/408 (3) G06F3/0613 (3), G06F3/0659 (3), G06F12/0246 (2), G11C29/52 (2), G11C11/4074 (2)
With keywords such as: memory, device, data, cells, devices, methods, line, coupled, access, and information in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20250077077. SUSPENDING OPERATIONS OF A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): David Aaron Palmer of Boise ID (US) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: methods, systems, and devices for suspending operations of a memory system are described. a memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: various embodiments provide for processing write requests on a memory system based on queue identifiers and thread identification associated with the write requests. in particular, various embodiments can leverage queue identifiers and memory address information included in write requests to separate, associate those write request to threads (e.g., virtual thread) tracked by the memory system, and coalesce multiple write requests associated with a single thread into a single (larger) write to a sequence of blocks.
Inventor(s): Chulbum Kim of San Jose CA (US) for micron technology, inc., Sundararajan Sankaranarayanan of Fremont CA (US) for micron technology, inc., Xiangyu Tang of San Jose CA (US) for micron technology, inc., Dustin J. Carter of Placerville CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: a memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, wherein the memory sub-system controller provides a plurality of channel mappings, wherein a first channel mapping of the plurality of channel mappings identifies a first controller channel of the plurality of controller channels and one or more first memory channels of a plurality of memory channels, and wherein a second channel mapping of the plurality of channel mappings identifies a second controller channel of the plurality of controller channels and one or more second memory channels of the plurality of memory channels; one or more memory devices comprising the plurality of memory channels, wherein the one or more memory devices comprise a plurality of memory dies, wherein each memory channel of the plurality of memory channels corresponds to a respective one of the plurality of memory dies; and a channel switch circuit coupled between the plurality of the controller channels and the plurality of memory channels, wherein each controller channel of the plurality of the controller channels is capable to be mapped to the plurality of memory channels for data routing.
Inventor(s): Luca Bert of Bologna (BO) (IT) for micron technology, inc.
IPC Code(s): G06F3/06, G06F13/42
CPC Code(s): G06F3/0613
Abstract: a storage product manufactured as a standalone computer component and installed in a computing system to implement an internet application. the storage product includes a network interface, a host interface, computing circuits, and a local storage device having a storage capacity accessible via the network interface. a data generator is connected to the network interface. a local host system is connected to the host interface to control access, made via the network interface. the data generator can send bulk data to the network interface. the computing circuits can generate derived data from the bulk data and store the derived data and/or the bulk data in the local storage device. a central server and/or a user device can connect over internet via to the network interface of the storage product to access the derived data and/or the bulk data.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0644
Abstract: apparatuses, systems, and methods for half-page modes. a memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. in some memory devices, each half of the memory cells may be separately activated by different word line portions. in some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. the additional information may be provided along additional data terminals so as not to increase the data burst length.
Inventor(s): Roberto Izzi of Caserta (IT) for micron technology, inc., Luca Porzio of Casalnuovo (IT) for micron technology, inc., Marco Onorato of Villasanta (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for techniques for detection of shutdown patterns are described. a memory device may receive a set of commands from a host device. the memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. the memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. the memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. the memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.
Inventor(s): Nabeel Meeramohideen Mohamed of Round Rock TX (US) for micron technology, inc., Steven Andrew Moyer of Round Rock TX (US) for micron technology, inc., David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for access heatmap generation at a memory device are described. in some examples, a memory device may maintain a register for tracking access operation occurrence, for which access operations of an address of the memory device may be mapped to multiple fields of the register. in some cases, in response to a first access operation performed on a first address of the memory device, the memory device may increment a first field and a second field of the register and, in response to a second access operation performed on a second address of the memory device, the memory device may increment the first field and a third field of the register. in some examples, the memory device may maintain a second register having a set of fields that each indicate a respective address for which an access occurrence satisfies a threshold.
Inventor(s): Sahil Soi of Bangalore Urban (IN) for micron technology, inc., Dhananjayan Athiyappan of Bangalore Urban (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a processing device in a memory sub-system identifies an indication of a completion of a memory access command directed to a memory device and determines whether there are other memory access commands directed to the memory device that are pending. responsive to determining that there are other memory access commands pending, the processing device coalesces additional indications of completions of the other memory access commands that are available within a threshold period of time with the indication of the completion into a completion data chunk and sends the completion data chunk to a host system. the host system is to store the completion data chunk as one or more completion queue entries in a completion queue in a host memory of the host system via a single host memory write operation.
20250077345. HOST ERROR CONTROL MATRIX_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Joseph G. Garofalo of Palo Alto CA (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1044
Abstract: methods, systems, and devices for host error control matrix are described. a host device may implement a parity check matrix for generating error control information with a relatively low likelihood that a multi-bit error in a codeword associated with the error control information is mistaken for a single-bit error. the host device may implement a parity check matrix patterned such that when the error control information is generated, there is a relatively low likelihood that an error code resulting from a comparison of the error control information will yield an indication of a single-bit error when a multi-bit error occurs. for example, the host device may compare first error control information generated for a codeword and transmitted to a memory device with second error control information generated after receiving the codeword from the memory device, and generate an error code using the results of the comparison.
Inventor(s): Antonino Capri' of Bergamo (IT) for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio MI (IT) for micron technology, inc., Joseph M. McCrate of Boise ID (US) for micron technology, inc., Graziano Mirichigni of Vimercate (IT) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc., Marco Sforzin of Cernusco Sul Naviglio MI (IT) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1064
Abstract: a variety of applications can include a memory device implementing one or more caches or buffers integrated with a controller of the memory device to provide post package repair resources. the one or more caches or buffers can be separate from the media subsystem that stores user data for the memory device. arrangements of the one or more caches or buffers can include the one or more caches or buffers structured between decoder-encoder arrangements of the memory device and the media subsystem of the memory device. other arrangements of the one or more caches or buffers can include decoder-encoder arrangements of the memory device structured between the one or more caches or buffers and the media subsystem of the memory device. combinations of arrangements may be implemented. additional apparatus, systems, and methods are disclosed.
Inventor(s): Brent Keeth of Boise ID (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Shivasankar Gunasekaran of Erie CO (US) for micron technology, inc., Sai Krishna Mylavarapu of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/108
Abstract: methods, systems, and devices for data protection techniques in stacked memory architectures are described. a memory system having a stacked memory architecture may include error correction information associated with a data set that includes multiple data segments stored across multiple memory arrays and, in some examples, multiple dies of the memory system. as part of a write operation for a first data segment of a data set, the memory system may retrieve the remaining data segments of the data set and calculate error correction information using the first data segment and the remaining data segments. as part of a read operation for a second data segment of the data set, the memory system may retrieve each data segment of the data set and perform an error correction operation on the data set using the error correction information.
Inventor(s): Craig William Warner of Coppell TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F11/20, G06F11/16
CPC Code(s): G06F11/2056
Abstract: disclosed in some examples are methods, systems, devices, and architectures which provide for techniques for memory device and memory fabric redundancy within distributed memory systems. in some examples, two memory devices are paired and each stores a same set of data such that writes to the memory devices are duplicated and reads may be satisfied from either device. in some examples, a memory processing unit (mpu) may be incorporated into the memory architecture to support these paired memory devices. the mpu may be placed between the host and a multi-planed memory fabric which connects to multi-ported cxl memory devices. in some examples, the mpu may also enable the use of alternative fabric links. that is, if a memory fabric link between the mpu and a memory device is unavailable, an alternative link may be utilized to restore connectivity to a memory device.
20250077411. MEMORY ACCESS STATISTICS MONITORING_simplified_abstract_(micron technology, inc.)
Inventor(s): David A. Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/0882, G06F13/16
CPC Code(s): G06F12/0238
Abstract: systems, apparatuses, and methods related to memory access statistics monitoring are described. a host is configured to map pages of memory for applications to a number of memory devices coupled thereto. a first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. a second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. the host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
Inventor(s): Kishore K. Muchherla of San Jose CA (US) for micron technology, inc., Hong Lu of San Jose CA (US) for micron technology, inc., Mark Ish of Manassas VA (US) for micron technology, inc., Akira Goda of Setagaya (JP) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: an apparatus can comprise a memory array comprising a plurality of erase blocks and a plurality of strings of memory cells. each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. a controller coupled to the memory array can be configured to: receive a write command corresponding to data to be written to the memory array; determine a temperature classification for the data to which the write command corresponds; and, based on the determined temperature classification for the data, route the data to a first write cursor or to one of a number of different write cursors.
Inventor(s): Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Xiangyu Tang of San Jose CA (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Haibo Li of Cupertino CA (US) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a memory device can include a memory array including memory cells arranged in one or more pages. the memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. the control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. the control logic can also receive an erase request to erase the one or more pages after the second time.
Inventor(s): Patrick Michael Sheridan of Boulder CO (US) for micron technology, inc.
IPC Code(s): G06F12/06, G06F12/02, G06F13/16
CPC Code(s): G06F12/0638
Abstract: disclosed in some examples are methods, systems, memory devices, memory controllers, and machine-readable mediums which provide for reserving physical memory device resources to specific execution units. execution units may include processes, threads, virtual machines, functions, procedures, or the like. physical memory device resources may include channels, modules, ranks, banks, bank groups, and the like. for example, a physical memory device resource that is reservable may be a smallest unit that allows for parallel access with another of the same size unit.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/06
CPC Code(s): G06F12/0646
Abstract: apparatuses, systems, and methods for half-page modes. a memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. in some memory devices, each half of the memory cells may be separately activated by different word line portions. in some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. the additional information may be provided along additional data terminals so as not to increase the data burst length.
Inventor(s): Eric N. Lee of San Jose CA (US) for micron technology, inc., Leonid Minz of Beer Sheva (IL) for micron technology, inc., Yoav Weinberg of Toronto (CA) for micron technology, inc., Ali Feiz Zarrin Ghalam of Sunnyvale CA (US) for micron technology, inc., Luigi Pilolli of L'Aquila (IT) for micron technology, inc.
IPC Code(s): G06F13/30, G06F13/16
CPC Code(s): G06F13/30
Abstract: operations include determining, based on a period of time during which a logical level of the signal line is maintained at a first logical level, that a data transfer to the memory array is being suspended, determining, while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level, and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed.
Inventor(s): Sujeet V. Ayyapureddi of Boise ID (US) for micron technology, inc., Brent Keeth of Boise ID (US) for micron technology, inc., Matthew A. Prather of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C5/04, G11C7/22
CPC Code(s): G11C7/109
Abstract: methods, systems, and devices for buffer configurations for communications between memory dies and a host device are described. a memory device may include a buffer having a first interface coupled with a host device and a second interface coupled with a memory die of the memory device. the first interface may communicate information with the host device at a first frequency and according to a first signaling scheme, and the second interface may communicate information with the memory die at a second frequency and according to a second signaling scheme. the first frequency may be higher than the second frequency, and the second signaling scheme may include a greater quantity of voltage levels than the first signaling scheme.
Inventor(s): Patrick Michael Sheridan of Boulder CO (US) for micron technology, inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1096
Abstract: disclosed in some examples are methods, systems, memory devices, and machine-readable mediums which store a single compressed value per line with a marker value in a front of the compressed version of the memory line. in some examples, the only value stored in the memory line is the value normally stored therein. this removes the complexity of the prediction tables and the inclusion of invalid values as well as preventing the penalty when those prediction tables are wrong. furthermore, by inclusion of the marker in the beginning of the memory line, the system can quickly determine the compression status of the memory line without having to read the entire line. that is, it can quickly stop reading the rest of the memory line once the compressed data is read out which saves the memory device from having to read the entire line.
Inventor(s): Shawn M. Hilde of Meridian ID (US) for micron technology, inc., Dennis G. Montierth of Meridian ID (US) for micron technology, inc., Garth N. Grubb of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406
CPC Code(s): G11C11/40615
Abstract: methods, systems, and devices for a self-refresh state with decreased power consumption are described. a memory system may enter a self-refresh state to refresh a set of rows of memory cells at the memory system. based on entering the self-refresh state, the memory system may execute a first set of refresh operations on the rows of memory cells according to a first rate. additionally, the memory system may determine, while in the self-refresh state, whether to decrease the rate for executing the refresh operations to a second rate based on whether each of the rows of memory cells is refreshed according to the first rate. in cases that the memory system determines to decrease the rate for executing the refresh operations, the memory system may execute a set of second refresh operations on the rows of memory cells according to the second, slower, rate while in the self-refresh state.
Inventor(s): Sangjin Byeon of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4074, G11C5/14, G11C11/4076
CPC Code(s): G11C11/4074
Abstract: a method to attenuate excessive supply voltage fluctuations in a memory system comprising a memory controller and a memory device configured to store and retrieve data is provided. the method includes detecting a potential supply voltage fluctuation at a voltage-threshold violation detection circuit in the memory controller, wherein the potential supply voltage fluctuation corresponds to an inrushing current from an initialization state or a surge of current from a switch to a busy state after staying in a long-term idle state. in response to detecting the potential supply voltage fluctuation, the method includes generating a control signal from the voltage-threshold violation detection circuit. the method includes transmitting the control signal from the memory controller to the memory device. the method includes decoding the control signal in the memory device. the method includes attenuating the potential supply voltage fluctuation to prepare for memory access.
Inventor(s): Huy T. Vo of Boise ID (US) for micron technology, inc., Eric Carman of Boise ID (US) for micron technology, inc., Kamal M. Karda of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4074, G11C11/4091, H10B12/00
CPC Code(s): G11C11/4074
Abstract: systems, methods, and apparatus are provided for discharging an access device in a memory device. an example structure includes a memory device having a local sense line and a bleeder device coupled to the local sense line and a bleeder supply. the memory device can also include a sense line multiplexor coupled to the local sense line and a global sense line, and a sense amplifier coupled to the global sense line. the sense amplifier can be configured to sense and latch a voltage of the global sense line in response to the memory device receiving a command. the memory device can further include a plurality of access devices coupled to the local sense line, a plurality of capacitors coupled to the plurality of access devices, and a plate voltage supply, separate from the bleeder supply, coupled to the plurality of capacitors.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4078, G11C11/406
CPC Code(s): G11C11/4078
Abstract: disclosed are methods, systems, and apparatuses for providing per-channel row hammer alerts, from a memory device to a host, without the use of a dedicated per-channel alert interface. when detecting a row hammer alert condition, the memory device may determine whether an existing interface (e.g., a severity interface used to transmit severity information) is available. the interface may be available outside of certain designated burst positions during a read burst. once the interface is available, the memory device may transmit a row hammer alert indication to the host. the host may determine whether information received over the interface is associated with a row hammer alert or severity, depending on when the information was received (e.g., in what burst position during a read burst).
20250078909. APPARATUS FOR SMALL SWING DATA TRANSFER_simplified_abstract_(micron technology, inc.)
Inventor(s): HARUTAKA MAKABE of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/4074, G11C11/4093
CPC Code(s): G11C11/4096
Abstract: embodiments of the disclosure provide an apparatus comprising a small swing driver and a small swing repeater on data transfer wiring of a memory device. the small swing driver includes 1st pair of 1st-type p/n-mos transistors and 2nd pair of 2nd-type p/n-mos transistors. the small swing repeater includes 3rd pair of 1st-type p/n-mos transistors and 4th pair of 2nd-type p/n-mos transistors. in the small swing driver, positive power supply voltage and 1st step-down power supply voltage are applied to gate and source of 2nd-type p-mos transistor of 2nd pair, and 2nd step-down power supply voltage is applied to 2nd-type p-mos transistor of 2nd pair as backbias voltage. in the small swing repeater, 1st and 2nd step-down power supply voltages are applied to source and gate of 2nd-type p-mos transistor of 4th pair. 2nd step-down power supply voltage is also applied to 2nd-type p-mos transistor of 4th pair as backbias voltage.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., David A. Daycock of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4097, G11C11/408, G11C11/4091, H10B12/00
CPC Code(s): G11C11/4097
Abstract: a microelectronic device includes memory cells, hieratical digit line (hdl) structures, and sense amplifier (sa) devices. the memory cells are within an array region and respectively include an access device and a storage node device vertically underlying and coupled to the access device. the hdl structures are within the array region and vertically overlie and are coupled to the memory cells. the hdl structures respectively include a lower section, an upper section vertically overlying and at least partially horizontally offset from the lower section, and a middle section vertically extending from and between the lower section and the upper section. the sa devices are within the array region and vertically overlie and are coupled to the hdl structures. related methods, memory devices, and electronic systems are also described.
Inventor(s): Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Sead Zildzic of Folsom CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Violante Moschiano of Avezzano (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/28
CPC Code(s): G11C16/102
Abstract: a system includes a memory device including a memory array and processing logic, operatively coupled with the memory array, to perform operations including identifying a set of cells of the memory array to be programmed with dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.
Inventor(s): Curtis Egan of Brighton CO (US) for micron technology, inc.
IPC Code(s): G11C16/26, G11C11/56
CPC Code(s): G11C16/26
Abstract: methods, systems, and devices for coding to decrease error rate discrepancy between pages are described. for example, to identify a unit-distance code for operating a memory device, voltage drifts of a set of read voltages after a duration may be identified and each of the read voltages may be mapped to one of a set of pages of the memory cell using various possible unit-distance codes. thus, for each unit-distance code the set of pages may be associated with respective subsets of the set of read voltages. then, for each unit-distance code a set of average read voltage drifts corresponding to one of the set of pages may be identified. the memory device may be operated using a unit-distance code associated with a smaller range of the set of average read voltage drifts than ranges of sets of average read voltage drifts associated with other unit-distance codes.
Inventor(s): Yang Liu of San Jose CA (US) for micron technology, inc., Steven Michael Kientz of Westminster CO (US) for micron technology, inc., Tingjun Xie of Milpitas CA (US) for micron technology, inc., Aaron Lee of Sunnyvale CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Wei Wang of Fremont CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C29/52
CPC Code(s): G11C16/3418
Abstract: an example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. the processing device is configured to initiate a scan operation on a plurality of block families of the memory device. each of the plurality of block families is assigned to a voltage offset bin of a plurality of voltage offset bins. the processing device further determines that a number of scan operations to be performed in one scan interval is greater than a maximum number of scan operations to be performed in a scan interval. the processing device further determines based on the voltage offset bins of the plurality of block families and a time elapsed since execution of a previous scan operation of the plurality of block families, a scan priority of each of the plurality of block families, and schedules, based on the scan priority, a scan operation of one or more block families of the plurality of block families during one or more subsequent scan intervals. based on the scan result, two or the plurality of block families which are scanned within the same or different intervals can be combined and thus release block family memory if their measurement results satisfy combining criterion.
Inventor(s): Aaron Yip of Los Gatos CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10, G11C16/24
CPC Code(s): G11C16/3427
Abstract: apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. a programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. the selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. additional methods and apparatus are disclosed.
Inventor(s): Kai Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G11C29/42, G11C7/06, G11C7/10, G11C29/12
CPC Code(s): G11C29/42
Abstract: methods, systems, and devices for techniques for initializing memory error correction are described. a memory system may perform operations relating to writing data to multiple memory cells belonging to one or more rows of the memory system in response to a single write command. for example, the memory system may receive (e.g., from a host system) an activation command (e.g., a row group activation command) indicating a row group address. the memory system may activate a set of rows indicated by the row group address. in response to a write command (e.g., a row group write command), the memory system may write data in a respective memory cell of each row indicated by the row group address. for example, each memory cell to be written may correspond to a column address included in the write command. the memory system may write a same logic state to each memory cell.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C11/408, G11C11/4096
CPC Code(s): G11C29/52
Abstract: apparatuses, systems, and methods for half-page modes. a memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. in some memory devices, each half of the memory cells may be separately activated by different word line portions. in some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. the additional information may be provided along additional data terminals so as not to increase the data burst length.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C11/408, G11C11/4096
CPC Code(s): G11C29/52
Abstract: apparatuses, systems, and methods for half-page modes. a memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. in some memory devices, each half of the memory cells may be separately activated by different word line portions. in some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. the additional information may be provided along additional data terminals so as not to increase the data burst length.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc., Bret K. Street of Meridian ID (US) for micron technology, inc., Akshay N. Singh of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Bharat Bhushan of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/48, H01L23/498, H01L25/18, H10B80/00
CPC Code(s): H01L24/08
Abstract: a semiconductor device assembly with layered dielectric is disclosed. the semiconductor device assembly includes a first semiconductor die and a second semiconductor die coupled with the first semiconductor die. the second semiconductor die is at least partially surrounded by a tensile dielectric and a compressive dielectric disposed at the first semiconductor die. the tensile dielectric is configured to experience tensile stress at an upper surface and compressive stress at a lower surface (e.g., the tensile dielectric will warp concave down). in contrast, the compressive dielectric is configured to experience compressive stress at an upper surface and tensile stress at a lower surface (e.g., the compressive dielectric will warp concave up). as a result, stress in the semiconductor device assembly can be reduced and overall yield can be improved.
Inventor(s): Christopher Glancey of Boise ID (US) for micron technology, inc., Shams U. Arifeen of Boise ID (US) for micron technology, inc., Koustav Sinha of Boise ID (US) for micron technology, inc., Quang Nguyen of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/13
Abstract: semiconductor die assemblies with flexible interconnects, and associated methods and systems are disclosed. the semiconductor die assembly includes a package substrate and a semiconductor die attached to the package substrate through the flexible interconnects. the flexible interconnects include one or more rigid sections and one or more flexible sections, each of which is disposed next to the rigid sections. the flexible sections may include malleable materials with relatively low melting temperatures (e.g., having relatively low modulus at elevated temperatures) such that the flexible interconnects can have reduced flexural stiffness during the assembly process. the malleable materials of the flexible interconnects, through plastic deformation in response to stress generated during the assembly process, may facilitate portions of the flexible interconnects to shift so as to reduce transfer of the stress to other parts of the semiconductor die assembly-e.g., circuitry of the semiconductor die.
Inventor(s): Brandon P. Wirz of Boise ID (US) for micron technology, inc., David R. Hembree of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L25/065
CPC Code(s): H01L24/14
Abstract: a semiconductor device assembly is provided. the assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. the assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. the first solder joint thickness is less than the second solder joint thickness.
Inventor(s): Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/065, H01L25/00
CPC Code(s): H01L25/0657
Abstract: semiconductor devices having three-dimensional bonding schemes and associated systems and methods are disclosed herein. in some embodiments, the semiconductor device includes a package substrate, a stack of semiconductor dies carried by the package substrate, and an interconnect module carried by the package substrate adjacent the stack of semiconductor dies. the stack of semiconductor dies can include a first die carried by the package substrate and a second die carried by the first die. meanwhile, the interconnect module can include at least a first tier and a second tier. the first tier can be carried by and electrically coupled to the package substrate, and the second tier can be carried by and electrically coupled to the first tier. in turn, the second die can be electrically coupled to the second tier.
Inventor(s): Zhanqiang Su of Shanghai (CN) for micron technology, inc., Junjun Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): H04L1/00, H04L1/1812, H04L1/20
CPC Code(s): H04L1/0061
Abstract: methods, systems, and devices for enhanced negative acknowledgment control (nac) frame are described. a device may generate and communicate an enhanced nac frame that includes additional error information to indicate to the device a cause for the error. the device may receive a data frame and determine an error condition associated with a set of layers of a protocol stack. the device may generate feedback indicating a cause for the determined error condition and transmit the feedback indicating the error cause. the feedback may be a nac that includes a first quantity of bits configured for indicating an existence of an error and a second quantity of bits configured for indicating the error cause. a format of the nac frame may include bits configured to identify multiple types of error causes associated with the different layers of the protocol stack.
Inventor(s): Albert Fayrushin of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/35, H10B43/35
CPC Code(s): H10B43/27
Abstract: a microelectronic device includes a stack structure, a cell pillar structure, doped semiconductor material, and control logic devices. the stack structure includes vertically neighboring tiers respectively including a conductive structure and an insulative structure vertically neighboring the conductive structure. the cell pillar structure vertically extends through the stack structure and includes a fill material, a channel material horizontally surrounding the fill material, and an outer material stack horizontally surrounding the channel material. the doped semiconductor material vertically overlies the stack structure and includes a first portion substantially continuously horizontally extending over the stack structure and the cell pillar structure, and a second portion vertically projecting from the first portion and in physical contact with the channel material of the cell pillar structure. the control logic devices vertically underlie and are coupled to the cell pillar structures. related methods, memory devices, and electronic systems are also described.
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a conductive contact, a conductive portion formed over the conductive contact, and data lines located over the first conductive portion and separated from the first conductive portion by a dielectric material, the data lines formed from respective levels of conductive materials, and a conductive structure located on a side of the levels of conductive materials. the levels of conductive materials are stacked one over another in a first direction in different levels of the apparatus. the conductive structure includes a first portion and a second portion. the first portion extends in the first direction and coupled to a level of conductive material among the levels of conductive materials. the second portion extends in a second direction and coupled to the conductive portion.
Inventor(s): Adharsh Rajagopal of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc., Yi Fang Lee of Boise ID (US) for micron technology, inc., Glen H. Walters of Baltimore MD (US) for micron technology, inc., Alexandre Marc Subirats of Boise ID (US) for micron technology, inc., Yuanzhi Ma of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/786, H01L29/423, H01L29/49, H01L29/66
CPC Code(s): H10D30/6755
Abstract: systems, methods and apparatus are provided for transistors having a channel region comprising a crystalline spinel indium-gallium-zinc-oxide (igzo) material.
Micron Technology, Inc. patent applications on March 6th, 2025
- Micron Technology, Inc.
- G06F3/06
- CPC G06F3/0611
- Micron technology, inc.
- CPC G06F3/0613
- G06F13/42
- CPC G06F3/0644
- CPC G06F3/0659
- G06F11/10
- CPC G06F11/1044
- CPC G06F11/1064
- CPC G06F11/108
- G06F11/20
- G06F11/16
- CPC G06F11/2056
- G06F12/02
- G06F12/0882
- G06F13/16
- CPC G06F12/0238
- CPC G06F12/0246
- G06F12/06
- CPC G06F12/0638
- CPC G06F12/0646
- G06F13/30
- CPC G06F13/30
- G11C7/10
- G11C5/04
- G11C7/22
- CPC G11C7/109
- CPC G11C7/1096
- G11C11/406
- CPC G11C11/40615
- G11C11/4074
- G11C5/14
- G11C11/4076
- CPC G11C11/4074
- G11C11/4091
- H10B12/00
- G11C11/4078
- CPC G11C11/4078
- G11C11/4096
- G11C11/4093
- CPC G11C11/4096
- G11C11/4097
- G11C11/408
- CPC G11C11/4097
- G11C16/10
- G11C16/08
- G11C16/28
- CPC G11C16/102
- G11C16/26
- G11C11/56
- CPC G11C16/26
- G11C16/34
- G11C29/52
- CPC G11C16/3418
- G11C16/04
- G11C16/24
- CPC G11C16/3427
- G11C29/42
- G11C7/06
- G11C29/12
- CPC G11C29/42
- CPC G11C29/52
- H01L23/00
- H01L23/48
- H01L23/498
- H01L25/18
- H10B80/00
- CPC H01L24/08
- CPC H01L24/13
- H01L25/065
- CPC H01L24/14
- H01L25/00
- CPC H01L25/0657
- H04L1/00
- H04L1/1812
- H04L1/20
- CPC H04L1/0061
- H10B43/27
- H10B41/27
- H10B41/35
- H10B43/35
- CPC H10B43/27
- H01L29/786
- H01L29/423
- H01L29/49
- H01L29/66
- CPC H10D30/6755
