Micron Technology, Inc. patent applications on March 20th, 2025
Patent Applications by Micron Technology, Inc. on March 20th, 2025
Micron Technology, Inc.: 43 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (10), G06F13/16 (6), G06F12/02 (5), H10B43/27 (4), H10B41/27 (3) G06F3/0659 (4), G06F13/1668 (2), G06F11/0772 (2), G06F12/0292 (2), H10B41/27 (2)
With keywords such as: memory, data, device, material, physical, structures, include, region, methods, and systems in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): William A. Lendvay of Boise ID US for micron technology, inc., Paul Zipp of Boise ID US for micron technology, inc., Yoshihisa Fukushima of Hachioji JP for micron technology, inc., Mamoru Nagase of Yokohama JP for micron technology, inc., Tetsuya Shibata of Sagamihara JP for micron technology, inc.
IPC Code(s): G06F1/3234, G11C5/14
CPC Code(s): G06F1/3253
Abstract: methods, systems, and devices for programming power management circuits in a system are described. an apparatus may include a set of one or more power management circuits configured to provide one or more operating voltages for the apparatus. the apparatus may also include an interface coupled with a controller via a bus. the apparatus may include a first switching circuit configured to isolate the bus from the controller and to couple the bus with a second switching circuit. the second switching circuit may be configured to isolate the set of one or more power management circuits from the controller and to couple the set of one or more power management circuits with the first switching circuit.
Inventor(s): Donald Martin Morgan of Meridian ID US for micron technology, inc., Alan J. Wilson of Boise ID US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0604
Abstract: methods, systems, and devices for retiring pages of a memory device are described. an ordered set of device information pages may be used to store device information. the device information pages may be in non-volatile memory. each page may include a counter value of the number of accesses to indicate if the page includes valid data. a flag associated with the page may be set when the counter value reaches a threshold, to retire the page. upon power-up, the device may determine which page to use, based on the flags. the flag may be stored in the page, or may be separate (e.g., fuse elements). if fuse elements are used, the page may store a programming-in-process flag to indicate when programming of the fuse element may not have been completed before power loss, in which case the programming may be restarted after power is restored.
20250094047. DUAL COMPRESSION IN MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio Mi IT for micron technology, inc., Rishabh Dubey of Agrate Brianza IT for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio Mi IT for micron technology, inc., Danilo Caraccio of Milano IT for micron technology, inc., Emanuele Confalonieri of Segrate IT for micron technology, inc., Nicola Del Gatto of Cassina de' Pecchi IT for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: a variety of applications can include a memory device implementing a dual compression scheme. a memory subsystem of the memory device can be arranged into multiple regions. a first region of the memory subsystem can be used to store non-compressible data. a second region can be used to store compressible data. the second region can have a first subregion and a second subregion. the first subregion can be used to accept compressible data as non-compressed data corresponding to a compression ratio being less than a threshold compression ratio. the second subregion can be used to accept compressed data corresponding to a compression ratio being greater than the threshold compression ratio. additional apparatus, systems, and methods are disclosed.
20250094054. Efficient Command Protocol_simplified_abstract_(micron technology, inc.)
Inventor(s): Kang-Yong Kim of Boise ID US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: this document describes apparatuses and techniques for an efficient command protocol for memory access. in various aspects, a memory controller may implement combined operations of different command types (e.g., an activation command plus a read, an activation command plus a write, or an activation command plus a pre-charge command) to better utilize a multiple clock ratio of a command bus (e.g., a (1.5+0.5) n operation in a dual clocking wck2ck ratio of 4:1), which may improve utilization of a data bus for associated memory responses. by so doing, the efficient command protocol may improve power efficiency and system level performance of a computing system.
Inventor(s): Yu-Chung Lien of San Jose CA US for micron technology, inc., Zhenming Zhou of San Jose CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. a wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. existing data stored by a second set of memory cells is read. an expected data state metrics is produced for each data partition of the plurality of data partitions. a data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. the identified data partition is programmed to the identified wordline.
20250094071. TECHNIQUES FOR DATA TRANSFER OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Jotiba Koparde of Bangalore IN for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: methods, systems, and devices for techniques for data transfer operations are described. a memory system may select a source set of memory cells and a destination set of memory cells using one or more counters corresponding to access operations for the source and the destination. for example, as part of a data transfer operation, the memory system may prioritize transferring data from a block with a lower quantity of read operations to a block with a lower quantity of access operations. in some cases, the memory system may prioritize transferring data from a page with a lower quantity of read operations to a page with a slower read duration.
Inventor(s): Robert Winston Mason of Boise ID US for micron technology, inc., Tieniu Li of San Jose CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: methods, systems, and devices for methods for performing voltage sweep operations are described. based on detecting a failure at a portion of a memory device, the memory system controller may initialize a voltage sweep operation to identify threshold voltages of the memory cells at the portion of the memory device. in one example, the memory system controller may identify and store a value (e.g., a delta value) that represents a difference between a quantity of transitions experienced by a first memory cell at a first voltage iteration and a quantity of transitions experienced by the first memory cell at a second voltage iteration. in another example, the memory system controller may identify the quantity of transitions from a first logic state to a second logic state and a quantity of transitions from the second logic state to a first logic state and store such values in respective memory arrays.
20250094085. TECHNIQUES FOR ATOMIC WRITE OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Luca Porzio of Casalnuovo IT for micron technology, inc., Christian M. Gyllenskog of Meridian ID US for micron technology, inc., Dionisio Minopoli of Frattamaggiore IT for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for techniques for atomic write operations are described. a memory system may determine a set of pages for an atomic write operation in which data associated with a write command is linked together for writing to a non-volatile memory. the memory system may write, to the non-volatile memory, metadata that indicates the set of pages is associated with the atomic write operation. based on the metadata, the memory system may determine whether each page of the set of pages has been written with data for the atomic write operation. the memory system may then communicate to a host system an indication of a completion status for the atomic write operation based on determining whether each page of the set of pages has been written with the data for the atomic write operation.
Inventor(s): Zhengbo Wang of Shanghai CN for micron technology, inc., Jia Sun of Shanghai CN for micron technology, inc., Ming Ma of Shanghai CN for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for techniques for firmware enhancement in memory devices are described. a memory system may include a volatile memory device and a non-volatile memory device, which may store a node address mapping. a host system in communication with the memory system may transmit a command instructing the memory system to transfer at least a portion of the node address mapping from the non-volatile memory device to the volatile memory device. the memory system may transmit a response to the command to the host system indicating a status associated with transferring the portion of the node address mapping.
Inventor(s): Daniel James Gunderson of Longmont CO US for micron technology, inc.
IPC Code(s): G06F3/06, G06F11/14
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for predictive media management for read disturb are described. a read disturbance manager can monitor a bit error rate for a block of a memory die. the read disturbance manager can detect that a degradation of the bit error rate satisfies a degradation threshold specific to the memory die. in some cases, the read disturbance manager can perform a write operation to write data from the block of the memory die to a second block of the memory die based on detecting that the degradation of the bit error rate satisfies the degradation threshold.
20250094091. READ DATA ALIGNMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Sheng Hsu of San Jose CA US for micron technology, inc., Chihching Chen of Milpitas CA US for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: systems, apparatuses, and methods related to a controller architecture for read data alignment are described. an example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. the method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
20250094242. CHAINED RESOURCE LOCKING_simplified_abstract_(micron technology, inc.)
Inventor(s): Patrick Estep of Rowlett TX US for micron technology, inc., Tony M. Brewer of Plano TX US for micron technology, inc.
IPC Code(s): G06F9/52, G06F9/50
CPC Code(s): G06F9/526
Abstract: devices and techniques for chained resource locking are described herein. threads form a last-in-first-out (lifo) queue on a resource lock to create a chained lock on the resource. a data store representing the lock for the resource holds the previous thread's identifier, enabling a subsequent thread to wake the previous thread using the identifier when the subsequent thread releases the lock. generally, the thread releasing the lock need not interact with the data store, reducing contention for the data store among many threads.
Inventor(s): Paul Dlugosch of Eagle ID US for micron technology, inc.
IPC Code(s): G06F9/54, G06F11/30, G06F11/34, G06F15/173, G06F15/82, G06N5/02
CPC Code(s): G06F9/544
Abstract: programmable devices, hierarchical parallel machines and methods for providing state information are described. in one such programmable device, programmable elements are provided. the programmable elements are configured to implement one or more finite state machines. the programmable elements are configured to receive an n-digit input and provide a m-digit output as a function of the n-digit input. the m-digit output includes state information from less than all of the programmable elements. other programmable devices, hierarchical parallel machines and methods are also disclosed.
20250094262. Usage-Based-Disturbance Alert Signaling_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID US for micron technology, inc., Victor Wong of Boise ID US for micron technology, inc., Donald Morgan of Meridian ID US for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0772
Abstract: apparatuses and techniques for implementing usage-based-disturbance alert signaling are described. the technology allows usage-based-disturbance (ubd) alerts to be externally communicated from a memory device without a dedicated external interface. rather, ubd alerts are combined with memory error/alert signals and communicated on a shared alert-related interface. ubd tracking occurs at the memory bank level, with corresponding independent ubd alert signals. these signals are efficiently combined to generate an overall ubd alert. a temporary backoff signal is generated when an overall ubd alert is sent. the backoff signal ensures requisite external timing parameters are met while allowing the individual memory banks to generate persistent ubd alerts.
Inventor(s): Noorshaheen Mavungal Noorudheen of Long Beach CA US for micron technology, inc., Sudhakar Ravindra Parab of Bengaluru IN for micron technology, inc., Sanjay Tanaji Shinde of Bangalore IN for micron technology, inc.
IPC Code(s): G06F11/07, G06F11/10
CPC Code(s): G06F11/0772
Abstract: aspects of the present disclosure configure a system component, such as memory sub-system controller, to pause memory sub-system operations in response to a critical event. the memory sub-system controller can include a front-end (fe) device that stores critical event trigger data in trigger event logic registers. upon detecting that operations of the memory sub-system, such as command latencies, correspond to the critical event trigger data, the fe device performs pause operations, including storing a state of the memory sub-system and transmitting an interrupt signal to the memory sub-system controller, such as a cpu, to initiate debugging operations.
Inventor(s): Marco SFORZIN of Cernusco sul Naviglio IT for micron technology, inc., Emanuele CONFALONIERI of Segrate IT for micron technology, inc., Daniele BALLUCHI of Milano IT for micron technology, inc., Danilo CARACCIO of Milano IT for micron technology, inc., Nicola DEL GATTO of Cassina de’ Pecchi IT for micron technology, inc., Rishabh DUBEY of Boise ID US for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1016
Abstract: provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. the logical-to-physical (l2p) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. when a die containing l2p data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.
20250094303. HOST SYSTEM DIAGNOSTIC TESTING_simplified_abstract_(micron technology, inc.)
Inventor(s): Binbin Huo of Taufkirchen DE for micron technology, inc., Olivier Duval of for micron technology, inc.
IPC Code(s): G06F11/30, G06F11/34, G06F13/16
CPC Code(s): G06F11/3037
Abstract: methods, systems, and devices for host system diagnostic testing are described. a diagnostic tool including a diagnostic executable stored to an external memory may evaluate a system including a host subsystem and a memory subsystem. upon initialization, the diagnostic executable may configure trace points in one or more layers (e.g., associated with an operating system) of the host subsystem based on dependencies (e.g., libraries) stored to the external memory, and may receive, from the host subsystem, first data collected at the trace points, directly from a host system buffer, or from the memory subsystem. concurrent to the collection procedure, the diagnostic executable may perform processing operations on the first data to generate second data, which may be associated with one or more metrics of system performance. the second data is stored to the external memory, and may be utilized to evaluate the system.
Inventor(s): Yanhua Bi of Shanghai CN for micron technology, inc.
IPC Code(s): G06F12/02, G06F13/16
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for data organization for logical to physical table compression are described. the memory system may identify a region that includes one or more logical addresses associated with discontinuous corresponding physical addresses. the memory system may include a plurality of regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. the memory system may determine a period of inactivity of access operations on the plurality of memory cells and rearrange, during the period of inactivity, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the plurality of physical addresses.
20250094339. SMART FACTORY RESET PROCEDURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Giuseppe Cariello of Boise ID US for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/0891
CPC Code(s): G06F12/0246
Abstract: methods, systems, techniques, and devices for smart factory reset procedures are described. in accordance with examples as disclosed herein, a memory system may receive one or more commands associated with a reset procedure. the memory system may identify, in response to the one or more commands, a first portion of one or more memory arrays of the memory system as storing user data and a second portion of the one or more memory arrays as storing data associated with an operating system. the memory system may update a mapping of the memory system based on identifying the first portion and the second portion. the memory system may transfer the data associated with the operating system to a third portion of the one or more memory arrays and perform an erase operation on a subset of physical addresses of the set of physical addresses.
20250094341. TECHNIQUES FOR ACCESSING MANAGED NAND_simplified_abstract_(micron technology, inc.)
Inventor(s): Junjun Wang of Shanghai CN for micron technology, inc., Yi Heng Sun of Shanghai CN for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/06
CPC Code(s): G06F12/0253
Abstract: methods, systems, and devices for techniques for accessing managed not-and (nand) memory are described. an indicator of a first type that indicates whether each physical address in a group of physical addresses stores valid data may be accessed. indicators of a second type may be used to indicate whether respective physical addresses of the group of physical addresses store valid data. data stored at the group of physical addresses may be transferred to a different group of physical addresses based on the indicator of the first type. also, another indicator of the first type that indicates whether each physical address in the different group of physical addresses stores valid data may be updated.
20250094343. DYNAMIC PAGE MAPPING WITH COMPRESSION_simplified_abstract_(micron technology, inc.)
Inventor(s): Rishabh Dubey of Agrate Brianza IT for micron technology, inc., Marco Sforzin of Cernusco Sul Naviglio MI IT for micron technology, inc., Emanuele Confalonieri of Segrate IT for micron technology, inc., Danilo Caraccio of Milano IT for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio MI IT for micron technology, inc., Nicola Del Gatto of Cassina de’ Pecchi (MI) IT for micron technology, inc.
IPC Code(s): G06F12/02, G06F13/16
CPC Code(s): G06F12/0292
Abstract: a variety of applications can include a memory device having dynamic page mapping with compression. the memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. the entry location can include a flag along with the physical address of the first stripe. the flag can identify data of the virtual page as being compressed or uncompressed. a controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. the header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. additional apparatus, systems, and methods are disclosed.
20250094344. CHAINED MAPPING WITH COMPRESSION_simplified_abstract_(micron technology, inc.)
Inventor(s): Rishabh Dubey of Agrate Brianza IT for micron technology, inc., Marco Sforzin of Cernusco Sul Naviglio MI IT for micron technology, inc., Emanuele Confalonieri of Segrate IT for micron technology, inc., Danilo Caraccio of Milano IT for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio MI IT for micron technology, inc., Nicola Del Gatto of Cassina de' Pecchi (MI) IT for micron technology, inc.
IPC Code(s): G06F12/02, G06F13/16
CPC Code(s): G06F12/0292
Abstract: a variety of applications can include a memory device having chained mapping with compression of received data. the memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. a controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. additional apparatus, systems, and methods are disclosed.
Inventor(s): Alexander Tomlinson of Austin TX US for micron technology, inc., Gaurav Sanjay Ramdasi of Pune IN for micron technology, inc., Gregory Alan Becker of Austin TX US for micron technology, inc.
IPC Code(s): G06F12/0875
CPC Code(s): G06F12/0875
Abstract: an event trigger to flush key-value data from a volatile memory device is detected. in response to detection of the event trigger, a determination is made whether the key-value data comprises uncommitted data for one or more active database transactions. if the key-value data comprises uncommitted data for one or more active database transactions, the uncommitted data is moved to a hold aside buffer in the volatile memory device, and committed data in the key-value data is stored on a non-volatile memory device.
20250094364. STATUS CHECK USING CHIP ENABLE PIN_simplified_abstract_(micron technology, inc.)
Inventor(s): Chulbum Kim of San Jose CA US for micron technology, inc., Mark A. Helm of Santa Cruz CA US for micron technology, inc., Yoav Weinberg of Thornhill CA for micron technology, inc.
IPC Code(s): G06F13/16, G06F1/26
CPC Code(s): G06F13/1668
Abstract: methods, systems, and devices for status check using chip enable pin are described. an apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. the status may indicate, for example, whether the memory device is available to receive a command. the driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. in some cases, the pin may be an example of a chip enable pin.
20250094365. KERNEL MAPPING TO NODES IN COMPUTE FABRIC_simplified_abstract_(micron technology, inc.)
Inventor(s): Gongyu Wang of Wellesley MA US for micron technology, inc., Jason Eckhardt of Austin TX US for micron technology, inc.
IPC Code(s): G06F13/16, G06F13/40, G06F15/78, G06N7/01
CPC Code(s): G06F13/1668
Abstract: a reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. compute kernels can be parsed into directed graphs and mapped to particular node or tile resources for execution. in an example, a branch-and-bound search algorithm can be used to perform the mapping. the algorithm can use a cost function to evaluate the resources based on capability, occupancy, or power consumption of the various node or tile resources.
20250094649. SAFETY AND SECURITY FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Aaron P. Boehm of Boise ID US for micron technology, inc., Lance W. Dover of Fair Oaks CA US for micron technology, inc., Steffen Buch of Munich DE for micron technology, inc.
IPC Code(s): G06F21/79, G06F21/60, G06F21/64, G06F21/72, G06F21/78, H04L9/06, H04L9/08, H04L9/32
CPC Code(s): G06F21/79
Abstract: methods, systems, and devices for safety and security for memory are described. in some examples, data associated with a memory device may be authenticated before an associated operation is executed. the data may be authenticated before it is executed at a volatile memory. the data may be associated with a hash (e.g., a first hash) and may be communicated from the memory device to a host device. at the host device, the data and the first hash may be written (e.g., stored) to temporary storage, such as a cache. once stored to the cache, the host device may generate an additional hash (e.g., a second hash) related to the data using a key inaccessible to the memory device. if the first hash and second hash match, the data may be authenticated and one or more operations may be executed.
20250095699. PROGRAMMABLE COLUMN ACCESS_simplified_abstract_(micron technology, inc.)
Inventor(s): Hyunyoo Lee of Boise ID US for micron technology, inc., Kang-Yong Kim of Boise ID US for micron technology, inc., Taeksang Song of San Jose CA US for micron technology, inc.
IPC Code(s): G11C7/10, G11C8/06, G11C11/4074
CPC Code(s): G11C7/1039
Abstract: methods, systems, and devices for programmable column access are described. a device may transfer voltages from memory cells of a row in a memory array to respective digit lines for the memory cells. the voltages may be indicative of logic values stored at the memory cells. the device may communicate respective control signals to a set of multiplexers coupled with the digit lines, where each multiplexer is coupled with a respective subset of the digit lines. each multiplexer may couple a digit line of the respective subset of digit lines with a respective sense component for that multiplexer based on the respective control signal for that multiplexer.
Inventor(s): William C. Waldrop of Allen TX US for micron technology, inc., Liang Chen of Allen TX US for micron technology, inc., Shingo Mitsubori of Inagi, Tokyo JP for micron technology, inc., Ryo Fujimaki of Sagamihara, Kanagawa JP for micron technology, inc., Atsuko Momma of Hachioji, Tokyo JP for micron technology, inc.
IPC Code(s): G11C11/4076, G11C11/4096
CPC Code(s): G11C11/4076
Abstract: apparatuses, systems, and methods for a per-dram addressability (pda) synchronizer circuit. the pda synchronizer circuit receives a write command signal which may be synchronous to a dqs clock as part of a first pda mode or asynchronous as part of a second pda mode. the pda synchronizer circuit includes a delay path which provides a first pda signal responsive to the write command signal and a synchronizer which provides a second pda signal responsive to the write command signal. the pda synchronizer circuit provides a synchronized write command signal responsive to whichever of the first pda signal or the second pda signal was provided first. when a pda mode is disabled, the write command signal may be passed as the synchronized write command signal.
Inventor(s): Eric Carman of Boise ID US for micron technology, inc., Christopher Morzano of Boise ID US for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/408, G11C11/4094
CPC Code(s): G11C11/4091
Abstract: systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. an apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. a first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. a second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.
20250095746. DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Carmine Miccoli of Boise ID US for micron technology, inc., Andrew Bicksler of Nampa ID US for micron technology, inc.
IPC Code(s): G11C16/12, G11C16/08, G11C16/10, G11C16/24, G11C16/32
CPC Code(s): G11C16/12
Abstract: processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. a first set of programming pulses corresponding to a first step voltage level are caused to be applied to program the set of memory cells. the processing logic determines that a programming voltage level associated with a programming pulse of the first set of one or more programming pulses satisfies a condition. the first set voltage is adjusted to a second step voltage level in response to the condition being satisfied.
Inventor(s): Anilkumar Chandolu of Boise ID US for micron technology, inc., Indra V. Chary of Boise ID US for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/535, H10B41/27, H10B43/27
CPC Code(s): H01L21/76895
Abstract: a method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. the memory-block regions comprise part of a memory-plane region. a pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. the pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. other embodiments, including structure independent of method, are disclosed.
Inventor(s): Faxing CHE of Singapore SG for micron technology, inc., Chong Leong GAN of Taichung TW for micron technology, inc., Yeow Chon ONG of Toa Payoh SG for micron technology, inc., Hong Wan NG of Singapore SG for micron technology, inc.
IPC Code(s): H01L21/66, H01L23/00, H01L23/31, H01L25/065
CPC Code(s): H01L22/30
Abstract: implementations described herein relate to techniques and apparatuses related to a structure that may be used for characterizing properties related to an interfacial adhesion strength between an epoxy mold compound and a vertical edge of a semiconductor die included in a semiconductor die package. the techniques and apparatuses may be used to provide a more comprehensive understanding of interfacial adhesion strengths within the semiconductor die package relative to techniques available in semiconductor industry standards.
Inventor(s): Bharat Bhushan of Taichung TW for micron technology, inc., Akshay N. Singh of Boise ID US for micron technology, inc., Kunal R. Parekh of Boise ID US for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/304, H01L21/683, H01L23/48, H01L23/544, H01L25/065, H10B80/00
CPC Code(s): H01L24/08
Abstract: a method of forming a semiconductor wafer is provided. the method includes dicing wafers into dies, testing the dies for known good dies, and bonding known good dies to a carrier wafer to form a top kgd wafer. the method also includes filling gaps between top dies to form a top gap-fill layer around and above each of the top dies, and bonding the top dies with a dummy silicon wafer. the method also includes bonding known good dies to carrier wafers to form one or more core kgd wafers, as well as filling gaps between the core dies to form a core gap-fill layer around each of the core dies. the method then includes bonding the one or more core kgd wafers to the top kgd wafer to form a kgd wafer stack.
20250096202. STACKED SEMICONDUCTOR DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Bharat Bhushan of Taichung TW for micron technology, inc., Bret K. Street of Meridian ID US for micron technology, inc., Akshay N. Singh of Boise ID US for micron technology, inc., Kunal R. Parekh of Boise ID US for micron technology, inc., Wei Zhou of Boise ID US for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/00, H10B80/00
CPC Code(s): H01L25/0657
Abstract: a semiconductor device assembly is provided. the semiconductor device assembly includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die, and a second plurality of stacked memory dies mounted on and electrically coupled with the first plurality of stacked memory dies. a first dielectric material is disposed around the first plurality of stacked memory dies. a second dielectric material is disposed at the first dielectric material and surrounding the second plurality of stacked memory dies. a third dielectric material is disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies and between the first dielectric material and the second dielectric material.
20250097030. EMBEDDED HARDWARE SECURITY MODULE (HSM)_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhan Liu of Cupertino CA US for micron technology, inc.
IPC Code(s): H04L9/08, H04L9/32
CPC Code(s): H04L9/0897
Abstract: the disclosed embodiments relate to hardware security modules. in one embodiment, a method is disclosed comprising reading a random value from a physically unclonable function (puf); generating a seed value from the random value; generating a cryptographic key using the seed value; and processing a cryptographic operation using the cryptographic key.
20250098126. DEVICE TEMPERATURE ADJUSTMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Tracy D. Evans of Boise ID US for micron technology, inc., Gloria Y. Yang of Boise ID US for micron technology, inc., Jiewei Chen of Meridian ID US for micron technology, inc., Jing Zhou of Boise ID US for micron technology, inc.
IPC Code(s): H05K7/20, G05B15/02
CPC Code(s): H05K7/20836
Abstract: systems associated with device temperature adjustment are described. a device temperature adjustment system can include an electronic device having a temperature sensor integrated therein to detect a temperature of the electronic device and a temperature adjust module coupled to the electronic device to adjust a temperature of the electronic device based on the detected temperature.
Inventor(s): Shuangqiang Luo of Boise ID US for micron technology, inc., Brett D. Lowe of Boise ID US for micron technology, inc.
IPC Code(s): H10B41/27, G11C5/02, G11C5/06, H01L23/528, H10B43/27
CPC Code(s): H10B41/27
Abstract: a microelectronic device comprises a stack structure, slot structures vertically extending completely through the stack structure, and support pillar structures vertically extending through the stack structure. the stack structure comprises tiers vertically stacked relative to one another, each tier including a conductive material and insulative material vertically neighboring the conductive material. the stack structure includes a staircase structure therein comprising steps defined by edges of at least some of the tiers. the support pillar structures are arranged in rows horizontally extending in a first direction. the slot structures divide the stack structure into block structures. the microelectronic device further comprises additional slot structures within a horizontal area of one of the block structures. the additional slot structures include a first additional slot structure at least partially intersecting one of the rows of the support pillar structures. the additional slot structures also include a second additional slot structure horizontally spaced apart from the first additional slot structure and each of the rows of the support pillar structures in a second direction orthogonal to the first direction.
20250098159. MEMORY DEVICES INCLUDING PAD STRUCTURES_simplified_abstract_(micron technology, inc.)
Inventor(s): Erwin E. Yu of San Jose CA US for micron technology, inc., Michele Piccardi of Cupertino CA US for micron technology, inc., Surendranath C. Eruvuru of Boise ID US for micron technology, inc.
IPC Code(s): H10B41/27, B81B1/00, G11C5/02, G11C5/06, H01L23/538, H01L27/092, H10B43/27
CPC Code(s): H10B41/27
Abstract: a microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. the base structure comprises a logic region including logic devices. the memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. the conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. memory devices and electronic systems are also described.
20250098169. Integrated Structures_simplified_abstract_(micron technology, inc.)
Inventor(s): Justin B. Dorhout of Boise ID US for micron technology, inc., David Daycock of Boise ID US for micron technology, inc., Kunal R. Parekh of Boise ID US for micron technology, inc., Martin C. Roberts of Boise ID US for micron technology, inc., Yushi Hu of Boise ID US for micron technology, inc.
IPC Code(s): H10B43/27, H01L29/66, H01L29/76, H01L29/78
CPC Code(s): H10B43/27
Abstract: some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. the monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. a first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. the first vertically-extending region contains a first material. a second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. the second vertically-extending region contains a material which is different in composition from the first material.
Inventor(s): Qian Tao of Boise ID US for micron technology, inc., Matthew N. Rocklein of Boise ID US for micron technology, inc., Beth R. Cook of Boise ID US for micron technology, inc., D. V. Nirmal Ramaswamy of Boise ID US for micron technology, inc.
IPC Code(s): H10B53/30, H10N70/00, H10N70/20
CPC Code(s): H10B53/30
Abstract: an electronic device comprises ferroelectric random access memory cells. one or more of the ferroelectric random access memory cells comprises a crystallized ferroelectric material and an electrode adjacent to the crystallized ferroelectric material. the crystallized ferroelectric material exhibits a dominant crystallographic orientation. the electrode comprises a crystalline material exhibiting an additional dominant crystallographic orientation inducing the dominant crystallographic orientation of the crystallized ferroelectric material. a memory device is also disclosed comprising an array of ferroelectric memory cells. the ferroelectric memory cell comprises a crystallized ferroelectric material having a first side and a second side opposite the first side, and an electrode adjacent the first side of the ferroelectric material. the crystallized ferroelectric material comprises a crystallized hafnium-based material exhibiting a dominant () crystallographic orientation. the electrode comprises a crystalline titanium nitride material formulated to induce the dominant () crystallographic orientation of the crystallized ferroelectric material.
Inventor(s): Scott E. Sills of Boise ID US for micron technology, inc., Ramanathan Gandhi of Singapore SG for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID US for micron technology, inc.
IPC Code(s): H01L29/786, H01L29/66, H10B63/00
CPC Code(s): H10D30/6728
Abstract: a method of forming a device comprises forming dielectric structures over other dielectric structures overlying conductive contact structures, the dielectric structures separated from one another by trenches and laterally extending orthogonal to the other dielectric structures and the conductive contact structures. conductive gate structures are formed on exposed side surfaces of the dielectric structures within the trenches. dielectric oxide structures are formed on exposed side surfaces of the conductive gate structures within the trenches. exposed portions of the other dielectric structures are removed to form isolation structures. semiconductive pillars are formed on exposed side surfaces of the dielectric oxide structures and the isolation structures within the trenches. the semiconductive pillars are in electrical contact with the conductive contact structures. additional conductive contact structures are formed on upper surfaces of the semiconductive pillars. a device, a memory device, and an electronic system are also described.
Inventor(s): Scott E. Sills of Boise ID US for micron technology, inc., Kirk D. Prall of Boise ID US for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID US for micron technology, inc., Ramanathan Gandhi of Boise ID US for micron technology, inc.
IPC Code(s): H01L29/78, H01L29/06, H01L29/08, H01L29/10, H01L29/51, H10B51/20, H10B53/20
CPC Code(s): H10D30/701
Abstract: a device comprises an array comprising rows and columns of elevationally-extending transistors. an access line interconnects multiple of the elevationally-extending transistors along individual of the rows. the transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. the channel region comprises an oxide semiconductor. a transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. at least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. other embodiments, including method embodiments, are disclosed.
Inventor(s): Martin F. Schubert of Mountain View CA US for micron technology, inc.
IPC Code(s): H01L33/62, H01L27/15, H01L31/02, H01L31/0304, H01L33/00, H01L33/32, H01L33/38
CPC Code(s): H10H20/857
Abstract: high-voltage solid-state transducer (sst) devices and associated systems and methods are disclosed herein. an sst device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of sst dies connected in series between the first and second terminals. the individual sst dies can include a transducer structure having a p-n junction, a first contact and a second contact. the transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. the first and second terminals can be configured to receive an output voltage and each sst die can have a forward junction voltage less than the output voltage.
Micron Technology, Inc. patent applications on March 20th, 2025
- Micron Technology, Inc.
- G06F1/3234
- G11C5/14
- CPC G06F1/3253
- Micron technology, inc.
- G06F3/06
- CPC G06F3/0604
- CPC G06F3/0608
- CPC G06F3/0613
- CPC G06F3/0619
- CPC G06F3/0647
- CPC G06F3/0653
- CPC G06F3/0659
- G06F12/06
- G06F11/14
- G06F9/52
- G06F9/50
- CPC G06F9/526
- G06F9/54
- G06F11/30
- G06F11/34
- G06F15/173
- G06F15/82
- G06N5/02
- CPC G06F9/544
- G06F11/07
- CPC G06F11/0772
- G06F11/10
- CPC G06F11/1016
- G06F13/16
- CPC G06F11/3037
- G06F12/02
- CPC G06F12/0246
- G06F12/0891
- CPC G06F12/0253
- CPC G06F12/0292
- G06F12/0875
- CPC G06F12/0875
- G06F1/26
- CPC G06F13/1668
- G06F13/40
- G06F15/78
- G06N7/01
- G06F21/79
- G06F21/60
- G06F21/64
- G06F21/72
- G06F21/78
- H04L9/06
- H04L9/08
- H04L9/32
- CPC G06F21/79
- G11C7/10
- G11C8/06
- G11C11/4074
- CPC G11C7/1039
- G11C11/4076
- G11C11/4096
- CPC G11C11/4076
- G11C11/4091
- G11C11/408
- G11C11/4094
- CPC G11C11/4091
- G11C16/12
- G11C16/08
- G11C16/10
- G11C16/24
- G11C16/32
- CPC G11C16/12
- H01L21/768
- H01L23/535
- H10B41/27
- H10B43/27
- CPC H01L21/76895
- H01L21/66
- H01L23/00
- H01L23/31
- H01L25/065
- CPC H01L22/30
- H01L21/304
- H01L21/683
- H01L23/48
- H01L23/544
- H10B80/00
- CPC H01L24/08
- CPC H01L25/0657
- CPC H04L9/0897
- H05K7/20
- G05B15/02
- CPC H05K7/20836
- G11C5/02
- G11C5/06
- H01L23/528
- CPC H10B41/27
- B81B1/00
- H01L23/538
- H01L27/092
- H01L29/66
- H01L29/76
- H01L29/78
- CPC H10B43/27
- H10B53/30
- H10N70/00
- H10N70/20
- CPC H10B53/30
- H01L29/786
- H10B63/00
- CPC H10D30/6728
- H01L29/06
- H01L29/08
- H01L29/10
- H01L29/51
- H10B51/20
- H10B53/20
- CPC H10D30/701
- H01L33/62
- H01L27/15
- H01L31/02
- H01L31/0304
- H01L33/00
- H01L33/32
- H01L33/38
- CPC H10H20/857
