Micron Technology, Inc. patent applications on March 13th, 2025
Patent Applications by Micron Technology, Inc. on March 13th, 2025
Micron Technology, Inc.: 36 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (9), G11C16/34 (5), G11C16/04 (5), G11C29/44 (4), G11C16/16 (4) G06F3/0619 (2), G06F3/0655 (2), G06F11/1068 (2), G11C16/3418 (2), G11C16/16 (2)
With keywords such as: memory, device, data, access, error, read, based, voltage, include, and array in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Jonathan D. Harms of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F1/3234, G06F1/08, G06F1/3206, G06F1/324, G06F11/00, G06F11/30, G06F11/34
CPC Code(s): G06F1/3275
Abstract: methods and apparatus for using characterized devices such as memories. in one embodiment, characterized memories are associated with a range of performances over a range of operational parameters. the characterized memories can be used in conjunction with a solution density function to optimize memory searching. in one exemplary embodiment, a cryptocurrency miner can utilize characterized memories to generate memory hard proof-of-work (pow). the results may be further validated against general compute memories; such that only valid solutions are broadcasted to the mining community. in one embodiment, the validation mechanism is implemented for a plurality of searching apparatus in parallel to provide a more distributed and efficient approach. various other applications for characterized memories are also described in greater detail herein (e.g., blockchain, social media, machine learning, probabilistic applications and other error-tolerant applications).
Inventor(s): Su Wei Lim of Penang (MY) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: a system can include a memory; and a processing device, operatively coupled with the memory, to perform operations including: partitioning the memory into a plurality of memory partitions, wherein each of the plurality of memory partitions is associated with a corresponding partition identifier; receiving a host command to access data; identifying a compression ratio of the data; identifying a memory partition among the plurality of memory partitions; identifying a location among a plurality of locations on the memory partition by using a segment identifier and a unit offset address, wherein each of the plurality of locations is associated with a corresponding segment identifier, and wherein the unit offset address is determined in view of a compression ratio range associated with the memory partition; and performing an operation regarding the data at the identified location on the memory partition.
Inventor(s): Emanuele Confalonieri of Segrate (IT) for micron technology, inc., Antonino Caprí of Bergamo (IT) for micron technology, inc., Nicola Del Gatto of Cassina de’ Pecchi (IT) for micron technology, inc., Federica Cresci of Milan (IT) for micron technology, inc., Massimiliano Turconi of Gorgonzola (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: an apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. the plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent ras channels (e.g., channels for independent ras accesses). data received at the memory controller via different memory channels of one ras channel can be aligned at various circuits and/or components of the memory controller.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Tomer Tzvi Eliash of Sunnyvale CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of cells addressable by a first wordline of a first die of the memory device. the processing device identifies a programming order associated with the first wordline. the processing device adjusts, based on the programming order, a biasing scheme associated with the first wordline. the processing device further performs, using the programming order and biasing scheme, the programming operation on the first set of cells addressable by the first wordline.
Inventor(s): Bryan David Kerstetter of Kuna ID (US) for micron technology, inc., Donald M. Morgan of Meridian ID (US) for micron technology, inc., Alan J. Wilson of Boise ID (US) for micron technology, inc., John David Porter of Boise ID (US) for micron technology, inc., Jeffrey P. Wright of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. for example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. during the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. if the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. the controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.
Inventor(s): Douglas Eugene Majerus of Boise ID (US) for micron technology, inc., Cheng Long Ben of Shanghai (CN) for micron technology, inc., Qisong Lin of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: a memory device includes a boot block that stores boot block code encoded using an encoding scheme. the boot block code includes a set of machine-readable instructions for booting the memory sub-system. a read command directed at the boot block is received while the memory device is in a boot state. based on the command, the encoded boot block code is read from the boot block and decoded based on the encoding scheme. the decoded boot block code is provided to a memory sub-system controller responsive to the command
20250085887. INDUCTORS USING NAND LAYERS_simplified_abstract_(micron technology, inc.)
Inventor(s): Srivatsan Venkatesan of Gopanpalle (IN) for micron technology, inc., Kaveri Jain of Hyderabad (IN) for micron technology, inc., Salil Shashikant Mujumdar of Nanakaramguda (IN) for micron technology, inc., Rajat Vishnoi of Bangalore (IN) for micron technology, inc., Sushma Dogiparthi of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F3/06, G11C16/04
CPC Code(s): G06F3/0655
Abstract: an inductor is formed on an integrated circuit (ic) using one or more structures formed during or in coordination with 3d nand structure fabrication with one or more modifications. the inductor has a staircase structure, the staircase structure having a plurality of tiers that form steps on one side of the staircase structure. each tier comprises a conductive layer. the plurality of tiers includes at least a first tier and a second tier. the inductor has a first contact electrically coupling the first tier and the second tier. a first portion of a die is occupied by a memory sub-component comprising at least one three-dimensional (3d) nand memory component and a second portion of the die is occupied by the inductor.
20250085889. VARIABLE NAND MODE WITH SINGLE PLL SOURCE_simplified_abstract_(micron technology, inc.)
Inventor(s): Kang Seok Seo of Cupertino CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C16/04, G11C16/32
CPC Code(s): G06F3/0655
Abstract: aspects of the present disclosure configure a memory sub-system controller to select between different pll frequencies provided by the same pll to communicate with memory components. the controller configures clock generation circuitry to generate a first clock signal having a first frequency and receives a request to perform one or more hand-shaking operations with a set of memory components. the controller divides the first clock signal to generate a second clock signal having a second frequency that is smaller than the first frequency and communicates with the set of memory components using the second clock signal to perform the one or more hand-shaking operations.
Inventor(s): Alex Frolikov of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F13/16, G06F13/18
CPC Code(s): G06F3/0659
Abstract: a computer system having a host coupled to a storage device via a peripheral component interconnect express bus. the host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. in response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.
20250086055. REDUNDANT ARRAY MANAGEMENT TECHNIQUES_simplified_abstract_(micron technology, inc.)
Inventor(s): Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Deping He of Boise ID (US) for micron technology, inc., Xiangang Luo of Fremont CA (US) for micron technology, inc., Reshmi Basu of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for redundant array management techniques are described. a memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. the memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. the memory system may receive a write command associated with writing data to a type of memory cell. based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. in some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.
20250086056. SYNDROME DECODING SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc., Eyal En Gad of Highland CA (US) for micron technology, inc., Fan Zhou of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F7/501, G06F11/07, G11C29/44, G11C29/52, H03M13/11, H03M13/15, H03M13/29, H03M13/37, H03M13/45
CPC Code(s): G06F11/1068
Abstract: a method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. the method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
20250086058. READ CALIBRATION BY SECTOR OF MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Priya Venkataraman of Boise ID (US) for micron technology, inc., Pitamber Shukla of Boise ID (US) for micron technology, inc., Vipul Patel of Santa Clara CA (US) for micron technology, inc., Scott A. Stoller of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F3/06, G06F11/07, G06F12/0882, G11C16/34, G11C29/04, G11C29/44
CPC Code(s): G06F11/108
Abstract: read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. in response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. the page of memory can be read with the respective calibrated read level per sector. the calibrated read levels can be stored.
Inventor(s): Emanuele CONFALONIERI of Segrate (IT) for micron technology, inc., Marco SFORZIN of Cernusco sul Naviglio (IT) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07, H03M7/30
CPC Code(s): G06F11/1096
Abstract: provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks (lraid) including m (m>1) memory dice, the m memory dice stores stripes of data, and each stripe spanning over the m memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether memory dice required to store the compressed data in each stripe is n memory dice or less; where n is an integer less than m; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is n memory dice or less.
Inventor(s): Jun Wang of Shanghai (CN) for micron technology, inc., De Hua Guo of Shanghai (CN) for micron technology, inc., Jia Ling Pan of Shanghai (CN) for micron technology, inc., Kui Ding of Shanghai (CN) for micron technology, inc., Kun Liu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F11/14, G06F9/4401
CPC Code(s): G06F11/1417
Abstract: methods, systems, and devices for error information storage for boot-up procedures are described. a memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. in some cases, the memory system may additionally store the error information in a cache at the memory system. after storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. in cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.
20250086115. VALIDITY MAPPING TECHNIQUES_simplified_abstract_(micron technology, inc.)
Inventor(s): Xing Wang of Shanghai (CN) for micron technology, inc., Zhen Gu of Shanghai (CN) for micron technology, inc., Xu Zhang of Shanghai (CN) for micron technology, inc., Liping Xu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/0873
CPC Code(s): G06F12/0873
Abstract: methods, systems, and devices for validity mapping techniques are described. a memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. for example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). the memory device may set an entry of the change log based on whether the set of addresses are consecutive. for example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Lakshmi Kalpana K VAKATI of Fremont CA (US) for micron technology, inc., Dheeraj SRINIVASAN of San Jose CA (US) for micron technology, inc., Ting LUO of Santa Clara CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F21/57
CPC Code(s): G06F21/57
Abstract: in some implementations, a memory device may receive a single-level cell (slc) program command. the memory device may determine, based on at least one of a randomized variable associated with the memory or a program-erase cycle count associated with the memory, a program verify scheme to be performed when executing the slc program command. the program verify scheme may be one of a scheme associated with performing a program verify operation on all of the one or more subblocks of memory, a scheme associated with performing the program verify operation on a subblock associated with each odd word line (wl) to be programmed, or a scheme associated with performing the program verify operation on a subblock associated with each even wl to be programmed. the memory device may execute the slc program command by implementing the program verify scheme.
Inventor(s): James Ruane of San Jose CA (US) for micron technology, inc., Artsiom Zankovich of milpitas CA (US) for micron technology, inc.
IPC Code(s): G06F21/64, G06F21/54, G06F21/57
CPC Code(s): G06F21/64
Abstract: a processing device calculates a set of reference system measurements based on an initial firmware image corresponding to a memory device. the processing device stores the set of reference system measurements in a measurement attestation block of the memory device. a set of current system measurements are calculated by the processing device based on a current firmware image corresponding to the memory device. the processing device performs a comparison of the set of current system measurements with the set of reference system measurements stored in the measurement attestation block of the memory device and performs an action with respect to the memory device based on a result of the comparison.
20250086329. CRYPTOGRAPHIC KEY MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Juane Li of Milpitas CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Ying Yu Tai of Mountain View CA (US) for micron technology, inc.
IPC Code(s): G06F21/79, G06F21/60, G11C29/42, G11C29/44, H04L9/08
CPC Code(s): G06F21/79
Abstract: methods, systems, and devices for cryptographic key management are described. a memory device can issue, by a firmware component, a command to generate a first cryptographic key for encrypting or decrypting user data stored on a memory device. the memory device can generate, by a hardware component, the first cryptographic key based on the command. the memory device can encrypt, by the hardware component, the first cryptographic key using a second cryptographic key and an initialization vector. the memory device can store the encrypted first cryptographic key in a nonvolatile memory device separate from the hardware component.
20250086446. NEURON USING POSITS_simplified_abstract_(micron technology, inc.)
Inventor(s): Vijay S. Ramesh of Boise ID (US) for micron technology, inc., Richard C. Murphy of Boise ID (US) for micron technology, inc.
IPC Code(s): G06N3/065, G06F7/544, G06F7/57, G06F9/30, G06F9/50, G06N3/08, G11C11/34
CPC Code(s): G06N3/065
Abstract: systems, apparatuses, and methods related to a neuron using posits are described. an example apparatus may include a memory array including a plurality of memory cells configured to store data. the data can include a plurality of bit strings. the example apparatus may include a neuron component coupled to the memory array. the neuron component can include neuron circuitry configured to perform neuromorphic operations on at least one of the plurality of bit strings.
20250087249. INTERCONNECTIONS FOR 3D MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Toru Tanzawa of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C5/06, G11C5/02, G11C7/12, G11C7/22, G11C16/04, G11C16/06, G11C16/08, G11C16/10, G11C16/16, G11C16/26, H10B41/20, H10B41/35, H10B41/41
CPC Code(s): G11C5/063
Abstract: apparatuses and methods for interconnections for 3d memory are provided. one example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. the stack of materials has a stair step structure formed at one edge extending in a first direction. each stair step includes one of the pairs of materials. a first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.
Inventor(s): Si Hong Kim of Boise ID (US) for micron technology, inc., John D. Porter of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/22, G11C8/08
CPC Code(s): G11C7/1039
Abstract: systems and method for sensing an accessed voltage value associated with a memory cell is described. in different embodiments, a memory array may include a different number of sense components. moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. for example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.
Inventor(s): Kiyoshi Nakai of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/4076, G11C11/4093, H01L23/48, H03K19/20
CPC Code(s): G11C11/4096
Abstract: embodiments of the disclosure provide an apparatus comprising: a plurality of tsvs; a plurality of core dies stacked with one another; and an output control circuit. each core die includes a data output circuit coupled to one or more tsvs to output read data. the data output circuit includes a data splitter to provide first and second complementary read data in parallel based on the read data, an output data latch to latch the first and second read data, and an output data buffer to receive the first and second read data from the output data latch and drive the tsvs based on the first and second read data. the output control circuit provides a first reset signal to the output data buffer and a second reset signal to the data splitter or the output data buffer to disable the output of the read data to the tsvs.
Inventor(s): Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc.
IPC Code(s): G11C13/00, G11C16/04, H10B43/20
CPC Code(s): G11C13/0026
Abstract: methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. a memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. as part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.
Inventor(s): Shyam Sunder Raghunathan of Woodlands (SG) for micron technology, inc., Yingda Dong of Los Altos CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/04, G11C16/28
CPC Code(s): G11C16/16
Abstract: an apparatus can comprise a memory array comprising a plurality of strings of memory cells. a first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. a controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.
Inventor(s): Phiil Reusswig of Fremont CA (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/24, G11C16/34
CPC Code(s): G11C16/16
Abstract: aspects of the present disclosure configure a memory sub-system processor to manage memory erase operations. the processor accesses a configuration register to identify a quantity of memory slices to erase. the processor divides a set of memory components into a plurality of portions based on the identified quantity of memory slices to erase and performs one or more read operations in association with the memory sub-system between erasure of each of the plurality of portions of the set of memory components.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/16
CPC Code(s): G11C16/3418
Abstract: in some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. the memory device may determine that the portion of the memory is associated with a reliability risk. the memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an alternative erase scheme to erase the host data from the portion of the memory, wherein during a first portion of the alternative erase scheme, a first voltage is applied to even word lines and a second voltage, that is different from the first voltage, is applied to odd word lines, and wherein during a second portion of the alternative erase scheme, a third voltage is applied to the even word lines and a fourth voltage is applied to the odd word lines.
Inventor(s): Tingjun Xie of Milpitas CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Zhenlei Shen of Milpitas CA (US) for micron technology, inc., Charles See Yeung Kwong of Redwood City CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/10, G11C16/24, G11C16/26
CPC Code(s): G11C16/3418
Abstract: it is determined whether a write disturb capability associated with a first location of a memory device satisfies a threshold criterion. responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of memory units is remapped to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.
20250087283. ACCESS LINE VOLTAGE RAMP RATE ADJUSTMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., John Paul Aglubat of Meridian ID (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/12
CPC Code(s): G11C16/3459
Abstract: access line voltage ramp rate adjustment is described herein. an apparatus may include a memory device including a plurality of groups of memory cells and a processing device coupled to the memory device which may receive a program command to be executed on one of the plurality of groups of memory cells and determine if a program verify (pvfy) loop associated with the program command is below a threshold for a subblock of the memory device that includes the one of the plurality of groups. responsive to a determination that the pvfy loop is not below the threshold, the program command can be executed. responsive to a determination that the pvfy loop is below the threshold, an unselected access line voltage ramp rate for the subblock can be adjusted to a slower rate, and the program command can be executed using the adjusted unselected access line voltage ramp rate.
20250087289. SIGNAL DROP COMPENSATED MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Ferdinando Bedeschi of Biassono (IT) for micron technology, inc.
IPC Code(s): G11C29/42, G11C11/4091, G11C29/02, G11C29/44
CPC Code(s): G11C29/42
Abstract: apparatuses and methods for compensating for signal drop in memory. compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.
Inventor(s): Guang Hu of Mountain View CA (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/02, G11C29/04
CPC Code(s): G11C29/52
Abstract: a method includes identifying a read level offset assigned to a final bin in a scan order defined for a set of bins, identifying a set of bit error metric values by performing, using the read level offset, a scan operation with respect to a block of memory cells of the memory array, determining whether a final bit error metric value of the set of bit error metric values is greater than or equal to a threshold value, in response to determining that the final bit error metric value is greater than or equal to the threshold value, identifying a lowest bit error metric value of the set of bit error metric values, and selecting, from the set of bins, a bin having an assigned read level offset corresponding to the lowest bit error metric value.
20250087294. MEMORY REPAIRS_simplified_abstract_(micron technology, inc.)
Inventor(s): Sukneet S. Basuta of San Jose CA (US) for micron technology, inc., Kenneth M. Curewitz of Plymouth MA (US) for micron technology, inc.
IPC Code(s): G11C29/00
CPC Code(s): G11C29/702
Abstract: memory devices can be protected (e.g., repaired) against hard bit errors by remapping logical pages to valid physical addresses and excluding those physical addresses having hard bit errors from being mapped to. the remapping can be done in unit of a finer granularity than a row of memory cells such that those valid memory cells within a row can still be used for the remapping despite that the row may include unusable memory cells.
Inventor(s): Lingming Yang of Meridian ID (US) for micron technology, inc., Raghukiran Sreeramaneni of Frisco TX (US) for micron technology, inc., Nevil N. Gajera of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L21/66, H01L23/525, H01L25/065, H10B80/00
CPC Code(s): H01L22/32
Abstract: high-bandwidth memory (hbm) devices and associated systems and methods are disclosed herein. in some embodiments, the hbm devices include a first die (e.g., an interface die), a plurality of second dies (e.g., memory dies) carried by the first die communicably coupled to the first die through a plurality of hbm bus through substrate vias (tsvs). the hbm devices also include an hbm testing component carried at least partially by an upper surface of an uppermost second die. the hbm testing component provides access to the first and second dies through an uppermost surface of the hbm device to test the hbm device during manufacturing. for example, the hbm testing component allows the first and second dies to be tested after the hbm device is mounted to a base substrate of a system-in-package without requiring any footprint for access pins on the base substrate.
Inventor(s): Ko Han Lin of Taichung City (TW) for micron technology, inc., Tsung Che Tsai of Tainan City (TW) for micron technology, inc.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/14
Abstract: improved bump coplanarity for semiconductor device assemblies, and associated methods and systems are disclosed. in one embodiment, when openings in a passivation layer of a semiconductor device are formed to expose surfaces of bond pads, additional openings may also be formed in the passivation layer. the additional openings may have depths shallower than the openings extending to the surfaces of bond pads by leveraging partial exposures to the passivation layer using a leaky chrome process. subsequently, when active bumps (pillars) are formed on the exposed surfaces of bond pads, dummy bumps (pillars) may be formed on recessed surfaces of the additional openings such that differences in heights above the surface of the passivation between the active bumps and the dummy bumps are reduced to improve coplanarity.
20250088200. CONROL LOOP CIRCUITRY_simplified_abstract_(micron technology, inc.)
Inventor(s): Steven J. Baumgartner of Zumbro Falls MN (US) for micron technology, inc., Neeraj Savla of Inver Grove Heights MN (US) for micron technology, inc.
IPC Code(s): H03M1/78, H03F3/45
CPC Code(s): H03M1/785
Abstract: various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. an interface circuit can comprise a digital to analog converter (dac) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the dac; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the dac.
20250089233. NITRIDE LATTICE SUPPORT IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Yongjun J. Hu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/05
Abstract: systems, methods and apparatus are provided for nitride lattice support structures and double side capacitors in vertical three-dimensional (3d) memory. an example method includes a method for forming a nitride lattice support structures for an array of vertically stacked memory cells having access devices and storage nodes. the method includes depositing alternating layers of a channel material and a first sacrificial material in repeating iterations to form a vertical stack on a substrate. the vertical stack can be patterned to form a plurality of elongated vertical columns separated by a plurality of first vertical opening. a second sacrificial material can be deposited to fill the first vertical openings and cover the vertical stack. a plurality of vertical openings and lateral recesses can be formed. a nitride material can be deposited in the vertical openings and lateral recesses to form a plurality of nitride lattice support structures.
Inventor(s): Manuj Nahar of Boise ID (US) for micron technology, inc., Vassil N. Antonov of Boise ID (US) for micron technology, inc., Kamal M. Karda of Boise ID (US) for micron technology, inc., Michael Mutch of Meridian ID (US) for micron technology, inc., Hung-Wei Liu of Meridian ID (US) for micron technology, inc., Jeffery B. Hull of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/08, H01L21/02, H01L29/04, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H10D62/151
Abstract: a transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. the channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. other embodiments, including methods, are disclosed.
Micron Technology, Inc. patent applications on March 13th, 2025
- Micron Technology, Inc.
- G06F1/3234
- G06F1/08
- G06F1/3206
- G06F1/324
- G06F11/00
- G06F11/30
- G06F11/34
- CPC G06F1/3275
- Micron technology, inc.
- G06F3/06
- CPC G06F3/0608
- CPC G06F3/0611
- CPC G06F3/0619
- CPC G06F3/0632
- G11C16/04
- CPC G06F3/0655
- G11C16/32
- G06F13/16
- G06F13/18
- CPC G06F3/0659
- G06F11/10
- CPC G06F11/1068
- G06F7/501
- G06F11/07
- G11C29/44
- G11C29/52
- H03M13/11
- H03M13/15
- H03M13/29
- H03M13/37
- H03M13/45
- G06F12/0882
- G11C16/34
- G11C29/04
- CPC G06F11/108
- H03M7/30
- CPC G06F11/1096
- G06F11/14
- G06F9/4401
- CPC G06F11/1417
- G06F12/0873
- CPC G06F12/0873
- G06F21/57
- CPC G06F21/57
- G06F21/64
- G06F21/54
- CPC G06F21/64
- G06F21/79
- G06F21/60
- G11C29/42
- H04L9/08
- CPC G06F21/79
- G06N3/065
- G06F7/544
- G06F7/57
- G06F9/30
- G06F9/50
- G06N3/08
- G11C11/34
- CPC G06N3/065
- G11C5/06
- G11C5/02
- G11C7/12
- G11C7/22
- G11C16/06
- G11C16/08
- G11C16/10
- G11C16/16
- G11C16/26
- H10B41/20
- H10B41/35
- H10B41/41
- CPC G11C5/063
- G11C7/10
- G11C8/08
- CPC G11C7/1039
- G11C11/4096
- G11C11/4076
- G11C11/4093
- H01L23/48
- H03K19/20
- CPC G11C11/4096
- G11C13/00
- H10B43/20
- CPC G11C13/0026
- G11C16/28
- CPC G11C16/16
- G11C16/24
- CPC G11C16/3418
- G11C16/12
- CPC G11C16/3459
- G11C11/4091
- G11C29/02
- CPC G11C29/42
- CPC G11C29/52
- G11C29/00
- CPC G11C29/702
- H01L21/66
- H01L23/525
- H01L25/065
- H10B80/00
- CPC H01L22/32
- H01L23/00
- CPC H01L24/14
- H03M1/78
- H03F3/45
- CPC H03M1/785
- H10B12/00
- CPC H10B12/05
- H01L29/08
- H01L21/02
- H01L29/04
- H01L29/06
- H01L29/66
- H01L29/78
- CPC H10D62/151
