Micron Technology, Inc. patent applications on June 6th, 2024
Patent Applications by Micron Technology, Inc. on June 6th, 2024
Micron Technology, Inc.: 46 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (9), G11C16/10 (5), G11C16/34 (5), H01L23/00 (4), H01L33/48 (4) G06F3/0679 (7), G06F3/0655 (5), G11C16/3459 (4), G06F3/0659 (3), G11C16/26 (3)
With keywords such as: memory, device, data, portion, conductive, semiconductor, structure, include, material, and devices in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20240183522.SOLID STATE LIGHTS WITH COOLING STRUCTURES_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Sills of Boise ID (US) for micron technology, inc.
IPC Code(s): F21V29/67, F21V7/00, F21V7/05, F21V9/30, F21V13/04, F21V13/14, F21V29/507, F21V29/74, F21V29/80, F21V29/83, F21Y115/10, H01L33/48, H01L33/60
CPC Code(s):
Abstract: a solid state lighting (ssl) with a solid state emitter (sse) having thermally conductive projections extending into an air channel, and methods of making and using such ssls. the thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. the projections can be electrical contacts between the sse and a power source. the air channel can be oriented generally vertically such that air in the channel warmed by the sse flows upward through the channel.
Inventor(s): Perry V. Lea of Eagle ID (US) for micron technology, inc., Glen E. Hush of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C7/10, G11C7/22, G11C11/4076, G11C11/4091, G11C11/4093, G11C11/4094, G11C11/4096, G11C11/4097
CPC Code(s):
Abstract: the present disclosure includes apparatuses and methods for simultaneous in data path compute operations. an apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. a plurality of shared i/o lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. the first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.
20240184455.READ TRAINING FOR NON-VOLATILE MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Andrea Vigilante of Milano (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s):
Abstract: methods, systems, and devices for read training for non-volatile memory are described. in some examples, a memory system may perform read training by receiving a read command and reading a first subset of data. the memory system may apply one or more delays to each byte of the first subset of data and may select a delay for reading a second subset of data. upon selecting the delay, the memory system may read the second subset of data using the selected delay.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc., Saideep Tiku of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s):
Abstract: methods, systems, and devices for management of vehicle system information using a deep learning device are described. the deep learning device of a vehicle (such as a deep learning accelerator (dla)) may receive information associated with an environment of the vehicle from one or more sensors of the vehicle. the dla may perform one or more operations using one or more machine learning models. for example, the dla may compress the information which may reduce a resolution associated with the information, a frame rate associated with the information, or both. the dla may generate, as part of a run-time operation, a first set of analytics associated with operation of the vehicle using the compressed information. additionally, or alternatively, the dla may generate, as part of a post-processing operation, a second set of analytics using the compressed or an uncompressed version of the information.
Inventor(s): Angelo Alberto Rovelli of Agrate Brianza (IT) for micron technology, inc., Federica Cresci of Milan (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s):
Abstract: an access controller can be provided to regulate and secure access to an intermediate memory to which data stored in a one-time-programmable (otp) memory can be copied. to secure the access of the intermediate memory, the access controller can regulate a frequency at which the intermediate memory can be accessed and cryptographically manage (e.g., encrypt and/or decrypt) data being read from and/or written to the intermediate memory.
Inventor(s): David Aaron Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s):
Abstract: methods, systems, and devices for data type based write management techniques are described. a memory system may store (e.g., multiplex) different subsets of logical data types into the same data blocks and later separate the different types of logical data into respective data blocks. for example, the memory system may write each logical data type to a certain type of memory cell. the memory system may write different logical data types to the same type of memory cell and later separate them into the respective data blocks. for example, the memory system may write first data of a first logical data type and second data of a second logical data type to the same data block if both logical data types are associated with storage to the same type of memory cell and subsequently transfer the first data and second data to respective data blocks.
Inventor(s): Nikesh AGARWAL of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s):
Abstract: in a computer host system, a system and method to compress the transmission between the central processing unit (cpu) and the dynamic random access memory (dram) of either of an extended consecutive series of ‘0’ bits or an extended consecutive series of ‘1’ bits. the cpu or a compute express link (cxl) initiator associated with the cpu identifies the consecutive strings of ‘0’ bits or ‘1’ bits. the cpu or the cxl initiator sets data flags in a flit data structure, using just two bits or four bits to indicate the strings. the data structure is sent to a cxl memory, which interprets the flags and constructs the extended series of ‘0’ bits or extended series of ‘1’ bits.
Inventor(s): Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Ashutosh Malshe of Fremont CA (US) for micron technology, inc., Giuseppina Puzzilli of Boise ID (US) for micron technology, inc., Saeed Sharifi Tehrani of San Diego CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s):
Abstract: disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to receiving a read request to perform a read operation on a block of the memory device, incrementing a counter associated with the block to track a number of read operations performed on the block; setting a timer associated with the block to an initial value; determining that respective values of the counter and the timer are indicative of a minimum number of read operations performed on the block; and issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.
Inventor(s): Marco Onorato of Villasanta (MB) (IT) for micron technology, inc., Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc., Roberto Izzi of Caserta (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s):
Abstract: methods, systems, and devices for app launch detection from read chunk analysis are described. read commands may be received for accessing data stored in a memory system. the read commands may be used to determine a distribution of sizes for associated read data over an interval of time based, at least in part, on receiving the read commands. the memory system may detect the launch of an application based in part on the distribution of the sizes of the read data over the interval of time. upon detecting the launch of the application, a procedure may be performed to reduce a duration associated with launching the application.
20240184596.COMPRESSING FIRMWARE DATA_simplified_abstract_(micron technology, inc.)
Inventor(s): Jiawei Wang of Shanghai (CN) for micron technology, inc., Zephyr Yu of Shanghai (CN) for micron technology, inc., Yaming Lu of Shanghai (CN) for micron technology, inc., Long Lu of Shanghai (CN) for micron technology, inc., Huachen Li of Shanghai (CN) for micron technology, inc., Wenjun Wu of Shanghai (CN) for micron technology, inc., Chen Huang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F9/30
CPC Code(s):
Abstract: methods, systems, and devices for compressing firmware data are described. a memory system may access firmware data associated with the memory system that includes bank data. the memory system may determine whether the bank data in the firmware data is compressed and, in cases that the bank data is compressed, the memory system may decompress the bank data prior to storing the bank data at a controller of the memory system. in some examples, a bank header in the firmware data may include information for the memory system to decompress the bank data. for example, the bank header may indicate the size of the compressed bank data associated with each bank. additionally, the memory system may read the compressed bank data according to the indicated size and store the bank data at the controller or at a memory device of the memory system.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F16/23
CPC Code(s):
Abstract: a computing device having a computer express link (cxl) connection between a memory sub-system and a host system to write records of a database into a storage portion of the memory sub-system and store data identifying changes to the database into a memory portion of the memory sub-system. the records can be written to the storage portion using a storage access protocol of the cxl connection; and the change data can be stored to the memory portion using a cache coherent memory access protocol of the cxl connection. the change data can be written from the memory portion to a file in the storage portion.
Inventor(s): Byron Harris of Mead CO (US) for micron technology, inc., Daniel Boals of Broomfield CO (US) for micron technology, inc., Abedon Madril of Frederick CO (US) for micron technology, inc.
IPC Code(s): G06F12/0802, G06F3/06
CPC Code(s):
Abstract: a total count for an address mapping table is maintained, wherein the total count reflects a total number of updates to the address mapping table, and wherein the address mapping table comprises a plurality of sections. respective section counts for the plurality of sections are maintained, wherein each respective section count reflects a total number of updates to a corresponding section. it is determined that the total count for the address mapping table satisfies a threshold criterion. a first section of the plurality of sections with a highest section count is identified based on the respective section counts. the first section of the address mapping table is written to a non-volatile memory device.
Inventor(s): Raja V.S. Halaharivi of Gilroy CA (US) for micron technology, inc., Venkat R. Gaddam of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F12/10
CPC Code(s):
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to modify one or more regions of the memory device; identifying one or more mapping structures associated with each region of the one or more regions of the memory device; determining that a counter satisfies a threshold criterion, wherein the counter indicates a number of memory access commands at the one or more regions; creating a copy of each mapping structure associated with each region; and modifying the copy of each mapping structure according to the request to modify the one or more regions of the memory device.
Inventor(s): Gaurav SINHA of Oberschleißheim (DE) for micron technology, inc., Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G06F13/16
CPC Code(s):
Abstract: implementations described herein relate to a memory device that enables communication between multiple connected host devices. in some implementations, a memory device may receive, from a first host device in communication with the memory device, a send communication command instructing the memory device to transmit data from the first host device to at least a second host device in communication with the memory device. the memory device may receive, from the second host device, a receive communication command instructing the memory device to transmit data to the second host device from at least the first host device. the memory device may transmit a message from the first host device to the second host device based on the send communication command and the receive communication command.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F16/2455, G06F16/22
CPC Code(s):
Abstract: host system failover via a memory sub-system storing in-memory data for database operations. over a connection from a host interface of the memory sub-system, a first portion of the memory sub-system can be attached to a first host system as a memory device accessible via a first protocol; and a second portion of the memory sub-system can be attached to the first host system as a storage device accessible via a second protocol. a database manager running in the first host system can store the in-memory data in the memory device and store a persistent copy of database records in the storage device. when the first host system fails, the memory sub-system can be reconnected to a second host system to use the in-memory data for continued database operations.
Inventor(s): Alessandro ORLANDO of Milan (IT) for micron technology, inc., Danilo CARACCIO of Milan (IT) for micron technology, inc., Niccolò IZZO of Vignate (IT) for micron technology, inc.
IPC Code(s): G06F21/73, G06F21/60, G06F21/64
CPC Code(s):
Abstract: implementations described herein relate to an immutable certificate for a device identifier composition engine (dice). in some implementations, a device may include a secure computing environment. the secure component environment may include a hardware root of trust (hrot) dice component, a dice layer 0 (l0) component configured to derive a dice identity key, wherein the dice l0 component is above the hrot dice component in a layer stack, a dice layer 1 (l1) component configured to derive a dice alias key based on the dice identity key, wherein the dice l1 component is above the dice l0 component in the layer stack, wherein the dice l1 component and the dice l0 component are implemented as mutable code, and a controller. the controller may be configured to generate a set of certificates based on a compound device identifier (cdi).
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc., Saideep Tiku of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06N3/08
CPC Code(s):
Abstract: methods, systems, and devices for driving report generation using a deep learning device are described. in some cases, a vehicle may use sensor data and a deep learning device to provide a report to a driver of the vehicle. the vehicle may collect data from vehicle sensors and store a set of inputs received from the sensors in a volatile memory device. one or more processing units coupled with the memory system of the vehicle system may generate a model associated with the environment of the vehicle using the stored sensory inputs. the vehicle may identify events using the model, the sensory inputs or both. in some examples, the vehicle may employ a deep learning device to generate an event report using a machine learning model and the set of inputs.
Inventor(s): Yao Fu of Castro Valley CA (US) for micron technology, inc., Paul Glendenning of Woodside CA (US) for micron technology, inc., Tommy Tracy, II of Charlottesville VA (US) for micron technology, inc., Eric Jonas of San Francisco CA (US) for micron technology, inc.
IPC Code(s): G06N20/20, G06N5/01, G06N20/00
CPC Code(s):
Abstract: an apparatus includes a processing resource configured to receive a feature vector of a data stream. the feature vector includes a set of feature values. the processing resource is further configured to calculate a set of feature labels based at least in part on the set of feature values to generate a label vector, provide the label vector to another processing resource, and to receive a plurality of classifications corresponding to each feature label of the label vector from the other processing resource. the plurality of classifications are generated based at least in part on a respective range of feature values of the set of feature values. the processing resource is configured to then combine the plurality of classifications to generate a final classification of the data stream.
Inventor(s): Yutao Gong of Atlanta GA (US) for micron technology, inc., Dmitry Vengertsev of Boise ID (US) for micron technology, inc., Seth A. Eichmeyer of Boise ID (US) for micron technology, inc., Jing Gong of Boise ID (US) for micron technology, inc.
IPC Code(s): G06T7/00, G01N21/88, G01N21/95, G06V10/762, G06V10/764, G06V10/776, G06V10/82, H01L21/67
CPC Code(s):
Abstract: an inspection system for determining wafer defects in semiconductor fabrication may include an image capturing device to capture a wafer image and a classification convolutional neural network (cnn) to determine a classification from a plurality of classes for the captured image. each of the plurality of classes indicates a type of a defect in the wafer. the system may also include an encoder to encode to convert a training image into a feature vector; a cluster system to cluster the feature vector to generate soft labels for the training image; and a decoder to decode the feature vector into a re-generated image. the system may also include a classification system to determine a classification from the plurality of classes for the training image. the encoder and decoder may be formed from a cnn autoencoder. the classification cnn and the cnn autoencoder may each be a deep neural network.
20240185540.CONSTRUCTING AN AUGMENTED REALITY IMAGE_simplified_abstract_(micron technology, inc.)
Inventor(s): Zahra Hosseinimakarem of Boise ID (US) for micron technology, inc., Radhika Viswanathan of Boise ID (US) for micron technology, inc., Carla L. Christensen of Boise ID (US) for micron technology, inc., Bhumika Chhabra of Boise ID (US) for micron technology, inc.
IPC Code(s): G06T19/00, G01B11/06, G01B11/25
CPC Code(s):
Abstract: methods, devices, and systems related to a computing device for capturing an augmented reality (ar) image displaying an ar are described. an example method can include projecting a structured array of light, from a mobile device, onto an object. the method further includes measuring multi-directional sections of the object with the projected light. the method further includes reconstructing a three-dimensional (3d) figure of the object based on the measured multi-directional sections. the method further includes displaying an augmented reality (ar) image associated with the 3d figure on a user interface of the mobile device.
20240185892.MEMORY ARRAY DECODING AND INTERCONNECTS_simplified_abstract_(micron technology, inc.)
Inventor(s): Hernan A. Castro of Shingle Springs CA (US) for micron technology, inc., Stephen W. Russell of Boise ID (US) for micron technology, inc., Stephen H. Tang of Fremont CA (US) for micron technology, inc.
IPC Code(s): G11C5/06, G11C8/10, H01L23/50, H10B99/00
CPC Code(s):
Abstract: methods and apparatuses for thin film transistors and related fabrication techniques are described. the thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. the fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
Inventor(s): Ugo Russo of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C8/12, G11C11/56, G11C16/08, G11C19/32, H10B41/35, H10B43/27
CPC Code(s):
Abstract: some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. channel material pillars extend through the stack. some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. memory cells are along the channel material pillars. an insulative level is over the stack. a select gate configuration is over the insulative level. the select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. the first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. the first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. some embodiments include methods of forming assemblies.
20240185898.SYNDROME DECODING SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Eyal En Gad of Highland CA (US) for micron technology, inc., Leon Zlotnik of Camino CA (US) for micron technology, inc., Yoav Weinberg of Thornhill (CA) for micron technology, inc.
IPC Code(s): G11C7/10, G06F11/10
CPC Code(s):
Abstract: a method includes receiving, by shift circuitry, a bit string comprising a plurality of bits and determining, based on a shifting indicator, a quantity of bits by which the bit string is to be shifted within the shift circuitry. the method further includes generating a shifted bit string by performing, by the shift circuitry, an operation to shift the bit string by the quantity of bits indicated by the shifting indicator and performing, by decision circuitry coupled to the shift circuitry, an operation to alter one or more of the plurality of bits of the shifted bit string from a logical value of one to a logical value of zero or from a logical value of zero to a logical value of one.
20240185909.COMMAND CLOCK STRUCTURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Martin Brox of Munich (DE) for micron technology, inc., Thomas Hein of Munich (DE) for micron technology, inc., Filippo Vitale of Dachau (IT) for micron technology, inc.
IPC Code(s): G11C11/4076, G11C11/406, G11C11/4072
CPC Code(s):
Abstract: methods, systems, and devices for command clock structure are described. a memory device may receive a command to determine a relationship (e.g., a phase relationship) between an external clock and an internally generated clock. in some examples, the memory device may execute the command and may report (e.g., to a host device) whether the command is successfully or unsuccessfully executed. the memory device may report the successful or unsuccessful execution of the command by driving one or more pins to a first value or a second value.
Inventor(s): James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Patrick Robert Khayat of San Diego CA (US) for micron technology, inc., AbdelHakim S. Alhussien of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C11/56, G06F18/214, G06N20/00, G11C7/02, G11C29/12, G11C29/14, G11C29/38
CPC Code(s):
Abstract: a memory device to determine a voltage window to read soft bit data. for example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. the soft bit data identifies exclusive or (xor) of results read from the group of memory cells at the first voltage and at the second voltage respective. the memory device can provide a response to the read command based on the hard bit data and the soft bit data.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/26, G11C16/34
CPC Code(s):
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells associated with a wordline in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells associated with the wordline in the block using a first pass voltage applied during a program verify phase, wherein the first pass voltage is lower than a default program verify pass voltage.
20240185926.WRITING USER DATA INTO STORAGE MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Kishore Kumar Mucherla of San Jose CA (US) for micron technology, inc., William Charles Filipiak of Northville MI (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Andrew Bicksler of Nampa ID (US) for micron technology, inc., Ugo Russo of Boise ID (US) for micron technology, inc., Niccolo' Righetti of Boise ID (US) for micron technology, inc., Christian Caillat of Boise ID (US) for micron technology, inc., Akira Goda of Setagaya (JP) for micron technology, inc., Ting Luo of Santa Clara CA (US) for micron technology, inc., Antonino Pollio of Vico Equense (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/16, G11C16/34
CPC Code(s):
Abstract: a variety of applications can include one or more memory devices having user data preloaded for the application prior to reflowing the memory devices on the system platform of the application. a touch-up data refresh method can be implemented to gain read window budget and to improve retention slope to protect the preload content to tolerate reflow to the system platform. techniques for data preload can include programming preload data into targeted blocks until the targeted blocks are programmed with the preload data and re-programming the preload data over the programmed preload data in the targeted blocks in a same set of memory cells, without an erase between programming and re-programming the preload data. variations of such techniques can be used to prepare a memory device with preload data followed by performing a reflow of the memory device to a structure for an application to which the memory device is implemented.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Jun Wan of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10
CPC Code(s):
Abstract: a request to perform a program operation to program a set of memory cells on a memory device is received. a defect indicator associated with the set of memory cells is determined to satisfy a defect condition. a value of a program verify parameter is determined based on the defect indicator. the program operation is performed using the value of the program verify parameter during a program verify phase of the program operation.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/26, G11C29/02
CPC Code(s):
Abstract: a request to perform a program operation to program a set of memory cells on a memory device comprising a sense amplifier circuit is received. a defect indicator associated with the set of memory cells is determined to satisfy a defect condition. a modified sensing time period, exceeding a default sensing time period, is determined based on the defect indicator. the program operation is performed using the modified sensing time period during a program verify phase of the program operation.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/24, G11C16/26
CPC Code(s):
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells in the block using a first bitline voltage applied during a program verify phase, wherein the first bitline voltage is higher than a default program verify bitline voltage.
20240185938.GLITCH DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Niccolò Izzo of Vignate (IT) for micron technology, inc., David Hulton of Boise ID (US) for micron technology, inc., Tamara Schmitz of Columbia MO (US) for micron technology, inc., Angelo Alberto Rovelli of Agrate Brianza (IT) for micron technology, inc., Craig A. Jones of Plano TX (US) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc.
IPC Code(s): G11C29/08, G11C29/02
CPC Code(s):
Abstract: a method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. the method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. the method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.
Inventor(s): Rachael Skreen of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/38, G11C29/12
CPC Code(s):
Abstract: an apparatus is provided, comprising a controller, a plurality of memory devices operably connected to the controller, circuitry configured to measure a performance metric for each of the plurality of memory devices, and circuitry configured to select, based upon the measured performance metric, a subset of the plurality of memory devices to disable in response to a recovery command. information corresponding to the selected subset can be stored in a mode register of the apparatus, and the apparatus can further comprise circuitry configured, in response to a recovery command, to disable the subset of the plurality of memory devices.
Inventor(s): Sanh D. Tang of Boise ID (US) for micron technology, inc., Roger W. Lindsay of Boise ID (US) for micron technology, inc., Krishna K. Parat of Palo Alto CA (US) for micron technology, inc.
IPC Code(s): H01L23/52, G11C13/00, H01L23/528, H01L27/10, H10B41/27, H10B41/35, H10B43/27, H10B43/35, H10B63/00, H10N70/00
CPC Code(s):
Abstract: a method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. the features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. the lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. other aspects and implementations are disclosed.
Inventor(s): Shuangqiang Luo of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/522, H01L21/768, H10B69/00
CPC Code(s):
Abstract: microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. at least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.
20240186267.SEMICONDUCTOR DEVICES COMPRISING STEPS_simplified_abstract_(micron technology, inc.)
Inventor(s): Rohit Kothari of Boise ID (US) for micron technology, inc., Adam L. Olson of Boise ID (US) for micron technology, inc., John D. Hopkins of Meridian ID (US) for micron technology, inc., Jeslin J. Wu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/3105, H01L21/311, H01L21/762
CPC Code(s):
Abstract: a method of forming a semiconductor device comprising forming a patterned resist over a stack comprising at least one material and removing a portion of the stack exposed through the patterned resist to form a stack opening. a portion of the patterned resist is laterally removed to form a trimmed resist and an additional portion of the stack exposed through the trimmed resist is removed to form steps in sidewalls of the stack. a dielectric material is formed between the sidewalls of the stack to substantially completely fill the stack opening, and the dielectric material is planarized. additional methods are disclosed, as well as semiconductor devices.
Inventor(s): Amy Rae Griffin of Boise ID (US) for micron technology, inc., Brent Keeth of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Eiichi Nakano of Boise ID (US) for micron technology, inc., James Brian Johnson of Boise ID (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/29, H01L25/065, H10B80/00
CPC Code(s):
Abstract: methods, systems, and devices for thermal distribution techniques in coupled semiconductor systems are described. a semiconductor system may be formed by coupling various semiconductor components with one another, and may also implement a semiconductor material to support a thermal path having a thermal conductivity that is relatively close to a thermal conductivity through the coupled semiconductor components of the semiconductor system. such a semiconductor material may be located in regions of the semiconductor system that are otherwise unoccupied by functional (e.g., electrically operable) semiconductor components and may, in some examples, be electrically inoperable (e.g., may lack functional circuitry). for implementations in which functional semiconductor components are directly coupled (e.g., by fusion bonding or hybrid bonding techniques), the semiconductor material may also be directly coupled with at least one of the semiconductor components.
Inventor(s): Scott D. Schellhammer of Meridian ID (US) for micron technology, inc., Vladimir Odnoblyudov of Eagle ID (US) for micron technology, inc., Jeremy S. Frei of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/075, H01L21/18, H01L21/20, H01L21/447, H01L23/00, H01L23/495, H01L33/00, H01L33/48, H01L33/62
CPC Code(s):
Abstract: discontinuous bonds for semiconductor devices are disclosed herein. a device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. the second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.
Inventor(s): Vladimir Odnoblyudov of Eagle ID (US) for micron technology, inc., Martin F. Schubert of Mountain View CA (US) for micron technology, inc.
IPC Code(s): H01L33/20, H01L21/02, H01L33/00, H01L33/08, H01L33/12, H01L33/38, H01L33/48, H01L33/62
CPC Code(s):
Abstract: various embodiments of sst dies and solid state lighting (“ssl”) devices with sst dies, assemblies, and methods of manufacturing are described herein. in one embodiment, a sst die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. in some embodiments, the support structure has an opening that is vertically aligned with the active region.
Inventor(s): Jonathon G. Greenwood of Tampa FL (US) for micron technology, inc.
IPC Code(s): H01L33/50, H01L23/00, H01L25/16, H01L27/02, H01L33/48, H01L33/56, H01L33/58, H01L33/62
CPC Code(s):
Abstract: packaged leds with phosphor films, and associated systems and methods are disclosed. a system in accordance with a particular embodiment of the disclosure includes a support member having a support member bond site, an led carried by the support member and having an led bond site, and a wire bond electrically connected between the support member bond site and the led bond site. the system can further include a phosphor film carried by the led and the support member, the phosphor film being positioned to receive light from the led at a first wavelength and emit light at a second wavelength different than the first. the phosphor film can be positioned in direct contact with the wire bond at the led bond site.
20240187003.SYSTEMS HAVING A PHASE FREQUENCY DETECTOR_simplified_abstract_(micron technology, inc.)
Inventor(s): Junjun Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): H03L7/089, H03L7/099, H03L7/183
CPC Code(s):
Abstract: a variety of applications can include a phase frequency detector structured to track the falling edges of two input signals to detect a phase difference between the two signals and to generate one or more signals that can be used to adjust one of the signals with respect to the other when the phase difference is greater than 180 degrees. the phase frequency detector can be implemented in a phase lock loop circuit to track the falling edges of a reference clock signal and the falling edge of a feedback signal. in response to detection of the phase difference between the reference clock signal and the feedback signal being greater than 180 degrees using the falling edges of these signals, the phase frequency detector can adjust its output signals to provide for recovery of a lock condition for the reference clock signal. additional devices, systems, and methods are discussed.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C11/405, G11C11/4096
CPC Code(s):
Abstract: some embodiments include apparatuses and methods of using the apparatuses. one of the apparatuses includes first, second, and third conductive structures, each having a length in a first direction, first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction, first conductive regions, and second conductive regions. each of the first and second memory cells includes a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures, a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures. the first conductive regions are opposite the first and second semiconductor portions, respectively, of the first memory cell. second conductive regions are opposite the first and second semiconductor portions, respectively, of the second memory cell.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C11/405, G11C11/4096
CPC Code(s):
Abstract: some embodiments include apparatuses and methods of using the apparatuses. one of the apparatuses includes a first conductive structure, a second conductive structure, a conductive portion coupled to one of the conductive structures, and a memory cell. the memory cell includes different semiconductor portions located on different levels of the apparatus and separated from each other by a dielectric portion. the first semiconductor portion is coupled to the first and second conductive structures. the second semiconductor portion is coupled to the first conductive structure. the memory cell includes a charge storage structure coupled to the second semiconductor portion. the charge storage structure includes multiple portions. part of the conductive portion is located between portions of the charge storage structure and separated from the charge storage structure by a dielectric material.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s):
Abstract: systems, methods and apparatus are provided for a twin channel access device, twin storage node memory cell in a vertical three-dimensional memory. the memory cell has a horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. the first channel is actuated by a first gate separated from the first channel region by a first gate dielectric. the access device further includes a third source/drain region and a fourth source/drain region separated by a second channel region. the second channel is actuated by a second gate separated from the second channel region by a second gate dielectric. the first and the second gate are connected. a horizontally oriented storage node is coupled to the second and/or fourth source/drain regions of the twin channel access device.
Inventor(s): Christopher J. Larsen of Boise ID (US) for micron technology, inc., S M Istiaque Hossain of Boise ID (US) for micron technology, inc., David A. Daycock of Boise ID (US) for micron technology, inc., Kevin R. Gast of Boise ID (US) for micron technology, inc., George Matamis of Eagle ID (US) for micron technology, inc., Lingyu Kong of Singapore (SG) for micron technology, inc., Sok Han Wong of Singapore (SG) for micron technology, inc., Lhaang Chee Ooi of Singapore (SG) for micron technology, inc., Wenjie Li of Singapore (SG) for micron technology, inc.
IPC Code(s): H10B43/27, G11C16/04, H10B43/10, H10B43/35
CPC Code(s):
Abstract: methods, systems, and devices for three-dimensional memory array formation techniques are described. a memory device may include a stack of materials over a substrate. the memory device may include an array of first pillars and an array of second pillars extending at least partially through the stack of materials. one or more first pillars may be excluded from one or more columns of pillars of the array first pillars. the memory device may include dielectric material in a slit extending at least partially through the stack of materials. based on the exclusion of the one or more first pillars, the slit may have a greater width at a first portion through the stack of materials than a second portion through the stack of materials. the dielectric material located in the slit may also have a greater width at the first portion than at the second portion.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B51/20, H10B41/10, H10B41/20, H10B51/10
CPC Code(s):
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a conductive structure; a ferroelectric portion encircling the conductive structure; a charge storage structure encircling the ferroelectric portion; a dielectric portion encircling the charge storage structure; a semiconductor portion encircling the dielectric portion; a first additional conductive structure adjacent a first side of the semiconductor portion; and a second additional conductive structure adjacent a second side of the semiconductor portion, wherein a direction from the first additional conductive structure to the second additional conductive structure is perpendicular to a direction of a length of the conductive structure.
Inventor(s): Farrell M. Good of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B63/00
CPC Code(s):
Abstract: methods, systems, and devices for memory cell protective layers in a three-dimensional memory array are described. a memory device may support accessing memory cells of a memory array arranged in a three-dimensional architecture. the three-dimensional architecture may include levels of memory cells separated by levels of dielectric materials, such that the memory cells are formed between the dielectric materials. to prevent or reduce diffusion between a given memory cell and the dielectric materials, a barrier material may be formed on the dielectric material before forming the memory cell. the barrier material may be located between the memory cell and dielectric material, which may reduce or prevent material diffusion.
Micron Technology, Inc. patent applications on June 6th, 2024
- Micron Technology, Inc.
- F21V29/67
- F21V7/00
- F21V7/05
- F21V9/30
- F21V13/04
- F21V13/14
- F21V29/507
- F21V29/74
- F21V29/80
- F21V29/83
- F21Y115/10
- H01L33/48
- H01L33/60
- Micron technology, inc.
- G06F3/06
- G11C7/10
- G11C7/22
- G11C11/4076
- G11C11/4091
- G11C11/4093
- G11C11/4094
- G11C11/4096
- G11C11/4097
- G06F9/30
- G06F12/02
- G06F16/23
- G06F12/0802
- G06F12/10
- G06F13/16
- G06F16/2455
- G06F16/22
- G06F21/73
- G06F21/60
- G06F21/64
- G06N3/08
- G06N20/20
- G06N5/01
- G06N20/00
- G06T7/00
- G01N21/88
- G01N21/95
- G06V10/762
- G06V10/764
- G06V10/776
- G06V10/82
- H01L21/67
- G06T19/00
- G01B11/06
- G01B11/25
- G11C5/06
- G11C8/10
- H01L23/50
- H10B99/00
- G11C8/12
- G11C11/56
- G11C16/08
- G11C19/32
- H10B41/35
- H10B43/27
- G06F11/10
- G11C11/406
- G11C11/4072
- G06F18/214
- G11C7/02
- G11C29/12
- G11C29/14
- G11C29/38
- G11C16/10
- G11C16/04
- G11C16/26
- G11C16/34
- G11C16/16
- G11C29/02
- G11C16/24
- G11C29/08
- H01L23/52
- G11C13/00
- H01L23/528
- H01L27/10
- H10B41/27
- H10B43/35
- H10B63/00
- H10N70/00
- H01L23/522
- H01L21/768
- H10B69/00
- H01L23/00
- H01L21/3105
- H01L21/311
- H01L21/762
- H01L23/29
- H01L25/065
- H10B80/00
- H01L25/075
- H01L21/18
- H01L21/20
- H01L21/447
- H01L23/495
- H01L33/00
- H01L33/62
- H01L33/20
- H01L21/02
- H01L33/08
- H01L33/12
- H01L33/38
- H01L33/50
- H01L25/16
- H01L27/02
- H01L33/56
- H01L33/58
- H03L7/089
- H03L7/099
- H03L7/183
- H10B12/00
- G11C11/405
- H01L29/06
- H01L29/08
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/786
- H10B43/10
- H10B51/20
- H10B41/10
- H10B41/20
- H10B51/10
- G06F3/0679
- G06F3/0655
- G11C16/3459
- G06F3/0659
