Micron Technology, Inc. patent applications on June 20th, 2024
Patent Applications by Micron Technology, Inc. on June 20th, 2024
Micron Technology, Inc.: 49 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (14), G11C16/10 (8), G11C16/34 (6), G11C16/26 (4), H01L25/065 (3) G11C16/10 (4), G06F3/0608 (2), G01N29/4427 (1), G11C29/76 (1), G11C11/4091 (1)
With keywords such as: memory, device, material, based, data, circuit, cells, voltage, access, and substrate in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Ming Chen of Singapore (SG) for micron technology, inc.
IPC Code(s): G01N29/44, G07C3/00
CPC Code(s): G01N29/4427
Abstract: methods, systems, and devices for abnormal sound detection are described. an audio recording of a mechanized environment may be obtained. first sounds extracted from the audio recording may be categorized into a set of categorical sounds. a library of first sound patterns may be generated using the categorical sound and based on second sounds extracted from the audio recording. the first sound patterns may include sequences of the categorical sounds. audio data including audio signals capture by sensors in the mechanized environment may be received, and second sound patterns detected in the audio signals may be compared with the first sound patterns. based on comparing the second sound patterns with the first sounds patterns, a sound pattern that is not in the library of the first sound patterns may be identified. an alarm may be generated based on detecting the sound pattern a threshold quantity of times.
20240201252.EOP PROBING ON MULTI-DIE STACKS_simplified_abstract_(micron technology, inc.)
Inventor(s): John M. Gonzales of Boise ID (US) for micron technology, inc., Seth A. Eichmeyer of Boise ID (US) for micron technology, inc., Atsuko Otsuka of Hiroshima (JP) for micron technology, inc., Takeshi Kaku of Hiroshima (JP) for micron technology, inc., Soeparto Tandjoeng of Boise ID (US) for micron technology, inc.
IPC Code(s): G01R31/311
CPC Code(s): G01R31/311
Abstract: an example method can include focusing a light source onto a circuit of a first memory die of a plurality of memory dies. a light of the light source can reach the circuit of the memory die and can be reflected back toward a sensor. the method can further include receiving the reflection of light from the circuit at the sensor. the method can further include determining whether the circuit is transferring a particular signal based on the reflected light.
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Nicola Colella of Capodrise (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide media fragmentation management. the controller receives, from a host, a file-based-optimization (fbo) entry comprising a plurality of logical block addresses (lbas) associated with a file. the controller accesses a page table that associates the plurality of lbas with respective physical addresses of a set of memory components and determines a first quantity of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of lbas. the controller computes a regression level for the file based on the first quantity of read operations relative to a second quantity of lbas included in the plurality of lbas.
20240201851.OPEN BLOCK MANAGEMENT IN MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Michael Winterfeld of Firestone CO (US) for micron technology, inc., Juane Li of Milpitas CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: a method for tracking open blocks in a memory device includes partitioning, by a memory sub-system controller, a storage region in the memory device into a plurality of channels, each channel including a plurality of planesets, and each planeset comprising a plurality of blocksets. the method further includes distributing evenly between the plurality of channels a plurality of active zones ready for a write operation. each active zone includes one or more open blocks. the method further includes sending, by the memory sub-system controller, an open block message to a controller in the memory device, the open block message including channel identifying information, planeset identifying information, and blockset identifying information. the channel identifying information, the planeset identifying information, and the blockset identifying information collectively identify one or more open blocks ready for a write operation in the memory device.
Inventor(s): Wenjun Wu of Shanghai (CN) for micron technology, inc., Huachen Li of Shanghai (CN) for micron technology, inc., Xiaolai Zhu of Shanghai (CN) for micron technology, inc., Ling Shi of Shanghai (CN) for micron technology, inc., Qingyuan Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/1009
CPC Code(s): G06F3/0613
Abstract: methods, systems, and devices for address mappings for random access operations are described. a portion of a l2p table may be loaded (e.g., to a buffer) upon receiving a write command (e.g., a random write command). in some instances, one or more entries (e.g., one or more mappings) included in the portion of the l2p table may be updated based on the write command. the portion of the l2p table may be maintained in the buffer during subsequent access operations, such as random read operations. the subsequent access operations may utilize the portion of the l2p table to access a memory device.
Inventor(s): JEREMY CHRITZ of SEATTLE WA (US) for micron technology, inc., DAVID HULTON of SEATTLE WA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0877, H04L9/06
CPC Code(s): G06F3/0622
Abstract: examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. for example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. the error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.
Inventor(s): Kwang-Ho Cho of Boise ID (US) for micron technology, inc., Miki Matsumoto of Tokyo (JP) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: methods, systems, and devices for row address latching for multiple activate command protocol are described. a memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. the memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. the memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.
Inventor(s): Sourabh Dhir of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. a memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. the memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. the memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.
Inventor(s): Giuseppe CARIELLO of Boise ID (US) for micron technology, inc., Jonathan S. PARRY of Boise ID (US) for micron technology, inc., Reshmi BASU of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/065
Abstract: in some implementations, a memory device may receive a write command that includes data to be written to the memory device. the memory device may receive an indication that single-level cell data caching is deactivated for the data. the memory device may determine whether the data is associated with a first data type or a second data type. the memory device may selectively write the data to single-level cell cache memory or multi-level cell main memory based on a determination of whether the data is associated with the first data type or the second data type and a determination of whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data caching.
20240201891.INPUT VOLTAGE DEGRADATION DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Joseph A. Oberle of Sunnyvale CA (US) for micron technology, inc., David C. Sastry of El Dorado Hills CA (US) for micron technology, inc., Anil Kumar Agarwal of Boise ID (US) for micron technology, inc., Sumit Tayal of Brentwood CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: a method includes performing a host-initiated test memory operation of a memory device in a memory sub-system and detecting, via a sensor circuit, an input voltage or input current of the memory device or the memory sub-system. the method further includes determining whether the input voltage or the input current meets a degradation criteria and generating a management control signal responsive based on the determination whether the input voltage or the input current meets the degradation criteria.
20240201893.INPUT VOLTAGE DEGRADATION DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Sumit Tayal of Brentwood CA (US) for micron technology, inc., Joseph A. Oberle of Sunnyvale CA (US) for micron technology, inc., David C. Sastry of El Dorado Hills CA (US) for micron technology, inc., Anil Kumar Agarwal of () for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a method includes performing a self-initiated test memory operation of a memory device in a memory sub-system and detecting, via a sensor circuit, an input voltage or input current of the memory device or the memory sub-system. the method further includes determining whether the input voltage or the input current meets a degradation criteria and generating a management control signal responsive based on the determination whether the input voltage or the input current meets the degradation criteria.
Inventor(s): Dheeraj DAKE of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: in some implementations, a device may obtain a command table associated with a memory device, wherein the command table includes one or more entries associated with one or more respective commands, and wherein each entry, from the one or more entries, includes one or more units of data. the device may receive an indication of a modification associated with a first command, wherein the first command indicates a sequence of a first one or more units of data. the device may modify the command table based on the modification associated with the first command, wherein modifying the command table includes at least one of: adding an entry, that indicates the sequence, to the one or more entries to indicate the first command, or removing the entry from the one or more entries. the device may provide, to a controller of the memory device, an indication of the command table.
Inventor(s): Abhishek Chaurasia of Redmond WA (US) for micron technology, inc., Andre Xian Ming Chang of Bellevue WA (US) for micron technology, inc.
IPC Code(s): G06F8/34, G06F8/36
CPC Code(s): G06F8/34
Abstract: a system providing neural network model definition code generation and optimization is disclosed. the system receives inputs to facilitate the generation of an artificial intelligence model, such as freehand drawings of a model, modules available in repositories, various forms of content, and other inputs. the system utilizes a neural network to analyze the inputs and generates blocks and connections to generate a graph for the artificial intelligence model. properties of the model are selected, and the system locates modules, generates code for modules, or both, based on the blocks and connections from the graph and the properties. the system generates the model definition for the artificial intelligence model using the located modules and the generated code. once the model definition is completed, the artificial intelligence model may be utilized to perform a task for which the artificial intelligence model has been created to perform.
20240202026.VIRTUAL QUEUE_simplified_abstract_(micron technology, inc.)
Inventor(s): Bhumika Chhabra of Boise ID (US) for micron technology, inc., Zahra Hosseinimakarem of Boise ID (US) for micron technology, inc., Carla L. Christensen of Boise ID (US) for micron technology, inc., Radhika Viswanathan of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F9/48, G06F9/455, G06F9/54
CPC Code(s): G06F9/4881
Abstract: methods and non-transitory machine-readable media associated with a virtual queue are described. a method can include receiving, by a processing resource, a request from a user to join a virtual queue, adding, by the processing resource, the user to the virtual queue, determining, by the processing resource, a queue optimization based on an estimated wait time for the user in the virtual queue, and providing to the user, by the processing resource, the queue optimization including the estimated wait time for the user in the virtual queue. the virtual queue can be updated in an example.
Inventor(s): Horia C. SIMIONESCU of Foster City CA (US) for micron technology, inc., Paul Roger STONELAKE of Kihei HI (US) for micron technology, inc., Alex Ga Hing TANG of Cupertino CA (US) for micron technology, inc., Parag R. MAHARANA of Dublin CA (US) for micron technology, inc.
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5016
Abstract: in some implementations, a memory device may allocate first credit amounts for respective physical functions from a set of physical functions associated with the memory device, wherein the first credit amounts correspond to allocations for one or more performance metrics for the set of physical functions over a time window. the memory device may allocate second credit amounts for the respective physical functions from the set of physical functions, wherein the second credit amounts correspond to allocations for the one or more performance metrics for virtual windows included in the time window, and wherein the second credit amounts are based on the first credit amounts and an amount of time associated with the time window. the memory device may perform, during each virtual window included in the time window, one or more operations associated with the set of physical functions based on the second credit amounts.
Inventor(s): Andrea Giovanni Xotta of Cornedo Vicentino (IT) for micron technology, inc., Umberto Siciliani of Rubano (IT) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07, G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G06F11/1068
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations comprising receiving a write command comprising host data, determining an operating temperature value of the memory device, and programming, to the memory device, the host data and a value reflecting the operating temperature.
20240202073.READ RECOVERY_simplified_abstract_(micron technology, inc.)
Inventor(s): Prashant Parashari of Hyderabad (IN) for micron technology, inc., Gaurav Singh of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F11/10, H03M13/00, H03M13/11
CPC Code(s): G06F11/1076
Abstract: a sign bit of a low-density parity-check (ldpc) codeword associated with a translation unit (tu) can be generated by performing an xor operation on a rain drop corresponding to the tu and a raw read of the tu. the ldpc codeword can include a hard bit and three soft bits that include the sign bit. the ldpc codeword can be decoded using the hard bit and the three soft bits. a read recovery operation can be performed on the tu using the decoded ldpc codeword.
Inventor(s): Rainer Bonitz of Bruckmuehl (DE) for micron technology, inc., Aaron P. Boehm of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/023
Abstract: apparatuses, systems, and methods for a memory refresh watchdog circuit. a memory may include a temperature sensor which sets a value of a refresh multiplier in a mode register. the memory includes a refresh watchdog circuit which determines an expected rate of refresh commands based on a current value of the refresh multiplier. the refresh watchdog circuit measures a rate at which refresh commands are received from a memory controller and compares the measured rate to the expected rate. for example, the refresh watchdog circuit may set a threshold based on the value of the refresh multiplier. the refresh watchdog circuit may change a count value each time a refresh command is received and compare the count value to the threshold. if the count value is less than the threshold, then the refresh watchdog circuit may determine that not enough refresh commands have been received.
Inventor(s): Xiangyu Tang of San Jose CA (US) for micron technology, inc., David Ebsen of Minnetonka MN (US) for micron technology, inc., Ying Huang of Boise ID (US) for micron technology, inc., Sundararajan Sankaranarayanan of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F3/06
CPC Code(s): G06F12/0253
Abstract: a subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. a first block from the subset of blocks is selected based on a valid data count of the first block. a second block from the subset of blocks is selected based on a data temperature of the second block. a comparison of the first block and the second block is performed in accordance with one or more comparison criterion. the first block or the second block is selected as a garbage collection source block based on the comparison. garbage collection is performed at the garbage collection source block.
20240202119.MEMORY DEVICE WITH ON-DIE CACHE_simplified_abstract_(micron technology, inc.)
Inventor(s): Sean S. Eilert of Penryn CA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Shivam Swami of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F12/0802, G06F3/06
CPC Code(s): G06F12/0802
Abstract: an example memory sub-system includes: a plurality of bank groups, wherein each bank group comprises a plurality of memory banks; a plurality of row buffers, wherein two or more row buffers of the plurality of row buffers are associated with each memory bank; a cache comprising a plurality of cache lines; a processing logic communicatively coupled to the plurality of bank groups and the plurality of row buffers, the processing logic to perform operations comprising: receiving an activate command specifying a row of a memory bank of the plurality of memory banks; fetching data from the specified row to a row buffer of the plurality of row buffers; and copying the data to a cache line of the plurality of cache lines.
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/16, G06F13/42
CPC Code(s): G06F13/1684
Abstract: this disclosure describes aspects of memory die interconnections to physical layer interfaces (phys) that may enable expanded channel bus width and improved signal integrity (si). in aspects, a memory die is operably coupled to a first phy via a command-and-address (ca) bus and data input/output (dq) bus of the first phy and to a second phy via a chip select (cs) bus of the second phy. the second phy may provide a cs signal to the memory die, and the first phy can perform a training procedure via ca signaling or dq signaling. the training procedure may improve si between the memory die and the phys. additionally, a memory die may be interconnected to different phys to expand a channel bus width. thus, by interconnecting memory dies to one or more phys as described herein, improved si and expanded channel bus width can be achieved.
Inventor(s): Andre Xian Ming Chang of Bellevue WA (US) for micron technology, inc., Abhishek Chaurasia of Redmond WA (US) for micron technology, inc.
IPC Code(s): G06N3/04, G06F16/2453
CPC Code(s): G06N3/04
Abstract: a system providing intermediate module neural architecture search is disclosed. the system searches a dynamic search space for candidate modules for a model of a neural network. the system analyzes an existing model and determines an insertion point at which the candidate modules may be inserted. a zero-shot metric is applied to the candidate modules to generate a ranking of candidate modules that may substitute an existing module at the insertion point. the system trains the candidate modules over a plurality of epochs on a distribution of data of a dataset. based on the training, the system determines an accuracy rank for each of the candidate modules. the system executes candidate models including the candidate modules on a deep learning accelerator to determine a runtime execution rank for the candidate models. based on the accuracy and runtime execution ranks, the system determines an optimal proposed model from the candidate models.
Inventor(s): Sherif Amer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06N3/063
CPC Code(s): G06N3/063
Abstract: methods, systems, and devices for techniques for analysis of synapses for neuromorphic arrays are described. a neuromorphic system may be configured such that each neuron reads a single synaptic circuit at a time. the synaptic circuit may receive a voltage pulse. due to variability in individual synaptic circuits, various synaptic circuits may activate due to a voltage pulse while other synaptic circuits may not activate when exposed to a voltage pulse of the same property. information associated with activating the synaptic circuits may contribute to a statistical distribution of the synaptic elements, which may be used to model and characterize the neuromorphic system and allow for more accurate neuromorphic system programming.
Inventor(s): Pavana Prakash of Houston TX (US) for micron technology, inc., Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Febin Sunny of Folsom CA (US) for micron technology, inc., Saideep Tiku of Fort Collins CO (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06N3/08
CPC Code(s): G06N3/08
Abstract: training the ann can include providing an initial ann model to a plurality of groups of edge devices and providing an input to a group of edge devices from the plurality of groups of edge devices. training the ann can also include, responsive to providing the input, receiving activation signals from a first portion of the plurality of groups. training the ann can include providing the activation signals to a second portion of the plurality of groups and provide commands to the plurality of groups of edge devices to train the initial ann model to generate a trained ann model based on training feedback generated using different activation signals received from the second portion of the plurality of groups. training the ann can also include receiving the trained ann model from the plurality of groups of edge devices.
Inventor(s): Wenjun Li of Meridian ID (US) for micron technology, inc., Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/06, G11C7/08
CPC Code(s): G11C7/065
Abstract: systems and methods for fabricating various devices with various fin widths in a sense amplifier (sa) of a memory device is described. the various devices in the sa are sensitive to various parameters, which are sensitive to the fin widths of corresponding finfets. fabricating various fin widths in the various devices in the sa improves the performance of the memory device. for instance, using thicker fins (greater fin widths) for nmos sense amplifiers and pmos sense amplifiers in the sa reduces threshold voltage variations while using thinner fins (smaller fin widths) for control devices in the sa keeps high performance for the control devices.
Inventor(s): Mattia Boniardi of Cormano (IT) for micron technology, inc., Richard K. Dodge of Santa Clara CA (US) for micron technology, inc., Innocenzo Tortorelli of Cernusco Sul Naviglio (IT) for micron technology, inc., Mattia Robustelli of Milano (MI) (IT) for micron technology, inc., Mario Allegra of Monza (IT) for micron technology, inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1096
Abstract: methods, systems, and devices for adaptive write operations for a memory device are described. in an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. in some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. in some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).
20240203481.DECODING ARCHITECTURE FOR MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Paolo Fantini of Vimercate (IT) for micron technology, inc., Enrico Varesi of Milano (IT) for micron technology, inc., Lorenzo Fratin of Buccinasco (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C5/06, G11C11/4074
CPC Code(s): G11C11/4085
Abstract: methods, systems, and devices for a decoding architecture for memory devices are described. word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. two word line plates in a same plane may be activated via a shared electrode. memory cells coupled with the two word line plates sharing the electrode, or a subset thereof, may represent a logical page for accessing memory cells. a memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.
Inventor(s): Huy T. Vo of Boise ID (US) for micron technology, inc., Charles L. Ingalls of Meridian ID (US) for micron technology, inc., Shizhong Mei of Boise ID (US) for micron technology, inc., Luoqi Li of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/4074
CPC Code(s): G11C11/4091
Abstract: a memory device may include multiple memory cells configured to store data. the memory device may also include multiple digit lines that carry data to and from a respective memory cell. the memory device may include multiple sense amplifiers each selectively coupled to respective digit lines and including first and second transistors and first and second gut nodes coupled to the first and second transistors, respectively. each sense amplifier may amplify a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based on respective charges the digit lines, where a gain of the amplification is based on a negative voltage supplied to the sense amplifier and/or negative digit line write back operations.
20240203490.CURRENT REFERENCES FOR MEMORY CELLS_simplified_abstract_(micron technology, inc.)
Inventor(s): Ferdinando Bedeschi of Biassono (IT) for micron technology, inc., Pierguido Garofalo of San Donato (IT) for micron technology, inc., Umberto Di Vincenzo of San Gervasio (IT) for micron technology, inc., Claudia Palattella of Cologno Monzese (IT) for micron technology, inc.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/004
Abstract: a variety of applications can include one or more memory devices having one or more memory arrays of memory cells, where each memory cell is a resistive memory cell arranged such that a clamp current for the memory cell can be provided by an access line biasing circuit to the memory cell opposite a coupling of a sense circuit to a digit line to the memory array. the access line biasing circuit and the sense circuit can be operated in a digit line precharge phase and an access line biasing phase of a memory cell of the memory array using a set of switches to control activities for the memory cell in the memory array, the sense circuit, and the access line biasing circuit. a reference current can be provided from the access line biasing circuit to the sense circuit. additional devices, systems, and methods are discussed.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L21/28, H01L29/423, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): G11C16/0483
Abstract: a method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. two of the first tiers have different vertical thicknesses relative one another. channel-material strings of memory cells extend through the first tiers and the second tiers. through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. the first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. the first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. after the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. other embodiments, including structure independent of method, are disclosed.
Inventor(s): Walter Di Francesco of Avezzano (IT) for micron technology, inc., Violante Moschiano of Avezzano (IT) for micron technology, inc., Umberto Siciliani of Rubano (PD) (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G06F12/0802, G11C11/56, G11C16/04
CPC Code(s): G11C16/10
Abstract: control logic in a memory device initiates a programming operation to program a set of memory cells of the memory device to a target programming level of a set of programming levels. during execution of the programming operation, a programming status associated with the set of memory cells. in response to determining the programming status satisfies a condition, causing a release of a set of data associated with the programming operation from a cache register.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G11C16/10
Abstract: a request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. a bitline voltage adjustment value based on a number of program erase cycles (pecs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. a default bitline voltage is adjusted by the bitline voltage adjustment value to generate an adjusted bitline voltage. the program operation on the set of vertically stacked memory cells is performed using the adjusted bitline voltage.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Christina Papagianni of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G11C16/10
Abstract: a request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. a program verify level adjustment value based on a number of program erase cycles (pecs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. a default program verify level is adjusted by the program verify level adjustment value to generate an adjusted program verify level. the program operation on the set of vertically stacked memory cells is performed using the adjusted program verify level.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G11C16/10
Abstract: a request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. a sensing time adjustment value based on a number of program erase cycles (pecs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. a default sensing time is adjusted by the sensing time adjustment value to generate an adjusted sensing time. the program operation on the set of vertically stacked memory cells is performed using the adjusted sensing time.
Inventor(s): Tomer Tzvi Eliash of Sunnyvale CA (US) for micron technology, inc., Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhengang Chen of San Jose CA (US) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C29/52
CPC Code(s): G11C16/102
Abstract: a processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first wordline of a first die of the memory device. the processing device identifies, based on a first predefined value, a second wordline of a second die of the memory device, wherein the first predefined value is a shift in an index value of the first wordline of the first die of the memory device. the processing device further performs a second programming operation on a second set of cells associated with the second wordline of the second die, wherein the second wordline of the second die is associated with a different index value than the first wordline of the first die.
Inventor(s): Chulbum Kim of San Jose CA (US) for micron technology, inc., Brian Kwon of Fremont CA (US) for micron technology, inc., Erwin E. Yu of San Jose CA (US) for micron technology, inc., Kitae Park of Cupertino CA (US) for micron technology, inc., Taehyun Kim of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/14, G06F3/06, G11C16/04, G11C16/22, G11C16/32
CPC Code(s): G11C16/14
Abstract: a memory device includes a memory array comprising memory cells and control logic operatively coupled with the memory array. the control logic causes, as part of a true erase sub-operation, an erase pulse to be applied to one or more sub-blocks of the memory array. the control logic tracks a number of suspend commands received from a processing device, including suspend commands received while memory cells of the one or more sub-blocks are being erased. the control logic causes, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation. the control logic, in response to the number of suspend commands satisfying a threshold criterion, alerts the processing device to terminate sending suspend commands.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C29/02
CPC Code(s): G11C16/3459
Abstract: a request to perform a program operation on a set of vertically stacked memory cells of a memory device is received. a pass voltage adjustment value based on a number of program erase cycles (pecs) associated with the memory device is determined responsive to determining that at least one memory cell of the set of vertically stacked memory cells is non-programmable. a default pass voltage is adjusted by the pass voltage adjustment value to generate an adjusted pass voltage. the program operation on the set of vertically stacked memory cells is performed using the adjusted pass voltage.
Inventor(s): Aswin Thiruvengadam of Folsom CA (US) for micron technology, inc., Daniel L. Lowrance of El Dorado Hills CA (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/02, G06F3/06, G06F12/02, G06F16/18, G11C7/04, G11C7/10, G11C16/10, G11C16/32, G11C16/34, G11C29/44
CPC Code(s): G11C29/028
Abstract: the present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. an example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
Inventor(s): SUSUMU TAKAHASHI of Sagamihara (JP) for micron technology, inc., HIROKI FUJISAWA of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C29/00
CPC Code(s): G11C29/76
Abstract: an apparatus that includes a plurality of first memory mats each including a plurality of normal column sections each storing user data, and a second memory mat including a plurality of first redundant column sections each substituting a defective one of column sections included in the plurality of first memory mats and a plurality of first bcc column sections each storing an error correction code.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Shuangqiang Luo of Boise ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/535, H10B41/27, H10B43/27
CPC Code(s): H01L21/76895
Abstract: integrated circuitry comprises vertical conductive vias individually having a lower portion thereof that is directly against conductor material of islands. the islands comprise multiple different composition materials directly above the conductor material. apart from the conductive vias, the islands individually comprise at least one of (a), (b), or (c), where: (a): a top material that is of different composition from all material that is vertically between the top material and the conductor material; (b): the top material having its top surface in a vertical cross-section extending laterally-outward beyond two opposing laterally-outermost edges of a top surface of the material that is immediately directly below the top material; and (c): is of different composition from that of an upper portion of the conductor material and including a portion thereof that is elevationally coincident with the conductor material or that is directly against the conductor material. other embodiments, including methods, are disclosed.
20240203804.ENGINEERED SEMICONDUCTOR SUBSTRATE_simplified_abstract_(micron technology, inc.)
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc., Roger W. Lindsay of Boise ID (US) for micron technology, inc., Lisa M. Clampitt of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/13, B28D5/00, H01L21/18, H01L21/304, H01L23/14
CPC Code(s): H01L23/13
Abstract: a semiconductor device assembly is provided. the semiconductive device assembly includes a semiconductor die with a substrate having an engineered portion and a semiconductive portion. the engineered portion includes one or more of: a sintered material, a corrugated material, oriented strands of material compressed to form a solid structure, layers of material compressed to form a solid structure, or a material arranged to form one or more planar trusses. the semiconductive portion is adhered directly to the engineered portion. a layer of dielectric material is disposed at the semiconductive portion, and circuitry is disposed at the layer of dielectric material. in doing so, a cost-efficient and mechanically robust semiconductor device may be assembled.
Inventor(s): Xiaopeng Qu of Boise ID (US) for micron technology, inc., Hyunsuk Chun of Boise ID (US) for micron technology, inc., Eiichi Nakano of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/473, H01L21/48, H01L23/367, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L23/4735
Abstract: semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. the semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. the microchannel can be configured beneath the memory device and/or the logic device.
Inventor(s): Seng Kim YE of Singapore (SG) for micron technology, inc., Kelvin Aik Boo TAN of Singapore (SG) for micron technology, inc., Hong Wan NG of Singapore (SG) for micron technology, inc., Chin Hui CHONG of Singapore (SG) for micron technology, inc., Ling PAN of Singapore (SG) for micron technology, inc., See Hiong LEOW of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/495, H01L21/56, H01L23/31, H01L25/065
CPC Code(s): H01L23/49565
Abstract: implementations described herein relate to various semiconductor device assemblies. in some implementations, a semiconductor device assembly includes a circuit substrate comprising a first substrate surface, a second substrate surface arranged opposite to the first substrate surface, and a substrate edge that extends from the first substrate surface to the second substrate surface; a series of holes arranged along the substrate edge of the circuit substrate, wherein each hole of the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die arranged on the first substrate surface; and a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and the first substrate surface, and wherein the package casing fills each hole of the series of holes.
Inventor(s): Hong Wan Ng of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc., Hem P. Takiar of Fremont CA (US) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/16, H01L21/56, H01L23/31, H01L25/00, H01L25/065
CPC Code(s): H01L25/16
Abstract: semiconductor devices and associated systems and methods are disclosed herein. in some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. a controller die with a first longitudinal footprint can be attached to the front side of the package substrate. a passive electrical component is also attached to the front side of the package substrate. a stack of semiconductor dies can be attached to the controller die and the passive electrical component. the stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. the controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): H04W12/069, H04L9/32, H04W12/08, H04W84/04
CPC Code(s): H04W12/069
Abstract: the disclosed embodiments relate to authenticating devices to a cellular network. in one embodiment, a method is disclosed comprising reading a mobile identifier from a storage area of a memory device, the mobile identifier comprising a value associated with a subscriber of a cellular network; signing the mobile identifier using a private key to generate a digital signature, the private key generated using a physically unclonable function (puf); transmitting the digital signature and a public key to a cellular network, the public key associated with the private key; and receiving, from the cellular network, a confirmation of access to the cellular network, the confirmation generated based on the public key and the digital signature.
Inventor(s): Bradley Russell BITZ of Meridian ID (US) for micron technology, inc., David R. CHRISTIANSON of Meridian ID (US) for micron technology, inc., Travis Michael JENSEN of Boise ID (US) for micron technology, inc., Kimball Davis LOWRY of Boise ID (US) for micron technology, inc., Joao Elmiro CHAVES of Middleton ID (US) for micron technology, inc.
IPC Code(s): H05K1/14, H05K1/02
CPC Code(s): H05K1/144
Abstract: an electronic system assembly includes a first circuit substrate having a surface, wherein the surface has a two-dimensional area defined in a first dimension and a second dimension; a plurality of first semiconductor chip packages mounted on and electrically coupled to the surface; a plurality of second circuit substrates positioned over the surface, wherein each first semiconductor chip package is arranged between the surface and a respective second circuit substrate in a third dimension; a plurality of conductive interconnect structures that extend in the third dimension, wherein the plurality of conductive interconnect structures are provided in a plurality of interconnect groups, and wherein each interconnect group connects a different second circuit substrate to the first circuit substrate; and a plurality of second semiconductor chip packages, wherein each second semiconductor chip package is mounted and electrically coupled to a respective second circuit substrate.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H10B12/31
Abstract: systems, methods and apparatus are provided for a hybrid gate dielectric access device for vertical three-dimensional (3d) memory. the memory cell has a first horizontally oriented access device having a first source/drain region and a second source/drain region separated by a first channel region. the first access device is operatively controlled by a first gate. a hybrid gate dielectric separates the gate from the channel region and a horizontally oriented storage node coupled to the second source/drain region of the access device.
Inventor(s): Sidhartha Gupta of Boise ID (US) for micron technology, inc., Adam W. Saxler of Boise ID (US) for micron technology, inc., Andrew Li of Boise ID (US) for micron technology, inc., John D. Hopkins of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: a method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier. the first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. the stack comprises horizontally-elongated trenches extending through the first tiers and the second tiers and are individually between immediately-laterally-adjacent memory-block regions. channel-material strings are formed that extend through the first and second tiers in the memory-block regions. through the horizontally-elongated trenches, the sacrificial material is replaced with conductive material that comprises control-gate lines in the memory-block regions. after the replacing, conducting material is formed in a lowest of the first tiers and directly electrically couples together the channel material of the channel-material strings and conductor material of the conductor tier. other embodiments, including structure, are disclosed.
Inventor(s): Marcello Mariani of Milano (IT) for micron technology, inc., Giorgio Servalli of Fara Gera D'Adda (IT) for micron technology, inc.
IPC Code(s): H10B53/30
CPC Code(s): H10B53/30
Abstract: a method used in forming an array of capacitors comprises forming first walls along a column direction and second walls along a row direction. the first and second walls individually comprise a first material directly above a second material. the first and second materials are of different compositions relative one another. all of the second material is removed from being directly under the first material in the second walls to form beams that are elongated along the row direction and are suspended between immediately-adjacent of the first walls and to leave the second material directly under the first material in the first walls. third walls are formed along the row direction. the third walls comprise third material that is of different composition from those of the first and second materials. the third material of individual of the third walls circumferentially-covers the beams. conductive material is grown over the first and second materials selectively relative to the third material. the selectively-grown conductive material is vertically-along sidewalls of the first walls and comprising first capacitor electrodes. the third walls are removed after the selectively growing. after removing the third walls, a capacitor insulator is formed over the first capacitor electrodes and that circumferentially-covers the beams. second capacitor electrodes are formed over the capacitor insulator to form a plurality of capacitors that individually comprise one of the first capacitor electrodes, the capacitor insulator, and one of the second capacitor electrodes. the second capacitor electrodes are common to multiple of the capacitors. other embodiments, including structure, are disclosed.
Micron Technology, Inc. patent applications on June 20th, 2024
- Micron Technology, Inc.
- G01N29/44
- G07C3/00
- CPC G01N29/4427
- Micron technology, inc.
- G01R31/311
- CPC G01R31/311
- G06F3/06
- CPC G06F3/0608
- G06F12/1009
- CPC G06F3/0613
- G06F12/0877
- H04L9/06
- CPC G06F3/0622
- CPC G06F3/0625
- CPC G06F3/0647
- CPC G06F3/065
- CPC G06F3/0653
- CPC G06F3/0655
- CPC G06F3/0659
- G06F8/34
- G06F8/36
- CPC G06F8/34
- G06F9/48
- G06F9/455
- G06F9/54
- CPC G06F9/4881
- G06F9/50
- CPC G06F9/5016
- G06F11/10
- G06F11/07
- G11C16/10
- G11C16/26
- G11C16/34
- CPC G06F11/1068
- H03M13/00
- H03M13/11
- CPC G06F11/1076
- G06F12/02
- CPC G06F12/023
- CPC G06F12/0253
- G06F12/0802
- CPC G06F12/0802
- G06F13/16
- G06F13/42
- CPC G06F13/1684
- G06N3/04
- G06F16/2453
- CPC G06N3/04
- G06N3/063
- CPC G06N3/063
- G06N3/08
- CPC G06N3/08
- G11C7/06
- G11C7/08
- CPC G11C7/065
- G11C7/10
- CPC G11C7/1096
- G11C11/408
- G11C5/06
- G11C11/4074
- CPC G11C11/4085
- G11C11/4091
- CPC G11C11/4091
- G11C13/00
- CPC G11C13/004
- G11C16/04
- H01L21/28
- H01L29/423
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- CPC G11C16/0483
- G11C11/56
- CPC G11C16/10
- G11C16/08
- G11C29/52
- CPC G11C16/102
- G11C16/14
- G11C16/22
- G11C16/32
- CPC G11C16/14
- G11C29/02
- CPC G11C16/3459
- G06F16/18
- G11C7/04
- G11C29/44
- CPC G11C29/028
- G11C29/00
- CPC G11C29/76
- H01L21/768
- H01L23/535
- CPC H01L21/76895
- H01L23/13
- B28D5/00
- H01L21/18
- H01L21/304
- H01L23/14
- CPC H01L23/13
- H01L23/473
- H01L21/48
- H01L23/367
- H01L25/00
- H01L25/065
- H01L25/18
- CPC H01L23/4735
- H01L23/495
- H01L21/56
- H01L23/31
- CPC H01L23/49565
- H01L25/16
- CPC H01L25/16
- H04W12/069
- H04L9/32
- H04W12/08
- H04W84/04
- CPC H04W12/069
- H05K1/14
- H05K1/02
- CPC H05K1/144
- H10B12/00
- H01L29/06
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H10B12/31
- CPC H10B43/27
- H10B53/30
- CPC H10B53/30
