Micron Technology, Inc. patent applications on June 13th, 2024
Patent Applications by Micron Technology, Inc. on June 13th, 2024
Micron Technology, Inc.: 40 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (13), G11C29/52 (3), H01L25/18 (3), H10B80/00 (3), G11C16/04 (3) G06F3/0659 (6), G06F3/064 (4), G06F12/1009 (2), G06F3/0619 (1), G11C29/08 (1)
With keywords such as: memory, device, cells, data, material, include, devices, based, dielectric, and commands in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Hyun Yoo Lee of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: described apparatuses and methods provide automated error correction with memory refresh. memory devices can include error correction code (ecc) technology to detect or correct one or more bit-errors in data. dynamic random-access memory (dram), including low-power double data rate (lppdr) synchronous dram (sdram), performs refresh operations to maintain data stored in a memory array. a refresh operation can be a self-refresh operation or an auto-refresh operation. described implementations can combine ecc technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. in an example, data for a read operation is checked for errors. if an error is detected, a corresponding address can be stored. responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. alternatively, data being refreshed can be checked for an error.
Inventor(s): Yun Li of Fremont CA (US) for micron technology, inc., James P. Crowley of Longmont CO (US) for micron technology, inc., Jiangang Wu of Milpitas CA (US) for micron technology, inc., Peng XU of Milpitas CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0631
Abstract: methods, systems, and devices for performance control for a memory sub-system are described. a memory sub-system can monitor a backend for writing data to a memory device. the memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. in some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.
Inventor(s): Hiroshi Akamatsu of Atlanta GA (US) for micron technology, inc., Reuben Pradhan of Atlanta GA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: apparatuses and methods for shared row and column address buses. row and column addresses are distributed along separate respective global buses in a central logic region of a memory. the row and column addresses are coupled through a shared address bus from the central logic region to a bank logic region. for example the row address may be provided along the shared address bus at a first time and the column address may be provided along the shared address bus at a second time.
Inventor(s): Yang Liu of San Jose CA (US) for micron technology, inc., Wenyen Chang of San Jose CA (US) for micron technology, inc., Wei Wang of Dublin CA (US) for micron technology, inc., Aaron Lee of Sunnyvale CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a system includes a memory device having a plurality of memory planes and a processing device operatively coupled with the memory device. the processing device to is perform operations including identifying a first block stripe of the memory device. the first block stripe includes a first plurality of blocks arranged across the plurality of memory planes. the operations further include determining that the first plurality of blocks of the first block stripe has greater than a threshold number of blocks associated with an error condition. responsive to determining that the first plurality of blocks has greater than the threshold number of blocks associated with the error condition, the operations further include mapping a block of the first plurality of blocks associated with the error condition to a second block stripe including a second plurality of blocks having fewer than the threshold number of blocks associated with the error condition.
20240192878.MEDIA MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Ashutosh Malshe of Fremont CA (US) for micron technology, inc., Antonio D. Bianco of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/064
Abstract: a method includes determining a health characteristic value of a block of memory cells, determining a difference between the health characteristic value and a health threshold, determining, based on the difference, a weight to associate with a block of memory cells, selecting, based on the weight, a block of memory cells for a media management operation; and performing a media management operation on the selected block of memory cells.
Inventor(s): Tomer Eliash of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superblock management based on memory component reliabilities.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc., Joseph Harold Steinmetz of Loomis CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: an apparatus with a solid state drive (ssd) having firmware to manage spare storage resources for proof of space activities. the ssd has a host interface configured to receive at least read commands and write commands from an external host system. the ssd has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. the firmware is executable in the ssd to allocate storage resources not used or allocated by the host system to support proof of space activities and dynamically return the allocated storage resources when execution of a command from the host system needs additional storage resources.
Inventor(s): Xiang Bai of Shanghai (CN) for micron technology, inc., Lingyun Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for techniques for efficiently handling misaligned sequential reads are described. a memory system may include a memory device that includes multiple memory dies. the memory system may receive a first read command and a second read command from a host system. the first read command may be associated with a first set of physical addresses and the second read command may be associated with a second set of physical addresses. the memory system may determine, based on the first set of physical addresses and the second set of physical addresses, that the first read command and the second read command are for a same memory die of the multiple memory dies. the memory system may then transmit to the memory die a read request that indicates the first set of physical addresses and the second set of physical addresses.
20240192888.LOW-LATENCY PROCESSING FOR UNMAP COMMANDS_simplified_abstract_(micron technology, inc.)
Inventor(s): Na Zhu of Shanghai (CN) for micron technology, inc., Ling Shi of Shanghai (CN) for micron technology, inc., Bo Sun of Shanghai (CN) for micron technology, inc., Huachen Li of Shanghai (CN) for micron technology, inc., Qingyuan Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for low-latency processing for unmap commands are described. a plurality of commands including one or more unmap commands and one or more other types of commands may be received from a device. the one or more unmap commands may be stored in a queue used for unmap commands and the other commands may be stored in another queue. ready-to-transfer messages for the one or more unmap commands stored in the queue may be transmitted to the device. in response to the ready-to-transfer messages, one or more messages including data for executing the one or more unmap commands may be received and stored in a portion of a buffer used for unmap commands.
Inventor(s): Jameer Mulani of Bangalore (IN) for micron technology, inc., Amiya Banerjee of Bangalore (IN) for micron technology, inc., Nitul Gohain of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for data layout configurations for access operations are described. the memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. the first set of memory cells may be written to as single-level cells (slcs), multi-level cells (mlcs), or triple-level cells (tlcs). the memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. the second set of memory cells may be written to as quad-level cells (qlcs). the memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.
20240192891.MEMORY DEVICE ACTIVE COMMAND TRACKING_simplified_abstract_(micron technology, inc.)
Inventor(s): Horia C. SIMIONESCU of Foster City CA (US) for micron technology, inc., Raja V.S. HALAHARIVI of Gilroy CA (US) for micron technology, inc., Prateek SHARMA of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: in some implementations, a memory device may obtain, from a host device, a first one or more commands associated with a first identifier. the memory device may maintain a first counter associated with tracking active commands from the host device. the memory device may detect an event, associated with a command, at a first time. the memory device may switch, based on detecting the event, an active identifier for commands obtained after the first time to a second identifier. the memory device may initiate a second counter associated with tracking active commands that were obtained prior to the first time. the memory device may perform an action associated with a command that is associated with the first identifier. the memory device may update, based on performing the action, the first counter and the second counter based on the at least one command being associated with the first identifier.
Inventor(s): Patrick Estep of Rowlett TX (US) for micron technology, inc., Sean S. Eilert of Penryn CA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: systems, apparatuses, and methods related to data reconstruction based on queue depth comparison are described. to avoid accessing the “congested” channel, a read command to access the “congested” channel can be executed by accessing the other relatively “idle” channels and utilize data read from the “idle” channels to reconstruct data corresponding to the read command.
Inventor(s): Bharani Rajendiran of Pleasanton CA (US) for micron technology, inc., Jason Duong of San Jose CA (US) for micron technology, inc., Chih-Kuo Kao of Fremont CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C11/408, G11C11/4094
CPC Code(s): G06F3/0659
Abstract: a memory access command is received. the memory access command is converted into a plurality of commands, wherein a number of commands comprised by the plurality of commands is equal to a number of partitions associated with a die of the memory device. a respective partition number and a respective page address are determined for each command of the plurality of commands. the plurality of commands is executed using, for each command of the plurality of commands, the respective partition number and the respective page address.
Inventor(s): Dmitri Yudanov of Cordova CA (US) for micron technology, inc., Sean S. Eilert of Penryn CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Shivasankar Gunasekaran of Folsom CA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc.
IPC Code(s): G06F9/30, G06F7/544
CPC Code(s): G06F9/3001
Abstract: methods, apparatuses, and systems for in-or near-memory processing are described. strings of bits (e.g., vectors) may be fetched and processed in logic of a memory device without involving a separate processing unit. operations (e.g., arithmetic operations) may be performed on numbers stored in a bit-parallel way during a single sequence of clock cycles. arithmetic may thus be performed in a single pass as numbers are bits of two or more strings of bits are fetched and without intermediate storage of the numbers. vectors may be fetched (e.g., identified, transmitted, received) from one or more bit lines. registers of a memory array may be used to write (e.g., store or temporarily store) results or ancillary bits (e.g., carry bits or carry flags) that facilitate arithmetic operations. circuitry near, adjacent, or under the memory array may employ xor or and (or other) logic to fetch, organize, or operate on the data.
Inventor(s): Douglas Vanesko of Dallas TX (US) for micron technology, inc., Bryan Hornung of Plano TX (US) for micron technology, inc., Patrick Estep of Rowlett TX (US) for micron technology, inc.
IPC Code(s): G06F9/30, G06F15/78, G06F15/82
CPC Code(s): G06F9/30065
Abstract: various examples are directed to systems and methods for executing a loop in a reconfigurable compute fabric. a first flow controller may initiate a first thread at a first synchronous flow to execute a first portion of a first iteration of the loop. a second flow controller may receive a first asynchronous message instructing the second flow controller to initiate a first thread at a second synchronous flow to execute a second portion of the first iteration. the second flow controller may determine that the first iteration of the loop is the last iteration of the loop to be executed and initiate the first thread at the second synchronous flow with a last iteration flag set.
Inventor(s): Jun Wang of Shanghai (CN) for micron technology, inc., De Hua Guo of Shanghai (CN) for micron technology, inc., Jia Ling Pan of Shanghai (CN) for micron technology, inc., Kui Ding of Shanghai (CN) for micron technology, inc., Kun Liu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F11/14, G06F9/4401
CPC Code(s): G06F11/1417
Abstract: methods, systems, and devices for error information storage for boot-up procedures are described. a memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. in some cases, the memory system may additionally store the error information in a cache at the memory system. after storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. in cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/0815
CPC Code(s): G06F12/0815
Abstract: a memory sub-system having a paging system to provide memory services over a connection from its host interface to a host system. the connection can support both a storage access protocol and a cache coherent memory access protocol. the memory sub-system can have a non-volatile memory to provide a storage capacity and a fast, volatile memory to cache active pages of a memory space provided by a memory device attached by the memory sub-system over the connection to the host system. the memory space can be configured in a namespace of the storage capacity of the non-volatile memory. optionally, the memory space can be configured for access both via the storage access protocol using logical block addresses and via the cache coherent memory access protocol using memory addresses.
Inventor(s): Liping Xu of Shanghai (CN) for micron technology, inc., Zhen Gu of Shanghai (CN) for micron technology, inc., Qingyuan Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/1009, G06F12/1045
CPC Code(s): G06F12/1009
Abstract: methods, systems, and devices for a sorted change log for physical page table compression are described. a mapping between a logical address and a physical address may be stored in a change log buffer. the mapping may be stored at a location of the change log buffer based on the logical address of the mapping relative to logical addresses of other mappings stored in the change log buffer. based on storing mappings in the change log buffer based on logical addresses of the mappings, a set of mappings in the change log may include a set of sequentially-indexed logical addresses. a compressed entry for a logical-to-physical table may be generated based on the set of mappings.
Inventor(s): Meng Wei of Shanghai City (CN) for micron technology, inc.
IPC Code(s): G06F12/1009, G06F12/02, G06F12/0891
CPC Code(s): G06F12/1009
Abstract: a logical-to-physical (l2p) data structure comprising a plurality of l2p table entries is maintained on the volatile memory device. each l2p table entry comprises a block number and a page table index corresponding to the non-volatile memory device. a plurality of physical-to-logical (p2l) data structures each comprising a plurality of p2l table entries is maintained on the volatile memory device. each of the plurality of p2l data structures corresponds to a portion of the l2p data structure.
20240193144.DATABASE MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc., Brian Toronyi of Boulder CO (US) for micron technology, inc.
IPC Code(s): G06F16/22
CPC Code(s): G06F16/2255
Abstract: a hash corresponding to a bit string is generated. the hash corresponds to an address location in a data structure associated with the bit string. an index and a modifier correspond to the address location in the data structure corresponding to the hash associated with a first address location in the data structure are determined. in response to determining that the modifier has a first value associated therewith, index information corresponding to the bit string is written to the first address location in the data structure. in response to determining that the modifier has a second value other than the first value associated therewith, the index information corresponding to the bit string is written to a second address location in the data structure.
Inventor(s): Richard E. Fackenthal of Carmichael CA (US) for micron technology, inc., Christopher K. Morzano of Boise ID (US) for micron technology, inc., Daniele Vimercati of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G11C11/4097
CPC Code(s): G11C11/4097
Abstract: devices and methods for operating a memory device including multiple memory cells configured to store data and multiple global digit lines configured to carry the data in memory accesses of the memory cells. the memory device also includes multiple local digit lines configured to carry the data between the global digit lines and the memory cells. the memory device further includes multiple digit line selection circuits configured to selectively couple selected local digit lines of the local digit lines to the global digit lines. the memory device also includes a controller configured to select a pattern of selected digit line selection circuits to at least partially cancel capacitive coupling between the selected local digit lines.
20240194256.WORD LINE DRIVERS FOR MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Brenton P. Van Leeuwen of Boise ID (US) for micron technology, inc., Mingdong Cui of Folsom CA (US) for micron technology, inc., Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0028
Abstract: systems, methods and apparatus are provided for word line drivers for memory devices. for instance, an apparatus can include sets of word lines, each word line of the sets of word lines configured to access a respective set of one or more memory cells, sets of digit lines, where each word line couples a memory cell of the set of one or more memory cells with each digit line within the sets of digit lines, and a plurality of resistors coupled to the sets of word lines.
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Innocenzo Tortorelli of Cernusco Sul Naviglio (IT) for micron technology, inc.
IPC Code(s): G11C13/00, G11C29/02, G11C29/12
CPC Code(s): G11C13/0033
Abstract: a memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. the plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
Inventor(s): Dmitry Mikulik of Meridian ID (US) for micron technology, inc., Leo Lukose of Leuven (BE) for micron technology, inc., Ramanathan Gandhi of Singapore (SG) for micron technology, inc.
IPC Code(s): G11C16/04, G11C5/06, H10B41/27, H10B41/35, H10B43/27, H10B43/35
CPC Code(s): G11C16/0483
Abstract: memory cells, and memories and memory array structures containing such memory cells, might include a control gate, a channel, a gate dielectric between the channel and the control gate, a charge-storage node between the gate dielectric and the control gate, a charge-blocking material between the charge-storage node and the control gate, a laminated dielectric between the charge-blocking material and the control gate, and a high-k dielectric between the laminated dielectric and the control gate, wherein the laminated dielectric comprises an instance of a first dielectric material between the charge-blocking material and the high-k dielectric and an instance of a second dielectric material between the instance of the first dielectric material and the high-k dielectric, and wherein the instance of the first dielectric material has a higher oxygen areal density than an oxygen areal density of the instance of the second dielectric material.
Inventor(s): Qun Su of Boise ID (US) for micron technology, inc., Pitamber Shukla of Boise ID (US) for micron technology, inc., Ryan Hrinya of Boise ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc., Jose Nino N. Monje of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/04, G11C16/08
CPC Code(s): G11C16/16
Abstract: a method includes determining that a first group of word lines associated with a block of memory cells are in a programmed state and determining that a second group of word lines associated with the block of memory cells are in an unprogrammed state. the method further includes applying a first debiasing voltage to the first group of word lines based on the determination that the first group of word lines are in the programmed state and applying a second debiasing voltage to the second group of word lines based on the determination that the second group of word lines are in the unprogrammed state.
Inventor(s): Ferdinando Bedeschi of Biassono (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc., Umberto Di Vincenzo of Capriate San Gervasio (IT) for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/08, G11C16/30, G11C29/52
CPC Code(s): G11C16/26
Abstract: the present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. a related system is also disclosed.
Inventor(s): Tomer Tzvi Eliash of Sunnyvale CA (US) for micron technology, inc., Yu-Chung Lien of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/32
CPC Code(s): G11C16/3459
Abstract: a system can include a plurality of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices, to perform operations comprising: determining whether a parameter of a power supply of the volatile memory device satisfies a threshold criterion; responsive to determining that the parameter of the power supply satisfies the threshold criterion, modifying a value of a parameter of a program operation; and programming, using the modified value of the parameter, designated data stored on the volatile memory device to a designated location on the non-volatile memory device.
Inventor(s): Daniel P. Cram of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/08
CPC Code(s): G11C29/08
Abstract: methods, systems, and devices for thermal conduction based batch testing system are described. a testing system may include a set of memory devices may arranged on a loading cartridge and placed within the testing system. the testing system may include one or more test boards located in parallel with the memory devices within the testing system. in some cases, the testing system may push the test boards toward the cartridge, causing the memory devices to thermally couple with a heater board. the testing system may include a fluid filled cooling plate thermally coupled with the heater board. in some examples, the testing system may generate a vacuum within a housing containing the test boards and cartridge, which may cause the outside atmosphere to apply a force on the test boards towards the heater board.
Inventor(s): Christophe Laurent of Agrate Brianza (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc.
IPC Code(s): G11C29/42, G11C29/12, G11C29/52
CPC Code(s): G11C29/42
Abstract: the present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, wherein a number of used parity cells is selected based on a status of the memory cells and is related to a selected error correction code (ecc) correction capability, and performing an ecc operation on the plurality of memory cells, the ecc correction capability being based on the selected number of used parity cells. related memory devices and systems are also herein disclosed.
20240194287.REPAIR TECHNIQUES FOR COUPLED MEMORY DIES_simplified_abstract_(micron technology, inc.)
Inventor(s): James Brian Johnson of Boise ID (US) for micron technology, inc., Brent Keeth of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Eiichi Nakano of Boise ID (US) for micron technology, inc., Amy Rae Griffin of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/02
CPC Code(s): G11C29/52
Abstract: methods, systems, and devices for repair techniques for coupled host and memory dies are described. for example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of circuitry configured to access the set of memory arrays, and a second die may include a second portion of circuitry configured to access the set of memory arrays. the second portion of the circuitry (e.g., of the second die) may be configured to support various repair techniques for operations with the set of memory arrays, including techniques in response to column failures or serialization failures associated with the first die, or in response to contact or other interconnection failures with or between the first die and the second die, among other techniques that may be differentiated based on an attribution of error conditions.
Inventor(s): Shyam Surthi of Boise ID (US) for micron technology, inc., David H. Wells of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L21/033, H01L21/32, H10B69/00
CPC Code(s): H01L21/76897
Abstract: semiconductor devices including self-aligned vertical connectors are disclosed herein. the self-aligned vertical connectors may have upper and lower portions that are concentric or have fixed relative positions across the connectors. the concentric or fixed relative positions may be aligned with a corresponding circuit or a bit line based on forming a conformal depression by depositing a controlled amount of conformal layer that fills wells adjacent to the bit line at a target location of the vertical connector. the vertical connector can be formed using the conformal depression, which may be self-aligned relative to the bit line as a result of filling the wells with the controlled amount of the conformal layer.
20240194547.SUBSTRATES FOR SEMICONDUCTOR PACKAGES_simplified_abstract_(micron technology, inc.)
Inventor(s): Ling Pan of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Kelvin Aik Boo Tan of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/13, H01L21/48, H01L23/00, H01L23/498, H01L25/18, H10B80/00
CPC Code(s): H01L23/13
Abstract: a variety of applications can include systems having packaged electronic devices. one or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. the first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. the second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. the second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.
Inventor(s): Min Hua Chung of Taichung (TW) for micron technology, inc., Chong Leong Gan of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/29, H01L21/56
CPC Code(s): H01L23/295
Abstract: a semiconductor device assembly is provided. the assembly includes a support layer with an inside surface, a semiconductor device, and an encapsulant material. the encapsulant material includes a bulk material and thermally conductive nanoparticles, each nanoparticle having an electrically insulative shell and an electrically conductive core. the semiconductor device is disposed on the inside surface of the support layer, the thermally conductive nanoparticles are evenly distributed throughout the bulk material, and the encapsulant material at least partially encapsulates the semiconductor device.
Inventor(s): Ravi Kumar Kollipara of Puppalaguda (IN) for micron technology, inc., Suresh Reddy Yarragunta of Bangalore (IN) for micron technology, inc.
IPC Code(s): H01L23/473, H01L21/56, H01L25/18, H10B80/00
CPC Code(s): H01L23/473
Abstract: a semiconductor device assembly is provided that includes a cooling system. the semiconductor device assembly includes a semiconductor die assembled onto a substrate. a channel is disposed at a back side of the semiconductor die to enable fluid to flow through the channel and cause heat to transfer from the semiconductor die to the fluid. the fluid is received through an inlet to enable the fluid to be flowed through the channel. after the fluid is flowed through the channel, the fluid is expelled through an outlet. in this way, a compact and effective cooling system for a semiconductor device assembly may be implemented.
Inventor(s): See Hiong LEOW of Singapore (SG) for micron technology, inc., Hong Wan NG of Singapore (SG) for micron technology, inc., Seng Kim YE of Singapore (SG) for micron technology, inc., Kelvin Aik Boo TAN of Singapore (SG) for micron technology, inc., Ling PAN of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/48, H01L25/00, H01L25/18, H10B80/00
CPC Code(s): H01L24/48
Abstract: implementations described herein relate to various semiconductor device assemblies. in some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. in some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. the semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. in some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/06, G11C5/06, H01L21/8238, H01L23/538, H01L25/065, H01L27/092
CPC Code(s): H01L27/0688
Abstract: methods, systems, and devices for transistor configurations for multi-deck memory devices are described. a memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. the memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. the memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. the stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.
20240196569.THERMAL ISOLATION FOR MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Suresh Reddy Yarragunta of Bangalore (IN) for micron technology, inc., Deepu Narasimiah Subhash of Bangalore (IN) for micron technology, inc.
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20509
Abstract: methods, systems, and devices for thermal isolation for memory systems are described. the enclosed heatsink architectures may impede heat transfer from a first group of components to a second group components. some examples include a partition (an air gap or other thermally insulating material) between multiple heatsinks. the heatsinks may each have heat transfer elements with various structures. in some examples, a first heatsink may overlap a second heatsink. the overlapping architecture may increase the size of the heatsink corresponding to the first set of components and increase their rate of heat exchange. in some examples, the heatsink architecture may include upper heatsinks and lower heatsinks. the enclosed heatsink architectures may reduce device overheating and time spent in thermal throttling, as well as improve the life expectancy, durability, efficiency, and performance of the memory devices. increased efficiency in cooling the device may save energy costs.
Inventor(s): Srinivas Pulugurtha of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C11/408, G11C11/4091, G11C11/4093, G11C11/4097
CPC Code(s): H10B12/50
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a memory cell, first, second, and third data lines, and first and second access lines. each of the first, second, and third data lines includes a length extending in a first direction. each of the first and second access lines includes a length extending in a second direction. the memory cell includes a first transistor including a charge storage structure, and a first channel region electrically separated from the charge storage structure, and a second transistor including a second channel region electrically coupled to the charge storage structure. the first data line is electrically coupled to the first channel region. the second data line is electrically coupled to the first channel region. the third data line is electrically coupled to the second channel region, the second channel region being between the charge storage structure and the third data line. the first access line is located on a first level of the apparatus and separated from the first channel by a first dielectric. the second access line is located on a second level of the apparatus and separated from the second channel by a second dielectric. the charge storage structure is located on a level of the apparatus between the first and second levels.
Inventor(s): Lifang Xu of Boise ID (US) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc., Indra V. Chary of Boise ID (US) for micron technology, inc., Richard J. Hill of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B41/35, G11C5/02, G11C16/04, H10B41/10, H10B41/20, H10B43/10, H10B43/20, H10B43/35
CPC Code(s): H10B41/35
Abstract: a microelectronic device includes a stack structure comprising blocks, additional dielectric slot structures, and a further dielectric slot structure. the stack structure includes alternating tiers of conductive and insulative structures. a block comprises a stadium structure and crest regions. the stadium structure includes staircase structures having steps comprising edges of the tiers. the additional dielectric slot structures individually extend in the first direction across a first of the crest regions and at least partially into the stadium structure. the additional dielectric slot structures are separated from one another in a second direction orthogonal to the first direction and individually vertically extend through the tiers. the further dielectric slot structure extends in the second direction across a second of the crest regions. the further dielectric slot structure intersects at least one of the additional dielectric slot structures and vertically extend through the tiers.
Inventor(s): Thomas M. Graettinger of Boise ID (US) for micron technology, inc., Lorenzo Fratin of Buccinasco (IT) for micron technology, inc., Patrick M. Flynn of Boise ID (US) for micron technology, inc., Enrico Varesi of Milano (IT) for micron technology, inc., Paolo Fantini of Vimercate (IT) for micron technology, inc.
IPC Code(s): H10N70/00
CPC Code(s): H10N70/8265
Abstract: methods, systems, and devices for a memory device with laterally formed memory cells are described. a material stack that includes a conductive layer between multiple dielectric layers may be formed, where the conductive layer and dielectric layers may form a channel in a sidewall of the material stack. the channel may be filled with one or more materials, where a first side of an outermost material of the one or more materials may be exposed. an opening may be formed in the material stack that exposes a second side of at least one material of the one or more materials. the opening may be used to replace a portion of the at least one material with a chalcogenide material where the electrode materials may be formed before replacing the portion of the at least one material with the chalcogenide material.
Micron Technology, Inc. patent applications on June 13th, 2024
- Micron Technology, Inc.
- G06F3/06
- CPC G06F3/0619
- Micron technology, inc.
- CPC G06F3/0631
- CPC G06F3/064
- G06F12/02
- CPC G06F3/0655
- CPC G06F3/0659
- G11C11/408
- G11C11/4094
- G06F9/30
- G06F7/544
- CPC G06F9/3001
- G06F15/78
- G06F15/82
- CPC G06F9/30065
- G06F11/14
- G06F9/4401
- CPC G06F11/1417
- G06F12/0815
- CPC G06F12/0815
- G06F12/1009
- G06F12/1045
- CPC G06F12/1009
- G06F12/0891
- G06F16/22
- CPC G06F16/2255
- G11C11/4097
- CPC G11C11/4097
- G11C13/00
- CPC G11C13/0028
- G11C29/02
- G11C29/12
- CPC G11C13/0033
- G11C16/04
- G11C5/06
- H10B41/27
- H10B41/35
- H10B43/27
- H10B43/35
- CPC G11C16/0483
- G11C16/16
- G11C16/08
- CPC G11C16/16
- G11C16/26
- G11C16/30
- G11C29/52
- CPC G11C16/26
- G11C16/34
- G11C16/10
- G11C16/32
- CPC G11C16/3459
- G11C29/08
- CPC G11C29/08
- G11C29/42
- CPC G11C29/42
- CPC G11C29/52
- H01L21/768
- H01L21/033
- H01L21/32
- H10B69/00
- CPC H01L21/76897
- H01L23/13
- H01L21/48
- H01L23/00
- H01L23/498
- H01L25/18
- H10B80/00
- CPC H01L23/13
- H01L23/29
- H01L21/56
- CPC H01L23/295
- H01L23/473
- CPC H01L23/473
- H01L25/00
- CPC H01L24/48
- H01L27/06
- H01L21/8238
- H01L23/538
- H01L25/065
- H01L27/092
- CPC H01L27/0688
- H05K7/20
- CPC H05K7/20509
- H10B12/00
- G11C11/4091
- G11C11/4093
- CPC H10B12/50
- G11C5/02
- H10B41/10
- H10B41/20
- H10B43/10
- H10B43/20
- CPC H10B41/35
- H10N70/00
- CPC H10N70/8265
