Micron Technology, Inc. patent applications on July 25th, 2024
Patent Applications by Micron Technology, Inc. on July 25th, 2024
Micron Technology, Inc.: 44 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (12), H10B41/27 (5), H10B43/27 (5), G11C16/04 (4), H10B43/35 (3) H10B43/27 (4), G06F3/0619 (3), G06F3/0625 (2), G06F3/0659 (2), G11C16/102 (2)
With keywords such as: memory, data, device, region, conductive, voltage, line, signal, cells, and control in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Gil Golov of Backnang (DE) for micron technology, inc.
IPC Code(s): B60W50/00, B60H1/00, B60R11/00, B60R11/04, G06N3/08, G06V20/59, G08B21/22
CPC Code(s): B60W50/0098
Abstract: the disclosed embodiments are directed to detecting persons or animals trapped in vehicles and providing automated assistance to such persons or animals. in one embodiment a method is disclosed comprising detecting that a vehicle is stopped; activating at least one camera and recording at least one image of an interior of the vehicle using the at least one camera; classifying the at least one image using a machine learning model; and operating at least one subsystem of the vehicle in response to detecting that classifying indicates that a person or animal is present in the at least one image.
20240248612. PROGRAM PULSE MODIFICATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Lei Lin of Fremont CA (US) for micron technology, inc., Peng Zhang of Los Altos CA (US) for micron technology, inc., Pitamber Shukla of San Jose CA (US) for micron technology, inc., Zhengang Chen of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to modify pulses used to program memory components. the controller receives a request to program data in an individual memory component of a set of memory components. the controller computes a plurality of memory reliability criteria associated with the individual memory component and compares the plurality of memory reliability criteria to one or more threshold values. the controller selects a program pulse used to program the data to the individual memory component based on a result of comparing the plurality of memory reliability criteria to the one or more threshold values.
Inventor(s): Joseph Harold Steinmetz of Loomis CA (US) for micron technology, inc., Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: an apparatus with a solid state drive (ssd) having firmware to farm proof of space plots stored outside of the ssd. the ssd has a communication interface configured to receive at least read commands and write commands from an external host system. the ssd has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. the firmware is executable in the ssd to receive and store configuration data specified via a user interface to indicate a location, outside of the ssd, storing a proof of space plot that can be used by the ssd to participate in proof of space activities in a cryptocurrency network.
Inventor(s): Sandeep Reddy Kadasani of Meridian ID (US) for micron technology, inc., Pitamber Shukla of San Jose CA (US) for micron technology, inc., Scott Anthony Stoller of Boise ID (US) for micron technology, inc., Niccolo' Righetti of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a set of threshold voltage distribution width measurements are obtained for a block in a memory device. an endurance estimate is determined for the block based on the threshold voltage distribution width measurements. the endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. one or more parameters of the block are managed based on the endurance estimate.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc., Tomer Tzvi ELIASH of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. the likelihood of a read retry timeout meeting a threshold is determined. a reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. the read retry operation is executed using the selected trim setting.
Inventor(s): Shivam Swami of Folsom CA (US) for micron technology, inc., Kenneth Marion Curewitz of Cameron Park CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0804
CPC Code(s): G06F3/0625
Abstract: systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. in one approach, a controller evaluates a demand on memory performance. if the demand of a current computation task needed by the host is high, a dram device is powered-up to meet the demand. otherwise, if the non-volatile memory device is adequate to meet the demand, the dram memory is partially or fully-powered down to save power. in another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., dram). a performance capability of a second memory device (e.g., nvram) is determined. a controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. in response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.
Inventor(s): Ximin Shan of San Jose CA (US) for micron technology, inc., Venkata Naga Lakshman Pasala of Milpitas CA (US) for micron technology, inc., Noorshaheen Mavungal Noorudheen of Trichur Kerala (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: a front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.
Inventor(s): Go Shikata of San Jose CA (US) for micron technology, inc., Xiangyu Yang of San Jose CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a memory device can include a memory array coupled with control logic. the control logic initiates a read operation on one or more memory cells of a plurality of memory cells arranged in one or more tiers. the control logic can further cause a read voltage to be applied to a selected wordline coupled to the one or more memory cells during the read operation. the control logic can cause a first voltage to be applied to a first set of unselected wordlines coupled to memory cells in a first tier of the one or more tiers during the read operation. the control logic can cause a second voltage to be applied to a second set of unselected wordlines coupled to memory cells in a second tier of the one or more tiers during the read operation, wherein the second voltage is less than the first voltage.
Inventor(s): Trevor Conrad Meyerowitz of Morgan Hill CA (US) for micron technology, inc., Dhawal Bavishi of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C5/04
CPC Code(s): G06F3/0656
Abstract: a system having a processing device and a controller, operatively connected to a memory sub-system via a communication channel, to: store information identifying an amount of available capacity of a buffer of the memory sub-system; transmit, through the communication channel to the memory sub-system, one or more write commands to store data in memory components of the memory sub-system, where the memory sub-system queues the one or more write commands in the buffer; update the information by deducting, from the amount of available capacity, an amount of buffer capacity used by the one or more write commands to generate a current amount of available capacity of the buffer; and determine whether to generate an information request to the memory sub-system based at least in part on the current amount of available capacity.
20240248646. WORKLOAD-BASED SCAN OPTIMIZATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Lakshmi Kalpana Vakati of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.
Inventor(s): Shakeel Isamohiuddin BUKHARI of San Jose CA (US) for micron technology, inc., Mark ISH of Manassas VA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
CPC Code(s): G06F3/0659
Abstract: a memory device may include logical units configured to store data, wherein the logical units are identified by corresponding logical unit numbers (luns) and are associated with corresponding lun queue groups. each lun queue group may include lun queues that are each associated with a respective intra-lun priority level that indicates a priority of a lun queue within a lun queue group. the lun queues are each associated with a respective execution priority level that indicates a priority for execution of commands in a lun queue across lun queue groups. a quantity of intra-lun priority levels may be greater than a quantity of execution priority levels. a lun scheduler may be configured to select and transfer commands from lun queue groups to the execution queue group based on intra-lun priority levels. a command executor may be configured to execute commands from the execution queue group based on execution priority levels.
Inventor(s): Gil Golov of Backnang (DE) for micron technology, inc.
IPC Code(s): G06F9/4401, B60R16/023, B60R16/03
CPC Code(s): G06F9/4408
Abstract: disclosed are devices and methods for improving the pre-booting of electronic control unit devices in vehicles. in one embodiment, a method is disclosed comprising detecting a triggering of a pre-booting condition based on one or more interactions with a vehicle; transmitting a power-on signal to at least one electronic control unit (ecu) in the vehicle, the at least one ecu operating in a low-power state; and fully booting the at least one ecu upon determining that the vehicle has been started.
20240248781. ERROR TRACKING BY A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Sai Krishna Mylavarapu of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0787
Abstract: methods, systems, and devices for error tracking by a memory system are described. a memory system transmit indications of corrupt data without storing (e.g., internally storing) the indication. in some examples, a memory system may read data (e.g., from an associated memory device) and detect an error in the data. the memory system may generate an indication of the error and may transmit the indication to a host device. in other examples, a host device may transmit corrupted data with an indication of such. the memory system may store the corrupt data (e.g., an inverted version of the corrupt data) and, upon receiving a subsequent read command, may transmit the corrupt data to the host system with an indication that the data is corrupt.
Inventor(s): Gerald L. Cadloni of Longmont CO (US) for micron technology, inc., Bruce A. Liikanen of Berthoud CO (US) for micron technology, inc., Violante Moschiano of Avezzano (IT) for micron technology, inc.
IPC Code(s): G06F11/07, G11C16/04, G11C16/26
CPC Code(s): G06F11/079
Abstract: an apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to one or each received data access command. the multiple read results may be used to dynamically calibrate a read voltage assigned to generate a read result in response to a read command.
Inventor(s): Shawn Storm of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1008
Abstract: a plurality of signals within a memory sub-system are analyzed by a signal analyzer component. relevant signals among the plurality of signals are determined by the signal analyzer component such that the relevant signals comprise a subset of signals among the plurality of signals. information corresponding to the relevant signals is sampled by the signal analyzer component and the signal analyzer component is responsible for extracting the information corresponding to the relevant signals among the plurality of signals.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/106
Abstract: apparatuses, systems, and methods for per row error correct and scrub (precs) information. there may be precs information associated with each row, and it may reflect a number of codewords stored along that row which were determined to include an error during error correct and scrub (ecs) operations. the memory may store the precs information in the memory array, for example, each row may store the precs information associated with that row.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc., Christopher Joseph Bueb of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F3/06, G06F12/06
CPC Code(s): G06F12/0246
Abstract: a technique to control write operations in a logical partition. for example, a device can receive a user specified write threshold for the logical partition that is hosted on a pool of memory cells shared by a plurality of logical partitions in wear leveling. an accumulated amount of data written into the memory cells according to write requests addressing the logical partition is tracked. in response to the accumulated amount reaches the write threshold, further write requests addressing the logical partition can be blocked, rejected, and/or ignored. for example, the logical partition can be used to buffer data for time shift in playing back content streaming from a server. write operations for time shift can be limited via the user specified threshold to prevent overuse of the total program erasure budget of the pool of memory cells shared with other logical partitions.
20240248846. RECALL PENDING CACHE LINE EVICTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Dean E. Walker of Allen TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F12/0855, G06F12/0891
CPC Code(s): G06F12/0855
Abstract: system and techniques for recall pending cache line eviction are described herein. a queue that includes a deferred memory request is kept for a cache line. metadata for the queue is stored in a cache line tag. when a recall is needed, the metadata is written from the tag to a first recall storage, referenced by a memory request id. after the recall request is transmitted, the memory request id is written to a second recall storage referenced by the message id of the recall request. upon receipt of a response to the recall request, the queue for the cache line can be restored by using the message id in the response to lookup the memory request id from the second recall storage, then using the memory request id to lookup the metadata from the first recall storage, and then writing the metadata into the tag for the cache line.
Inventor(s): Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Samuel E. Bradshaw of Sacramento CA (US) for micron technology, inc., Kenneth Marion Curewitz of Cameron Park CA (US) for micron technology, inc., Sean Stephen Eilert of Penryn CA (US) for micron technology, inc., Dmitri Yudanov of Sacramento CA (US) for micron technology, inc.
IPC Code(s): G06F12/10, H04L67/1097, H04W84/04
CPC Code(s): G06F12/10
Abstract: systems, methods and apparatuses of distributed computing based on memory as a service are described. for example, a set of networked computing devices can each be configured to execute an application that accesses memory using a virtual memory address region. each respective device can map the virtual memory address region to the local memory for a first period of time during which the application is being executed in the respective device, map the virtual memory address region to a local memory of a remote device in the group for a second period of time after starting the application in the respective device and before terminating the application in the respective device, and request the remote device to process data in the virtual memory address region during at least the second period of time.
Inventor(s): Samuel E. Bradshaw of Sacramento CA (US) for micron technology, inc., Shivasankar Gunasekaran of Folsom CA (US) for micron technology, inc., Hongyu Wang of Folsom CA (US) for micron technology, inc., Justin M. Eno of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G06F12/1009, G06F3/06, G06F9/50, G06F12/1027
CPC Code(s): G06F12/1009
Abstract: a computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. in one approach, an operating system allocates memory from a namespace for use by an application. the namespace is a logical reference to physical memory devices in which physical addresses are defined. the namespace is bound to a memory type. in response to binding the namespace to the memory type, the operating system adjusts a page table to map a logical memory address in the namespace to a memory device of the memory type.
Inventor(s): Bhargav Kalva of Boise ID (US) for micron technology, inc., Won Joo Yun of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/20
CPC Code(s): G06F13/20
Abstract: a semiconductor device includes a pair of transistors configured to implement buffering of input data to outputs. the semiconductor device also includes a first transistor configured to receive a common-mode of the outputs at a gate terminal of the first transistor. the semiconductor device also includes a current source configured to control a tail current from the pair of transistors. additionally, the semiconductor device includes a second transistor configured to adjust the tail current based at least in part on changes in a reference voltage used by the pair of transistors to buffer the input data. furthermore, the semiconductor device includes a third transistor configured to adjust the tail current based at least in part on changes in locally generated reference voltage based at least in part on a process and temperature variations.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06N3/063, H04N23/617, H04N25/709, H04N25/75, H04N25/771, H04N25/79
CPC Code(s): G06N3/063
Abstract: a method of artificial neural network computations, including: receiving image data having pixel values; generating, from the pixel values, a column of inputs to a set of artificial neurons; identifying a region of memory cells of the integrated circuit device having threshold voltages programmed to represent a weight matrix for the set of artificial neurons; instructing voltage drivers in the integrated circuit device to apply voltages to the region of memory cells according to the column of inputs; obtaining, based on the region of memory cells responsive to the applied voltages, a first column of data from an operation of multiplication and accumulation applied on the weight matrix and the column of inputs; and applying activation functions of the set of artificial neurons to the first column of data to generate a second column of data representative of outputs of the set of artificial neuron.
Inventor(s): Robert Richard Noel Bielby of Placerville CA (US) for micron technology, inc.
IPC Code(s): G06V20/59, B60K31/16, B60W60/00, G06F18/214, G06F18/25, G06V40/16, G06V40/50
CPC Code(s): G06V20/593
Abstract: a profile is automatically generated for an occupant of a vehicle. in one approach, data is collected from an interior of a vehicle to determine whether an occupant is present. if an occupant is present, a local profile is automatically generated. the local profile is sent to a remote computing device. the remote computing device links the local profile to a remote profile stored by the remote computing device. configuration data is generated by the remote computing device based on linking the local and remote profiles. the configuration data is sent to the vehicle and used by the vehicle to control the operation of one or more components of the vehicle.
Inventor(s): Gil Golov of Backnang (DE) for micron technology, inc.
IPC Code(s): G08G1/16, B60Q9/00, G06N3/04, G06N3/08, G07C5/00
CPC Code(s): G08G1/163
Abstract: the disclosed embodiments are directed to improving the persistence of pre-accident data in vehicles. in one embodiment a method is disclosed comprising receiving events broadcast over a vehicle bus; classifying the events using a machine learning model, the classifying comprising indicating that a collision is imminent; and copying data from a cyclic buffer of a black box device into a long-term storage device in response to the classifying.
Inventor(s): Eric J. Stave of Meridian ID (US) for micron technology, inc., Dirgha Khatri of Boise ID (US) for micron technology, inc., Elancheren Durai of Boise ID (US) for micron technology, inc., Quincy R. Holton of Kuna ID (US) for micron technology, inc., Timothy M. Hollis of Meridian ID (US) for micron technology, inc., Matthew B. Leslie of Boise ID (US) for micron technology, inc., Baekkyu Choi of San Jose CA (US) for micron technology, inc., Boe L. Holbrook of Boise ID (US) for micron technology, inc., Yogesh Sharma of Boise ID (US) for micron technology, inc., Scott R. Cyr of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C8/18, G11C7/10, G11C8/06, G11C8/12
CPC Code(s): G11C8/18
Abstract: memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).
Inventor(s): Makoto Kitagawa of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C11/22
CPC Code(s): G11C11/2255
Abstract: methods, systems, and devices for mitigating disturbance of digit lines at plate edges are described. generally, the described techniques relate to disturbance mitigation for one or more memory cells of a sub-array associated with an unselected digit lines located at an edge of the sub-array by including an additional shunt configured to selectively couple the edge digit lines with an associated plate line. for example, a central digit line may be coupled with a respective one of a first set of selection components and a respective one of a second set of selection components, while an edge digit line may be coupled with a respective one of the first set of selection components, a respective one of the second set of selection components, as well as a respective one of a third set of selection components.
Inventor(s): Gianluca COPPOLA of Liveri (IT) for micron technology, inc.
IPC Code(s): G11C11/406, G11C29/52
CPC Code(s): G11C11/40615
Abstract: in some implementations, a memory device may receive, from a host device, real-time clock information. the memory device may receive, from the host device, an indication of a refresh period. the memory device may determine that the refresh period has expired based on the real-time clock information. the memory device may perform a memory refresh on a memory of the memory device based on the refresh period being expired.
Inventor(s): Jinha Hwang of Boise ID (US) for micron technology, inc., Won Joo Yun of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/4076, G11C11/4093
CPC Code(s): G11C11/4091
Abstract: a semiconductor device includes an interface configured to receive clock signals and data signals. the interface includes a dual-tail latch. the dual-tail latch includes a sensing stage configured to sense and to amplify a differential voltage between at least a portion of the data signals and another signal. the sensing stage includes a first node and a second node between which the amplified differential voltage is output from the sensing stage. the dual-tail latch also includes a latch stage configured to latch a first latched value and a second latched value based at least in part on the amplified differential voltage. moreover, the differential voltage is based at least in part on a previous first value and a previous second value from the latch stage fed back to the sensing stage.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/04, G11C5/06, G11C16/30
CPC Code(s): G11C16/0483
Abstract: a semiconductor device can include a substrate of semiconductor material and multiple stacks of memory cells disposed within the substrate. each of the stacks can include a conductive string that connects memory cells to a bitline where each memory cell is located at an intersection of the conductive string and a wordline. the device can also include capacitor having a cylindrical body disposed between two adjacent stacks of memory cells where the capacitor includes an inner conductive layer and an outer conductive layer at least partially surrounding the inner conductive layer, where the inner conductive layer and the outer conductive layer are separated by a dielectric layer. the device can further include a power supply line conductively connected to an end of the capacitor at a base of the cylindrical body.
Inventor(s): Vinh Quang Diep of Hayward CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Yingda Dong of Los Altos CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/12
CPC Code(s): G11C16/102
Abstract: a request to execute a programming operation to program a set of memory cells associated with a target wordline of a memory device is identified. at a first time during application of a programming voltage to the target wordline, causing a first adjusted pass through voltage to be applied to a first portion of a first set of drain-side wordlines of the memory device. at a second time during application of the programming voltage to the target wordline, causing a second pass through voltage to be applied to a second portion of the first set of drain-side wordlines and to one or more source-side wordlines of the memory device, where the first adjusted pass through voltage is greater than the second pass through voltage.
Inventor(s): Umberto Di Vincenzo of Capriate San Gervasio (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/26, G11C16/30
CPC Code(s): G11C16/102
Abstract: apparatuses, methods, and systems for storing one data value by programming a first memory cell and a second memory cell are disclosed. the first memory cell and the second memory cell may each be programmed to a first data state, a second data state, or a third data state, and the one data value can correspond to a combination of the first data state, the second data state, or the third data state to which the first memory cell and the second memory cell are programmed, where two combinations of the first data state, the second data state, or the third data state to which the first memory cell is programmable and the first data state, the second data state, or the third data state to which the second memory cell is programmable are ineligible to correspond to the one data value.
Inventor(s): Tarun Singh Yadav of Boise ID (US) for micron technology, inc., Scott Anthony Stoller of Boise ID (US) for micron technology, inc., Pitamber Shukla of San Jose CA (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc., Attila A. Herrera of Boise ID (US) for micron technology, inc., Justin Bates of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/12
CPC Code(s): G11C29/1201
Abstract: aspects of the present disclosure configure a memory sub-system controller to adaptively allocate word lines (wls). the controller accesses reliability data of a set of main wls of a block of the set of memory components. the controller determines that one or more wls of the set of main wls of the block are associated with respective reliability data that transgress a threshold and, in response to determining that the one or more wls are associated with the respective reliability data that transgress the threshold, replaces the one or more wls of the set of main wls of the block with one or more dummy wls. the controller programs data into the block using the one or more dummy wls instead of the one or more wls of the set of main wls of the block.
Inventor(s): KENICHI ECHIGOYA of Sagamihara (JP) for micron technology, inc., HIDEKAZU EGAWA of Tokyo (JP) for micron technology, inc.
IPC Code(s): H01L23/522, H01L23/528, H10B12/00
CPC Code(s): H01L23/5228
Abstract: according to one or more embodiments of the disclosure, an apparatus comprising a voltage dividing circuit is provided. the voltage dividing circuit includes a first resistor unit, a second resistor unit parallel to the first resistor unit in a first direction, and a bridge. the bridge is between the first resistor unit and the second resistor unit and links a first middle portion of the first resistor unit to a second middle portion of the second resistor unit. the first and second middle portions are middle portions of the first and the second resistor units in a second direction perpendicular to the first direction.
Inventor(s): Surendranath C. Eruvuru of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, G11C16/04, H10B41/10, H10B41/20, H10B41/35, H10B43/10, H10B43/20, H10B43/35
CPC Code(s): H01L23/5283
Abstract: a stairless electrical interconnect structure with contact pillars embedded within and collectively accessing each tier in a periodic material stack, e.g., to provide electrical connections to access lines associated with a three-dimensional memory array, is described. the contact pillars can be formed in a corresponding array of vertical contact pillar trenches etched into the material stack in two stages to create depths of the trenches that vary between columns by a fixed number of tiers and then offset the depths between rows.
Inventor(s): Shuangqiang Luo of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc., Xiao Li of Boise ID (US) for micron technology, inc., Jivaan Kishore Jhothiraman of Meridian ID (US) for micron technology, inc., Mohad Baboli of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/535, H01L21/768, H01L23/522, H01L23/528, H10B41/27, H10B43/27
CPC Code(s): H01L23/535
Abstract: a microelectronic device comprises a stack structure comprising an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. each of the blocks comprises a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. the stadium structure comprises staircase structures each having steps comprising edges of the tiers of the stack structure. the filled trench comprises a dielectric material interposed between at least two additional dielectric materials. the dielectric liner structures comprise first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. the second protrusions have greater horizontal dimensions than the first protrusions. memory devices, electronic systems, and methods are also described.
Inventor(s): Ahmed Nayaz Noemaun of Boise ID (US) for micron technology, inc., Stephen W. Russell of Boise ID (US) for micron technology, inc., Tao D. Nguyen of Boise ID (US) for micron technology, inc., Santanu Sarkar of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/40, H01L21/82, H01L29/66
CPC Code(s): H01L29/408
Abstract: some embodiments include an integrated assembly having a pair of substantially parallel features spaced from one another by an intervening space. a conductive pipe is between the features and substantially parallel to the features. the conductive pipe may be formed within a tube. the tube may be generated by depositing insulative material between the features in a manner which pinches off a top region of the insulative material to leave the tube as a void region under the pinched-off top region.
Inventor(s): Yasuo Satoh of Tsukuba (JP) for micron technology, inc.
IPC Code(s): H03K5/156, G11C11/4076
CPC Code(s): H03K5/1565
Abstract: an apparatus according to some embodiments comprises: a first clock path including a first duty-cycle adjuster that adjusts a duty cycle of a first input clock signal, a second clock path including a second duty-cycle adjuster that adjusts a duty cycle of a second input clock signal having a different phase from the first input clock signal; and a control circuit configured to detect longest one or shortest one of first, second, third, and fourth time periods to generate a control signal. the first, second, third and fourth time periods are defined by phase differences between rising edges and falling edges of the first and second input clock signals.
Inventor(s): Aaron P. Boehm of Boise ID (US) for micron technology, inc., Scott E. Schaefer of Boise ID (US) for micron technology, inc.
IPC Code(s): H03M13/15, G06F11/07, H03M13/00
CPC Code(s): H03M13/159
Abstract: methods, systems, and devices for managing error control information using a register are described. a memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. the memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. the host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C5/06, H01L29/24
CPC Code(s): H10B12/20
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a conductive region, a first data line, a second data line, a first memory cell coupled to the first data line and the conductive region, a second memory cell coupled to the second data line and the conductive region, a conductive structure, and a conductive line. the first memory cell includes a first transistor coupled to a second transistor, the first transistor including a first charge storage structure. the second memory cell includes a third transistor coupled to a fourth transistor, the third transistor including a second charge storage structure. the conductive structure is located between and electrically separated from the first and second charge storage structures. the conductive line forms a gate of each of the first, second, third, and fourth transistors.
20240251552. NAND STAIRCASE LANDING PADS CONVERSION_simplified_abstract_(micron technology, inc.)
Inventor(s): Mojtaba Asadirad of Boise ID (US) for micron technology, inc., Yiping Wang of Boise ID (US) for micron technology, inc., David H. Wells of Boise ID (US) for micron technology, inc., Matt J. King of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: methods, systems, and devices for nand staircase landing pads conversion are described. a memory device may include one or more lateral word line contacts that may couple a word line with a conductive pillar that traverses a stack of materials of the memory device. the use of the lateral word line contact may allow for a conductive pillar to be coupled with a target word line without requiring an end of the conductive pillar to be placed directly on the word line. additionally, the memory architecture described herein may allow for the target word line to be coupled with cmos circuitry via a first conductive pillar without the use of a second conductive pillar, as the first conductive pillar may traverse the stack of materials and be coupled with the cmos circuitry. therefore, total quantity of conductive pillars may be reduced, and the risk of manufacturing errors may be lowered.
Inventor(s): Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc., John D. Hopkins of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/35, H10B41/41, H10B43/35, H10B43/40
CPC Code(s): H10B43/27
Abstract: some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. a source structure is coupled to lower regions of the channel-material-pillars. a panel extends across the memory region and the other region. doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. the doped-semiconductor-material is at least part of the source structure within the memory region. liners are directly adjacent to the conductive posts and laterally surround the conductive posts. the liners are between the conductive posts and the doped-semiconductor-material. some embodiments include methods of forming integrated assemblies.
Inventor(s): Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc., John D. Hopkins of Meridian ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/35, H10B41/41, H10B43/35, H10B43/40
CPC Code(s): H10B43/27
Abstract: some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. channel-material-pillars are arranged within the memory regions. conductive posts are arranged within the intermediate region. a panel extends across the memory regions and the intermediate region. the panel is laterally between a first memory-block-region and a second memory-block-region. doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. the doped-semiconductor-material is at least part of conductive source structures within the memory regions. insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. insulative liners are along upper regions of the conductive posts. some embodiments include methods of forming integrated assemblies.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Nancy M. Lomeli of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H01L21/225, H10B41/27
CPC Code(s): H10B43/27
Abstract: a liner is formed laterally-outside of individual channel-material strings in one of first tiers and in one of second tiers. the liners are isotropically etched to form void-spaces in the one second tier above the one first tier. individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. the conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Eric S. Carman of San Francisco CA (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Richard E. Fackenthal of Carmichael CA (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/50, H01L29/10, H01L29/423
CPC Code(s): H10B43/50
Abstract: some embodiments include apparatuses and methods forming the apparatuses. one of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.
Micron Technology, Inc. patent applications on July 25th, 2024
- Micron Technology, Inc.
- B60W50/00
- B60H1/00
- B60R11/00
- B60R11/04
- G06N3/08
- G06V20/59
- G08B21/22
- CPC B60W50/0098
- Micron technology, inc.
- G06F3/06
- CPC G06F3/0619
- CPC G06F3/0625
- G06F12/0804
- CPC G06F3/0632
- CPC G06F3/0655
- G11C5/04
- CPC G06F3/0656
- CPC G06F3/0659
- G06F12/02
- G06F9/4401
- B60R16/023
- B60R16/03
- CPC G06F9/4408
- G06F11/07
- CPC G06F11/0787
- G11C16/04
- G11C16/26
- CPC G06F11/079
- G06F11/10
- CPC G06F11/1008
- CPC G06F11/106
- G06F12/06
- CPC G06F12/0246
- G06F12/0855
- G06F12/0891
- CPC G06F12/0855
- G06F12/10
- H04L67/1097
- H04W84/04
- CPC G06F12/10
- G06F12/1009
- G06F9/50
- G06F12/1027
- CPC G06F12/1009
- G06F13/20
- CPC G06F13/20
- G06N3/063
- H04N23/617
- H04N25/709
- H04N25/75
- H04N25/771
- H04N25/79
- CPC G06N3/063
- B60K31/16
- B60W60/00
- G06F18/214
- G06F18/25
- G06V40/16
- G06V40/50
- CPC G06V20/593
- G08G1/16
- B60Q9/00
- G06N3/04
- G07C5/00
- CPC G08G1/163
- G11C8/18
- G11C7/10
- G11C8/06
- G11C8/12
- CPC G11C8/18
- G11C11/22
- CPC G11C11/2255
- G11C11/406
- G11C29/52
- CPC G11C11/40615
- G11C11/4091
- G11C11/4076
- G11C11/4093
- CPC G11C11/4091
- G11C5/06
- G11C16/30
- CPC G11C16/0483
- G11C16/10
- G11C16/08
- G11C16/12
- CPC G11C16/102
- G11C29/12
- CPC G11C29/1201
- H01L23/522
- H01L23/528
- H10B12/00
- CPC H01L23/5228
- H10B41/10
- H10B41/20
- H10B41/35
- H10B43/10
- H10B43/20
- H10B43/35
- CPC H01L23/5283
- H01L23/535
- H01L21/768
- H10B41/27
- H10B43/27
- CPC H01L23/535
- H01L29/40
- H01L21/82
- H01L29/66
- CPC H01L29/408
- H03K5/156
- CPC H03K5/1565
- H03M13/15
- H03M13/00
- CPC H03M13/159
- H01L29/24
- CPC H10B12/20
- CPC H10B43/27
- H10B41/41
- H10B43/40
- H01L21/225
- H10B43/50
- H01L29/10
- H01L29/423
- CPC H10B43/50
