Micron Technology, Inc. patent applications on July 18th, 2024
Patent Applications by Micron Technology, Inc. on July 18th, 2024
Micron Technology, Inc.: 35 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (10), G11C11/4096 (3), G06F11/07 (3), G06F11/10 (3), G11C11/408 (3) G06F11/1068 (3), G06F3/0655 (2), G06F3/0659 (2), G01K13/10 (1), G11C16/16 (1)
With keywords such as: memory, device, data, devices, voltage, array, tiers, described, region, and systems in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Luiza Souza Correa of Munich (DE) for micron technology, inc., Julius Löckemann of Munich (DE) for micron technology, inc., Elena Cabrera Bernal of Munich (DE) for micron technology, inc., Martin Brox of Munich (DE) for micron technology, inc., Jun Tan of Weißenfeld (DE) for micron technology, inc.
IPC Code(s): G01K13/10, G01K1/02, G01K7/14
CPC Code(s): G01K13/10
Abstract: methods, systems, and devices for temperature sensor linearization techniques are described. a temperature sensor associated with a semiconductor device may include a first circuit and a second circuit. the second circuit may be configured to determine that a first temperature, associated with the semiconductor device and indicated by one or more first bits generated by the first circuit, is within a first temperature range of a total temperature range measurable by the temperature sensor. the second circuit may be configured to generate and output, based on the first temperature being within the first temperature range, one or more second bits indicating a second temperature associated with the semiconductor device. the second circuit may generate the one or more second bits by applying, to the one or more first bits, a first-order operation corresponding to the first temperature range and associated with correcting an error of the first temperature.
Inventor(s): John D. Leidel of McKinney TX (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F13/16, G06F13/40, G06F13/42, G11C7/10, G11C21/00
CPC Code(s): G06F3/0607
Abstract: an interconnect system includes host devices, one or more memory devices, and a routing system to connect the host devices and the one or more memory devices. respective ones of the host devices include an interface to communicate packet requests over respective packetized links. respective ones of the one or more memory devices include an interface to receive and respond to the packet requests over the respective packetized links. the routing system includes devices interconnected in a routing topology. respective ones of the devices include a switch and interfaces. the routing system is to route the packet requests and responses between the host devices and respective memory device destinations over the respective packetized links.
Inventor(s): Biagio Iorio of Luco dei Marsi (IT) for micron technology, inc., Luca Nubile of Sulmona (IT) for micron technology, inc., Walter Di Francesco of Avezzano (IT) for micron technology, inc., Jeremy Binfet of Boise ID (US) for micron technology, inc., Liang Yu of Boise ID (US) for micron technology, inc., Yankang He of Mountain View CA (US) for micron technology, inc., Ali Mohammadzadeh of Mountain View CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/061
Abstract: control logic on a memory die of a multi-die memory sub-system receives, from a memory sub-system controller, a data burst command indicating an upcoming data burst event and determines an expected current utilization in the memory sub-system during the data burst event. the control logic further determines whether the expected current utilization in the memory sub-system during the data burst event satisfies a threshold criterion and responsive to determining that the expected current utilization in the memory sub-system during the data burst event does not satisfy the threshold criterion, pauses one or more operations being executed by the control logic on the memory die until the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion. responsive to determining that the expected current utilization in the memory sub-system during the data burst event satisfies the threshold criterion, the control logic provides, to the memory sub-system controller, an indication that the data burst event is approved and can perform one or more operations corresponding to the data burst event.
Inventor(s): Caixia Yang of Boise ID (US) for micron technology, inc., Deping He of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: methods, systems, and devices for suspension during a multi-plane write procedure are described. a memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. the memory system may then resume writing to the defective plane.
Inventor(s): Zhenming Zhou of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Nagendra Prasad Ganesh Rao of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining whether a temperature offset value of the segment satisfies a threshold criterion associated with a program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: methods, systems, and devices for partitioned transferring for write booster are described. techniques are described for a memory system to transfer data from a buffer associated with a write booster mode to higher-density blocks of the memory system based on a type of the data stored in the buffer. a first type of data may be transferred from the buffer to the higher-density blocks before a second type of data may be transferred from the buffer to the higher-density blocks. prioritizing the transfer of data from the buffer to the higher-density block based on the type of data may reduce a write amplification associated with the memory system.
Inventor(s): Kevin G. Werhane of Kuna ID (US) for micron technology, inc., Vijayakrishna J. Vankayala of Allen TX (US) for micron technology, inc., Tyrel Z. Jensen of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, apparatuses, and systems related to calibrating memory circuitry according to externally provided reference voltage are described. a memory device may include a calibration control logic that at least isolates an internal reference voltage from an internal buffer. the internal buffer may receive and process the externally provided reference voltage instead of command-address signals for calibration purposes.
20240241673. INTERNAL CLOCK SIGNALING_simplified_abstract_(micron technology, inc.)
Inventor(s): Liang Yu of Boise ID (US) for micron technology, inc., Luigi Pilolli of L'Aquila (IT) for micron technology, inc., Biagio Iorio of Luco dei Marsi (IT) for micron technology, inc.
IPC Code(s): G06F3/06, G06F1/04, G06F1/3234
CPC Code(s): G06F3/0659
Abstract: a method includes selecting a particular ready/busy pin (r/b#) among a plurality of r/b# pins that are associated with respective memory dice among a plurality of memory dice of a memory device. the method further includes receiving, by at least one memory dice among the plurality of memory dice, signaling indicative of performance of a memory access while the particular r/b# pin is set to low, and, initiating an internal clocking signal subsequent to receipt of the signaling indicative of performance of the memory access, wherein the internal clocking signal is associated with timing of operations performed by the plurality of memory dice.
Inventor(s): Qi Dong of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F8/65
CPC Code(s): G06F8/65
Abstract: exemplary methods, apparatuses, and systems include a wireless update programming manager for controlling performance of a wireless update by adjusting bit density of a set of blocks. the wireless update programming manager receives a size of an update file from a host using wireless communication. the wireless update programming manager selects an amount of memory for the update file based on the size to reallocate from a default bit density to a lower bit density than the default bit density. the wireless update programming manager programs a first portion of the update file using the memory reallocated to the lower bit density.
Inventor(s): Gil Golov of Backnang (DE) for micron technology, inc.
IPC Code(s): G06F9/30, G06N3/063
CPC Code(s): G06F9/3001
Abstract: the disclosed embodiments are directed toward improved control circuity for artificial intelligence processors. in one embodiment, a device is disclosed comprising a processing element, the processing element including a processing device configured to receive a first set of vectors; a hijack control circuit, the hijack control circuit configured to replace the first set of vectors with a second set of vectors in response to detecting that the processing element is idle; and a processing element control circuit (pecc), the pecc storing a set of values representing the second set of vectors, the set of values retrieved from a remote data source.
Inventor(s): Harold B Noyes of Boise ID (US) for micron technology, inc., David R. Brown of Lucas TX (US) for micron technology, inc., Paul Glendenning of Woodside CA (US) for micron technology, inc.
IPC Code(s): G06F9/448, G06F13/12, G06F13/16, G06F13/28, G06F13/38, G06F13/42
CPC Code(s): G06F9/4498
Abstract: a system includes a primary device comprising a first state machine lattice comprising a first plurality of configurable elements configured to analyze at least a portion of first data as a first analysis and to output a result of the first analysis. the system also includes a secondary device coupled to the primary device, wherein the secondary device comprises a second plurality of configurable elements configured to analyze at least a portion of second data received from the primary device as a second analysis and to output a result of the second analysis, wherein the primary device
Inventor(s): Santhosh Kumar Siripragada of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F11/10, G06F3/06, G06F11/07
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for techniques for managing memory exception handling are described. a memory device may write first data associated with a first access command to a first portion of a buffer of a memory device. the memory device may determine a programming failure to write second data to a page of a first block of the memory device. in response to determining the programming failure, the memory device may perform an access operation associated with the first access command to vacate the first data from the first portion of the buffer. in response, the memory device may write the second data to the first portion of the buffer. the memory device may write the second data from the first portion of the buffer to a page of a second block of the memory device in response to writing the second data to the first portion of the buffer.
Inventor(s): Christophe Vincent Antoine Laurent of Agrate Brianza (MB) (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (MB (IT) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: in some aspects, the techniques described herein relate to a method including: selecting a plurality of coding tables, the plurality of coding tables including an encoding table and a decoding table; building an error table using the plurality of coding tables, the error table representing potential bit errors that may occur during reading and writing to a memory device using the plurality of coding tables; masking the error table to eliminate error values in the error table meeting a preconfigured condition; determining if the error table includes one or more errors in invalid positions; and storing the error table when the error table does not include one or more errors in invalid positions.
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F11/10, G06F3/06, G06F11/07
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for determining locations in not-and (nand) memory for boot-up code are described. an indication of one or more timeout durations for a boot sequence may be received. information for the boot sequence may be stored in one or more memory cells based on the one or more timeout durations, where the one or more memory cells may be selected based on a read latency, an error rate, or a storage-level of the one or more memory cells with relation to the indicated one or more timeout durations. the information for the boot sequence stored in the one or more memory cells may be accessed based on an initialization of the boot sequence.
20240241793. HOST ASSISTED LINK START_simplified_abstract_(micron technology, inc.)
Inventor(s): Stephen Hanna of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F11/14, G06F1/28
CPC Code(s): G06F11/142
Abstract: methods, systems, and devices for host assisted link start are described. a memory device may receive, from a host device, a first request message for a recovery configuration associated with power recovery of a peripheral of the memory device. the memory device may transmit, to the host device based at least in part on the first request message, a first response message including the recovery configuration associated with the power recovery of the peripheral of the memory device. the recovery configuration may include parametric data associated with the peripheral of the memory device to store at the host device.
Inventor(s): Gaurav SINHA of Unterschleißheim (DE) for micron technology, inc., Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: implementations described herein relate to a shared function for a multi-port memory device. in some implementations, a memory device may include a first port, a second port, and one or more components configured to manage a shared function of the memory device. the shared function of the memory device may enable a host device that is connected to the first port of the memory device to identify and enumerate the second port of the memory device. in some implementations, the shared function of the memory device may establish a virtual connection between the first port and the second port, and may enable the host device that is connected to the first port of the memory device to share a resource or a function with another host device that is connected to the second port of the memory device.
Inventor(s): Christopher Baronne of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F12/126
CPC Code(s): G06F12/126
Abstract: devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. a barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.
Inventor(s): Vijayakrishna J. Vankayala of Allen TX (US) for micron technology, inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1039
Abstract: methods, systems, and devices for read operations for a memory array and register are described. in some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). the memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.
Inventor(s): Christopher Joseph Bueb of Folsom CA (US) for micron technology, inc., Ting Luo of Santa Clara CA (US) for micron technology, inc., Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc., Gianluca Coppola of Liveri (NA) (IT) for micron technology, inc., Ryan Laity of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406
CPC Code(s): G11C11/40626
Abstract: methods, systems, and devices for techniques for data refresh based on environmental conditions are described. a memory system may program data to a set of blocks, where an order in which the data be programmed to respective blocks of the set of blocks may be based on a first block ordering. the memory system may also program respective indications of respective temperatures of the programming for the respective blocks. the memory system may identify, during a start-up procedure, a flag indicating to perform a refresh operation for the set of blocks. as such, the memory system may perform during the start-up procedure, the refresh operation for the set of blocks using a second block ordering. in some examples, the second block ordering may be based on the respective indications of the respective temperatures for the set of blocks.
Inventor(s): Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Go Shikata of San Jose CA (US) for micron technology, inc., Gangotree Chakma of Morgan Hill CA (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C11/4076, G11C11/4096
CPC Code(s): G11C11/4085
Abstract: a memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including identifying a set of parameters related to the memory device, selecting, based on the set of parameters, a magnitude of a bias voltage to be applied to a global wordline during a read state transition of a block of the memory device from a transient state to a stable state, and causing the bias voltage to be applied to the global wordline.
20240242758. MEMORY ARRAY WITH MULTIPLEXED DIGIT LINES_simplified_abstract_(micron technology, inc.)
Inventor(s): Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc., Stefan Frederik Schippers of Peschiera del Garda (VR) (IT) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/408, G11C11/4091, H10B12/00, G11C11/56
CPC Code(s): G11C11/4096
Abstract: methods, systems, and devices for a memory device with multiplexed digit lines are described. in some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. a first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. the selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. in some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
Inventor(s): Tao Jiang of Shanghai (CN) for micron technology, inc., Bo Zhou of Shanghai (CN) for micron technology, inc., Guang Hu of Mountain View CA (US) for micron technology, inc.
IPC Code(s): G11C11/4099, G11C11/4074, G11C11/4076, G11C11/408, G11C11/4096
CPC Code(s): G11C11/4099
Abstract: methods, systems, and devices for reference voltage adjustment for word line groups are described. in some examples, one or more components of a memory system may determine a duration that data has been stored to one or more memory cells. based on the duration, a voltage value of one or more reference voltages may be adjusted accordingly. for example, a voltage value of one or more reference voltages may be adjusted based on the duration. moreover, the reference voltage values may be adjusted differently in response to the memory cells having stored data for a relatively longer duration, as opposed to memory cells that have stored data for a relatively shorter duration. the adjusted reference voltages may be used during a subsequent read operation. the voltage value of the one or more reference voltages may be adjusted on a word-line group by word-line group basis.
Inventor(s): Zhongyuan Lu of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/08, G11C16/10
CPC Code(s): G11C16/16
Abstract: a memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including identifying an erased block of the memory array, causing a set of cells addressable by a target wordline of the erased block to be set to a target threshold voltage, determining an amount of threshold voltage shift with respect to the target threshold voltage after a delay, determining whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric, and in response to determining that the amount of threshold voltage shift is sufficient, releasing the erased block for programming.
Inventor(s): Agostino Pirovano of Milano (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C27/00
CPC Code(s): G11C27/005
Abstract: apparatuses, methods, and systems for using a subthreshold voltage for mapping in memory are disclosed. an example apparatus includes a memory array including a plurality of memory cells each programmable to a first data state or a second data state, and circuitry coupled to the memory array and configured to encode an input vector comprising a first number of data states to be programmed to a first group of memory cells of a memory array, apply a subthreshold voltage to each of a second group of memory cells of the memory array, wherein the second group of memory cells is programmed to a weight vector comprising a second number of data states and wherein the subthreshold voltage is based upon the data states of the input vector, and map the input vector to a location in the memory array using the weight vector after applying the subthreshold voltage.
Inventor(s): Guang Shen of Shanghai (CN) for micron technology, inc.
IPC Code(s): G11C29/50, G06F3/06
CPC Code(s): G11C29/50004
Abstract: disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include computing an adjustment value of a threshold voltage offset associated with a block family of the memory device; determining that the adjustment value satisfies a threshold voltage criterion, wherein the threshold voltage criterion comprises a reference voltage level corresponding to known valley margins of the memory device; and updating the threshold voltage offset.
Inventor(s): Chao Lin Lee of Singapore (SG) for micron technology, inc., Rachmat Wibowo of Singapore (SG) for micron technology, inc., Lipeng Qian of Singapore (SG) for micron technology, inc., SAMUEL SISWANTO of Singapore (SG) for micron technology, inc.
IPC Code(s): H01J37/32
CPC Code(s): H01J37/32449
Abstract: methods, systems, and devices for plasma-assisted film removal for wafer fabrication are described. the present disclosure provides in-situ techniques for removing a film from a select portion of a wafer, such as a surrounding bevel edge. after forming a film on the wafer using chemical vapor deposition (cvd), the wafer may be raised to a higher position in the chamber for cvd. a combination of gases may be ejected from a gas fixture and directed, respectively, to different portions of the wafer. the combination of gases may react to selectively remove the film from the bevel edge of the wafer and maintain the film on other portions of the wafer.
Inventor(s): Kar Wui Thong of Boise ID (US) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc., Richard T. Housley of Boise ID (US) for micron technology, inc., Manampurathu Sivaramapanicker Suresh Kumar of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/544
CPC Code(s): H01L23/544
Abstract: a method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. the first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. the stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. the scribe-line area comprises a horizontal area in which a registration mark or an alignment mark is being fabricated. horizontally-spaced features of the registration mark or of the alignment mark are simultaneously formed in the first tiers and the second tiers in the horizontal area and in the individual die areas. the horizontally-spaced features in the horizontal area are grouped in sections that are horizontally-separated by gaps in at least one vertical cross-section where there are less, if any, such horizontally-spaced features than are in the sections. horizontally-spaced vertical slots are formed through uppermost of the first and second tiers of the stack in the horizontal area of the registration mark or of the alignment mark. through the horizontally-spaced vertical slots, the sacrificial material is replaced with metal material. after the replacing, the first and second tiers in the scribe-line areas are cut through to form individual die that individually comprise one of the individual die areas. other embodiments, including structure, are disclosed.
Inventor(s): Shigeru Sugioka of Higashihiroshima (JP) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/31, H01L23/58
CPC Code(s): H01L23/562
Abstract: according to one or more embodiments, an apparatus includes an insulating structure in the scribe region, a plurality of metal layers, the metal layers including a top metal layer in the insulating structure in the scribe region, a groove on a top of the insulating structure in the scribe region, and an air gap between the top metal layer and the groove in the scribe region.
20240243758. FILLER SYMBOLS FOR DATA BURSTS_simplified_abstract_(micron technology, inc.)
Inventor(s): Praveen Gurrala of Boise ID (US) for micron technology, inc., Bryan D. Butler of Boise ID (US) for micron technology, inc., John Todd Elson of Boise ID (US) for micron technology, inc.
IPC Code(s): H03M13/29, H04L25/03
CPC Code(s): H03M13/2906
Abstract: methods, systems, and devices for filler symbols for data bursts are described. a memory device may insert filler symbols into a stream of data symbols. for example, after transmitting a last data symbol of a data burst, a device may insert one or more filler symbols to maintain an active data burst. the device may randomize the transmission of filler symbols within the data burst. in some cases, the device may randomly select filler symbols from a variety of symbol types, therefore randomizing which one of the symbols is transmitted. in some other cases, the device may randomize the representation of filler symbols within an encoding scheme.
20240244779. SOLID STATE DRIVE ENCLOSURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Suresh Reddy Yarragunta of Bangalore (IN) for micron technology, inc., Deepu Narasimiah Subhash of Bangalore (IN) for micron technology, inc.
IPC Code(s): H05K5/02, H05K7/20
CPC Code(s): H05K5/026
Abstract: a number of embodiments of the present disclosure include an solid state drive (ssd) enclosure comprising a first component, wherein the first component is configured to cover a first side of an ssd, a second component; and a third component, wherein the third component is configured receive the second component, wherein the third component is configured to be releasably coupled to the second component, and wherein the second component and the third component are configured to cover a second side of the ssd.
Inventor(s): Scott E. Sills of Boise ID (US) for micron technology, inc., Si-Woo Lee` of Saratoga CA (US) for micron technology, inc., Richard E. Fackenthal of Carmichael CA (US) for micron technology, inc., Hiroki Fujisawa of Tokyo (JP) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: a microelectronic device includes memory array regions of memory cells each including a vertical stack structure comprising conductive structures vertically spaced from one another and horizontally extending through a vertical stack of memory cells. a staircase region is horizontally between two of the memory array regions horizontally neighboring one another and includes a first staircase structure horizontally extending from the vertical stack structure of a first of the two of the memory array regions and a second staircase structure horizontally extending from the vertical stack structure of a second of the two of the memory array regions. lateral conductive contacts provide a conductive path between the first steps of the first staircase structure and the second steps of the second staircase structure. related microelectronic devices, memory devices, and electronic systems are also described.
Inventor(s): Hidenori Yamaguchi of Higashihiroshima (JP) for micron technology, inc., Katsumi Koge of Higashihiroshima (JP) for micron technology, inc., Junya Suzuki of Higashihiroshima (JP) for micron technology, inc., Hiroshi Ichikawa of Higashihiroshima (JP) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/50
Abstract: a semiconductor device includes: a substrate; a memory cell region over the substrate; a peripheral region over the substrate, the peripheral region being adjacent to the memory cell region; and a plurality of first and second word-lines extending across the memory cell region and the peripheral region; wherein the plurality of first word-lines and the plurality of second word-lines are arranged alternately with each other; and wherein the length of the first word-line in the peripheral region is longer than the length of the second word-line in the peripheral region.
Inventor(s): Luan C. Tran of Meridian ID (US) for micron technology, inc., Guangyu Huang of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B41/27, G11C5/06, H10B41/35, H10B41/60, H10B43/27, H10B43/35
CPC Code(s): H10B41/27
Abstract: a method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. the insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. structure independent of method is disclosed.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc., Nancy M. Lomeli of Boise ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/10, H01L21/311, H01L21/3115, H01L21/3213, H01L21/3215, H10B41/10, H10B41/27, H10B43/27
CPC Code(s): H10B43/10
Abstract: a memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. the intervening material in a lowest of the conductive tiers comprises intervenor material. bridges extend laterally-between the immediately-laterally-adjacent memory blocks. the bridges comprise bridging material that is of different composition from that of the intervenor material. the bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. other embodiments, including method, are disclosed.
Inventor(s): Yifen Liu of Meridian ID (US) for micron technology, inc., Yan Song of Singapore (SG) for micron technology, inc., Albert Fayrushin of Boise ID (US) for micron technology, inc., Naiming Liu of Boise ID (US) for micron technology, inc., Yingda Dong of Los Altos CA (US) for micron technology, inc., George Matamis of Eagle ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H01L23/522, H10B43/10, H10B43/35, H10B43/40
CPC Code(s): H10B43/27
Abstract: an electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. a charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. a height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. related methods and systems are also disclosed.
Micron Technology, Inc. patent applications on July 18th, 2024
- Micron Technology, Inc.
- G01K13/10
- G01K1/02
- G01K7/14
- CPC G01K13/10
- Micron technology, inc.
- G06F3/06
- G06F13/16
- G06F13/40
- G06F13/42
- G11C7/10
- G11C21/00
- CPC G06F3/0607
- CPC G06F3/061
- CPC G06F3/0655
- CPC G06F3/0656
- CPC G06F3/0659
- G06F1/04
- G06F1/3234
- G06F8/65
- CPC G06F8/65
- G06F9/30
- G06N3/063
- CPC G06F9/3001
- G06F9/448
- G06F13/12
- G06F13/28
- G06F13/38
- CPC G06F9/4498
- G06F11/10
- G06F11/07
- CPC G06F11/1068
- G06F11/14
- G06F1/28
- CPC G06F11/142
- G06F12/02
- CPC G06F12/0246
- G06F12/126
- CPC G06F12/126
- CPC G11C7/1039
- G11C11/406
- CPC G11C11/40626
- G11C11/408
- G11C11/4076
- G11C11/4096
- CPC G11C11/4085
- G11C11/4091
- H10B12/00
- G11C11/56
- CPC G11C11/4096
- G11C11/4099
- G11C11/4074
- CPC G11C11/4099
- G11C16/16
- G11C16/08
- G11C16/10
- CPC G11C16/16
- G11C27/00
- CPC G11C27/005
- G11C29/50
- CPC G11C29/50004
- H01J37/32
- CPC H01J37/32449
- H01L23/544
- CPC H01L23/544
- H01L23/00
- H01L23/31
- H01L23/58
- CPC H01L23/562
- H03M13/29
- H04L25/03
- CPC H03M13/2906
- H05K5/02
- H05K7/20
- CPC H05K5/026
- CPC H10B12/30
- CPC H10B12/50
- H10B41/27
- G11C5/06
- H10B41/35
- H10B41/60
- H10B43/27
- H10B43/35
- CPC H10B41/27
- H10B43/10
- H01L21/311
- H01L21/3115
- H01L21/3213
- H01L21/3215
- H10B41/10
- CPC H10B43/10
- H01L23/522
- H10B43/40
- CPC H10B43/27
