Micron Technology, Inc. patent applications on July 11th, 2024
Patent Applications by Micron Technology, Inc. on July 11th, 2024
Micron Technology, Inc.: 66 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (24), G06F11/10 (5), G06F11/07 (4), H01L25/065 (3), H01L25/00 (3) G06F3/0659 (8), G06F11/1068 (3), G06F3/0619 (3), G06F3/0653 (3), H10B99/00 (2)
With keywords such as: memory, device, data, read, controller, cells, command, based, material, and voltage in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Rajesh H. Kariya of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F1/26
CPC Code(s): G06F1/26
Abstract: methods, systems, and devices for power management and delivery for high bandwidth memory are described. a high bandwidth memory (hbm) device may include a power management integrated circuit (pmic) and a voltage regulator integrated within an interface die of the hbm system or included as a separate chip within the hbm system stack. accordingly, the hbm system may be supplied a higher voltage and may regulate the voltage to a desired power level, which may increase the total power available to the hbm system without increasing the quantity of microbumps. additionally, a ground voltage, a positive voltage, or both, may be supplied to the hbm device via a back interface of the hbm device, which may reduce the quantity of microbumps at a front interface. in some examples, a modified heatsink assembly may supply the ground voltage, the positive voltage, or both, to the hbm system.
Inventor(s): Venkata Kiran Kumar Matturi of Milpitas CA (US) for micron technology, inc., Sharath Chandra Ambula of Nizampet (IN) for micron technology, inc., Niraimathi N S of Hitech City (IN) for micron technology, inc.
IPC Code(s): G06F1/28, G06F1/10
CPC Code(s): G06F1/28
Abstract: information associated with a power consumption level of a set of components of a controller of a memory device is identified. a determination is made whether the information associated with the power consumption level satisfies one or more conditions. in response to the one or more conditions being satisfied, swallowing one or more clock pulses of a clock signal transmitted to at least one component of the set of components of the controller are swallowed.
20240231610. CLUSTER NAMESPACE FOR A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Gaurav SINHA of Oberscheißheim (DE) for micron technology, inc., Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0604
Abstract: implementations described herein relate to a cluster namespace for a memory device. in some implementations, a memory device may receive a cluster namespace instruction, from a host device, that instructs the memory device to create a cluster namespace using memory resources of the memory device that are spread across a plurality of namespaces of the memory device. the memory device may identify namespace storage information that indicates memory resources associated with a plurality of namespaces of the memory device. the memory device may create the cluster namespace based on creating a plurality of extents that respectively map sets of logical block address ranges from the plurality of namespaces to the cluster namespace.
Inventor(s): Tomoharu Tanaka of Yokohama (JP) for micron technology, inc., Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Dung V. Nguyen of San Jose CA (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Dave Ebsen of Minnetonka MN (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: a memory device includes an array of memory cells and a controller configured to access the array of memory cells. the controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. the controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.
Inventor(s): Kyungjin Kim of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive die selection for block family scan operations. the controller assigns a set of memory components to one or more groups of a plurality of groups based on respective storage characteristics of the set of memory components, each of the plurality of groups corresponding to different storage characteristics. the controller determines a maximum quantity of memory components to perform block family (bf) scan operations at an individual measurement period. the controller distributes the maximum quantity of memory components across the one or more groups to which the set of memory components are assigned and, at the individual measurement period, performs the bf scan operations on a portion of the set of memory components corresponding to the maximum quantity of memory components.
Inventor(s): Donald M. Morgan of Meridian ID (US) for micron technology, inc., Bryan David Kerstetter of Kuna ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F21/56
CPC Code(s): G06F3/0616
Abstract: a system for providing maximum row active time enforcement for memory devices is disclosed. a host device issues an activate command to activate a memory bank of a plurality of memory banks of a memory. the memory device activates the memory bank and determines whether a precharge command to close the first memory bank has been issued by the host device within a maximum threshold amount of time since issuance of the activate command. if the system determines that the precharge command has been issued by the host device within the threshold, the memory device closes the memory bank via the host-issued precharge command. if, however, the system determines that the precharge command has not been issued by the host device within the threshold, the memory device internally issues a precharge command to close the memory bank to reduce potential data loss and other harmful effects to the memory device.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Tomer Tzvi Eliash of Sunnyvale CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/1009
CPC Code(s): G06F3/0619
Abstract: a processing device, operatively coupled with a memory device, performs a first programming operation on a first set of cells associated with a first sub-block of a first die of the memory device, wherein each die of the memory device comprises a plurality of sub-blocks. the processing device identifies, based on a first predefined value, a second sub-block of a second die of the memory device on which to perform a second programming operation, wherein the first predefined value is a shift in an index value of the first sub-block of the first die of the memory device. the processing device further performs the second programming operation on a second set of cells associated with the second sub-block of the second die, wherein the second sub-block of the second die is associated with a different index value than the first sub-block of the first die.
Inventor(s): Gianluca Nicosia of Boise ID (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Niccolo Righetti of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a memory sub-system with a memory device having a plurality of cells, and the plurality of cells having a set of cells, and a processing device operatively coupled to the memory device, the processing device to perform operations of determining a level information associated with the set of cells, where the set of cells comprise a target cell associated with a read operation, identifying a read level offset for the target cell based on the level information, and performing the read operation in accordance with the read level offset.
Inventor(s): Murong Lang of San Jose CA (US) for micron technology, inc., Tingjun Xie of Milpitas CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: methods, apparatuses and systems related to managing deck-specific read levels are described. the apparatus may include a memory array having the memory cells organized into two or more decks. the apparatus can determine a delay between programming the decks. the apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.
20240231655. ADAPTIVE CONTROL FOR IN-MEMORY VERSIONING_simplified_abstract_(micron technology, inc.)
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc., Haojie Ye of Ann Arbor MI (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: disclosed in some examples are systems, devices, machine-readable mediums, and methods for customizing an in-memory versioning mode for each memory location according to a predicted access behavior to optimize memory device performance. usage data in a previous time period may be utilized along with policy rules to determine whether to configure a particular memory address as a zero copy or direct copy mode. for example, memory addresses that are read frequently may be configured as direct copy mode to reduce the read latency penalty. this improves the functioning of the memory system by reducing read latency for memory addresses that are frequently read but written to less frequently, and reduces write latency for memory locations that are frequently written to, but not read as frequently.
20240231660. READ SOURCE DETERMINATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Tom V. Geukens of Longmont CO (US) for micron technology, inc., Byron D. Harris of Mead CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: apparatuses and methods for read source determination are provided. one example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.
20240231666. EMPTY PAGE SCAN OPERATIONS ADJUSTMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Peng Zhang of Los Altos CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Christina Papagianni of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0644
Abstract: aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. the controller selects a portion of the set of memory components that is empty and ready to be programmed. the controller reads one or more signals from the selected portion of the set of memory components. the controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. the controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.
Inventor(s): Angelo Covello of Avezzano AQ (IT) for micron technology, inc., Claudia Ciaschi of Latina LT (IT) for micron technology, inc., Michele Incarnati of Avezzano (IT) for micron technology, inc., Tommaso Vali of Sezze LT (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/065
Abstract: a memory device includes a local memory to store operational data and comparison logic operatively coupled with the local memory. the comparison logic, upon initialization of the memory device, compares, to detect any errors in the operational data, one copy of a first copy pair with one copy of a second copy pair of the operational data, the first copy pair including a first copy and an inverted first copy and the second copy pair including a second copy and an inverted second copy of the operational data. the comparison logic further reports an error in response to detecting the first copy pair does not match the second copy pair.
Inventor(s): Kyungjin Kim of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to identify a center of valley (cov) of a set of read levels. the controller detects a read error associated with reading data from the set of memory components in accordance with an individual read level of a plurality of read levels and, in response to detecting the read error, generates a plurality of bins as a function of a plurality of check failure bit count values and one or more error count values corresponding to a set of read levels adjacent to the individual read level. the controller computes the cov for the individual read level based on a pair of read levels defined by a set of the plurality of bins and updates a read level used to read the data based on the computed cov.
Inventor(s): Eric N. Lee of San Jose CA (US) for micron technology, inc., Dheeraj Srinivasan of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: a memory system includes a ready busy pin coupled with a plurality of dice and a processing device coupled with the ready busy pin. the processing device is to perform controller operations including waiting to perform any status checks until after assertion of a pulse on a status indicator signal received from the ready busy pin; detecting the pulse being asserted is an extended pulse comprising at least a partial overlap of a first pulse asserted by a first die and a second pulse asserted by a second die of the plurality of dice; initiating a polling delay period in response to detecting assertion of the extended pulse, wherein the polling delay period is greater than a pulse width of the first pulse; and initiating a first status check of dice operations being performed by the plurality of dice in response to detecting expiration of the polling delay period.
Inventor(s): Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Devin M. Batutis of San Jose CA (US) for micron technology, inc., Xiangang Luo of Fremont CA (US) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Sampath Ratnam of Boise ID (US) for micron technology, inc., Shane Nowell of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: an amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. the block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. the first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.
Inventor(s): Haojie Ye of Ann Arbor MI (US) for micron technology, inc., David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: devices and techniques for continuous in-memory versioning are described herein. a memory subsystem includes a memory device configured to store a first data unit, a second data unit, and a third data unit, wherein the first, second, and third data units have a set of physical memory locations on the memory device, and metadata associated with the first, second, and third data units, the metadata including state information and a dirty commit timestamp; and a processing device, operatively coupled to the memory device, the processing device configured to: receive, from a host system, a first memory command associated with a logical memory address, the logical memory address mapped to the set of physical memory locations of the memory device; and in response to receiving the first memory command, perform a data operation on the first, second, or third data unit based on the state information and the dirty commit timestamp.
20240231685. COMMAND TIMER INTERRUPT_simplified_abstract_(micron technology, inc.)
Inventor(s): Chandrakanth Rapalli of Hyderabad (IN) for micron technology, inc., Yoav Weinberg of Toronto (CA) for micron technology, inc., Tal Sharifie of Lehavim (IL) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for command timer interrupt are described. in some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. for example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. if the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.
20240231693. WRITE OPERATIONS ON A NUMBER OF PLANES_simplified_abstract_(micron technology, inc.)
Inventor(s): Tom V. Geukens of Longmont CO (US) for micron technology, inc., John J. Kane of Westminster CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: apparatuses and methods for determining performing write operations on a number of planes are provided. one example apparatus can include a controller configured to associate a first number of blocks together, wherein each of the first number of blocks are each located on different planes, receive commands to write data to a first page on the number of first blocks, and write data to the first page of each of the first number of blocks during a first time period.
Inventor(s): Wenjun Wu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for read buffer allocation balance between multiple memory dies are described. a memory system may transfer multiple device commands to various command queues in which each queue is associated with a respective memory die of the memory system. the memory system may determine an order for execution of the commands based on amounts of a buffer currently allocated to each memory die, amounts of a buffer request for each command, or both. the memory system may process the commands of each queue based on the order for execution and allocate buffer to respective memory dies based on the processed commands. the memory system may perform the commands, deallocate respective portions of the buffer associated with the commands, and transfer more device commands to each command queue.
Inventor(s): Lei Pan of Shanghai (CN) for micron technology, inc., Minjian Wu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: exemplary methods, apparatuses, and systems include a retention latency manager for controlling memory access operations in computing systems based on latency of a set of data bits. the retention latency manager receives a set of data bits from a host. the retention latency manager writes a time stamp. the retention latency manager writes the set of data bits to a location in memory. the retention latency manager computes a time difference between a current time and the time stamp. the retention latency manager selects a set of trim settings using the time difference. the retention latency manager reads the set of data bits from the first location in memory using the set of trim settings.
Inventor(s): Wenjun Wu of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for systems and techniques for transfer of dirty data are described. a memory system may include a memory device including a first controller, and a second controller coupled with the memory device. the second controller may issue, to the first controller, a command to sense data stored at one or more planes of the memory device. in response, the data from the one or more planes may be transferred to an interface between the one or more planes and the second controller. the second controller may issue, to the first controller, a command to transfer one or more portions of the data to the second controller that includes a bitmap indicating the one or more portions of the data. in response, the one or more portions of the data may be transferred to the second controller via the interface in accordance with the bitmap.
20240231702. MULTIPLANE DATA TRANSFER COMMANDS_simplified_abstract_(micron technology, inc.)
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for multiplane data transfer commands are described. implementations may provide a modified transfer command to leverage a sequential nature of a read operation. for example, a memory system may determine to read data stored across a set of planes of a non-volatile memory device and a sequence of the planes may be known. the memory system may issue a transfer command to a controller of the non-volatile memory device that supports automatic switching from one plane to the next in transferring data from the set of planes to a controller of the memory system. as a result, one transfer command may be issued by the memory system controller to transfer the data from the set of planes, for example, rather than one transfer command per plane.
20240231703. MEMORY SUB-SYSTEM COMMAND FENCING_simplified_abstract_(micron technology, inc.)
Inventor(s): Dhawal Bavishi of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a method includes memory fencing in memory components of a memory sub-system and receiving a first number of commands and a second number of command for execution on a memory sub-system, receiving a memory fencing command associated with the first number of commands and the second number of commands, and executing at least one of the first number of commands before executing at least one of the second number of commands in response to receiving the memory fencing command. the method further includes executing the at least one of the first number of commands by moving data from a first location in the memory subsystem to a second location in the memory sub-system and executing the at least one of the second number of commands by reading data from the second location in the memory sub-system and sending the data to a host system.
20240231708. DYNAMIC RAIN FOR ZONED STORAGE SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F11/10
CPC Code(s): G06F3/0689
Abstract: aspects of the present disclosure configure a system component, such as memory sub-system controller, to dynamically generate redundant array of independent nodes (rain) parity information for zone-based memory allocations. the rain parity information is generated for a given zone or set of zones on the basis of whether the given zone or set of zones satisfy a zone completeness criterion. the zone completeness criterion can represent a specified size such that when a given zone reaches the specified size, the parity information for that zone is generated.
20240231831. VECTOR INDEX REGISTERS_simplified_abstract_(micron technology, inc.)
Inventor(s): Steven Jeffrey Wallach of Dallas TX (US) for micron technology, inc.
IPC Code(s): G06F9/38, G06F9/30, G06F9/345, G06F9/355, G06F15/80
CPC Code(s): G06F9/3824
Abstract: disclosed herein are vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors. it is known to use scalar index registers in vector processors to access multiple positions of vectors by changing the scalar index registers in vector operations. by using a vector indexing register for indexing positions of one or more operand vectors, the scalar index register can be replaced and at least the continual changing of the scalar index register can be avoided.
20240231951. SHADOW COMPUTATIONS IN BASE STATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Dmitri Yudanov of Sacramento CA (US) for micron technology, inc.
IPC Code(s): G06F9/50, G06N20/00, H04W88/08
CPC Code(s): G06F9/5083
Abstract: systems and methods for implementing shadow computations in base stations. the systems and methods can include a method including initiating, at a base station (such as a cellular base station), a shadow computation of a main computation executing for a mobile device. the main computation can include a computational task, and the shadow computation can be at least a part of or a derivative of the main computation. the method can also include executing, by the base station, the shadow computation.
Inventor(s): Naveen BOLISETTY of Hyderabad (IN) for micron technology, inc., Tingjun XIE of Milpitas CA (US) for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/076
Abstract: in some implementations, a memory device may detect a first read failure associated with a page type and a memory section of the memory device. the memory device may perform multiple read recovery operations in a first order defined by a first sequence of read recovery operations. the memory device may identify a read recovery operation that results in successful recovery from the first read failure. the memory device may reorder the first sequence of read recovery operations to generate a second sequence of read recovery operations that prioritizes the read recovery operation. the memory device may detect a second read failure associated with the page type and the memory section. the memory device may perform one or more read recovery operations to recover from the second read failure in a second order defined by the second sequence of read recovery operations.
Inventor(s): Pavana Prakash of Houston TX (US) for micron technology, inc., Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Febin Sunny of Folsom CA (US) for micron technology, inc., Saideep Tiku of Fort Collins CO (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/079
Abstract: the present disclosure includes apparatuses, methods, and systems for classifying an area as hazardous or non-hazardous based on an operation of a semiconductor device. in an example, an apparatus can include a memory configured to store a global operation model and a processor coupled to the memory wherein the processor is configured to receive test data and operating data from a semiconductor device based on operation of the semiconductor device in an area, run the global operation model on the test data and the operating data from the semiconductor device to generate output data, and classify the area as hazardous or non-hazardous based on the output data.
Inventor(s): Melissa I. URIBE of El Dorado Hills CA (US) for micron technology, inc., Aaron P. BOEHM of Boise ID (US) for micron technology, inc., Scott E. SCHAEFER of Boise ID (US) for micron technology, inc., Steffen BUCH of Taufkirchen (DE) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: implementations described herein relate to command address fault detection using a parity bit. a memory device may receive, from a host device via a command address (ca) bus and during a unit interval, a set of ca bits associated with a ca word. the memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of ca bits and a parity generation process. the memory device may generate a second parity bit based on the set of ca bits and the parity generation process. the memory device may compare the first parity bit and the second parity bit. the memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.
20240232011. TECHNIQUES FOR IMPROVED DATA TRANSFER_simplified_abstract_(micron technology, inc.)
Inventor(s): Jameer Mulani of Bangalore (IN) for micron technology, inc., Amiya Banerjee of Bangalore (IN) for micron technology, inc., Nitul Gohain of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F11/10, G06F13/16
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for techniques for improved data transfer are described. as part of a data transfer operation from a first set of memory cells of a memory device to a second set of memory cells of the memory device, a memory controller of may read a set of data units from the first set of memory cells. the memory device may transmit the set of data units to the memory controller. the memory controller may decode the set of data units, and, in some cases, may generate one or more corrected data units. the memory controller may then generate parity information for the set of data units, and may encode and write the parity information, along with any corrected data units, to the second set of memory cells of the memory device without transferring the uncorrected data units.
Inventor(s): Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Niccolo’ Righetti of Boise ID (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Mark A. Helm of Santa Cruz CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Ugo Russo of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07, G06F11/14
CPC Code(s): G06F11/1068
Abstract: a method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.
20240232014. COMMAND AND DATA PATH ERROR PROTECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Chandrakanth Rapalli of Hyderabad (IN) for micron technology, inc., Yoav Weinberg of Toronto (CA) for micron technology, inc., Tal Sharifie of Lehavim (IL) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/108
Abstract: methods, systems, and devices for command and data path error protection are described. in some examples, a memory system may receive data units from a host device. the data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. a first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. the protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. the second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
Inventor(s): Jaeil Kim of Suwanee GA (US) for micron technology, inc., Simon J. Lovett of Nampa ID (US) for micron technology, inc.
IPC Code(s): G06F11/16, G06F3/06
CPC Code(s): G06F11/1612
Abstract: a memory device can include a bank of memory cells. the bank of memory cells can include multiple groups of columns of memory cells. the memory device can include controller circuitry to provide information pertaining to a column repair redundancy swap for repairing a selected group of the plurality of groups at row address strobe (ras) time. upon detection of an error condition in at least one group of columns of memory cells, the controller circuitry can implement the column repair redundancy swap on the corresponding group.
Inventor(s): Christophe Vincent Antoine Laurent of Agrate Brianza (MB) (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc.
IPC Code(s): G06F12/0891
CPC Code(s): G06F12/0891
Abstract: systems, methods, and apparatus for a memory device that stores a scrub list in a cache used to reduce data traffic to and from a memory array. in one approach, the cache merges the scrub list with cache data. data in the scrub list can be identified and distinguished from the cache data by adding a one-bit scrub flag to each data entry in the merged cache. in this merged approach, the cache data shares the same memory as the scrub list. read data that has an error is saved temporarily in this merged cache until the correct value for the data is written back into the memory array.
Inventor(s): Praveen Gurrala of Boise ID (US) for micron technology, inc., Aniket Bhandare of Boise ID (US) for micron technology, inc., John Todd Elson of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/16, G06F13/28
CPC Code(s): G06F13/1689
Abstract: methods, systems, and devices for an adjustable periodicity of burst access operations are described. generally, the described techniques relate to mitigating electromagnetic emissions associated with issuing access commands by adjusting a periodicity according to which the access commands are issued. for example, a first set of one or more commands to perform a first type of access operation may be issued according to a first time delay and a second set of one or more commands to perform the first type of access operation may be issued according to a second time delay, which may be different or the same as the first time delay. the second time delay may be (e.g., randomly) determined based on a value that is selected by a device that issues the commands, the value associated with modifying a periodicity according to which commands to perform the first type of access operation are issued.
20240232111. NETWORK CREDIT RETURN MECHANISMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Tony Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F13/364, G06F30/3953
CPC Code(s): G06F13/364
Abstract: implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. a wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. a source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. in some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane ) for credit return data. in other example embodiments, the receiving device uses a bitwise-or to combine the credit return data of all received flits in a single cycle.
20240232559. DYNAMIC MACHINE READABLE CODE_simplified_abstract_(micron technology, inc.)
Inventor(s): Yashvi SINGH of Boise ID (US) for micron technology, inc., Diana Calhoun MAJERUS of Boise ID (US) for micron technology, inc., Kristina Lauren MING of Boise ID (US) for micron technology, inc., Maria Pat F. CHAVARRIA of Boise ID (US) for micron technology, inc.
IPC Code(s): G06K19/06, H04L9/08
CPC Code(s): G06K19/06037
Abstract: in some implementations, a server device may generate a machine readable code that conveys first information associated with a first entity. the server device may provide an indication of the machine readable code that indicates the first information. the server device may obtain a request to update information conveyed by the machine readable code, the request including an indication of at least one of the machine readable code or the first information. the server device may modify the first information conveyed by the machine readable code to second information, based on the request and based on authenticating the request, wherein the second information includes a first secure information layer indicating the first information and a second secure information layer indicating information indicated by the request. the server device may provide, to the communication device, an indication of at least one of the machine readable code or the second information.
Inventor(s): Dmitri Yudanov of Cordova CA (US) for micron technology, inc., Sean S. Eilert of Penryn CA (US) for micron technology, inc., Hernan A. Castro of Shingle Springs CA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc.
IPC Code(s): G06N3/063, G06F12/06, G06N3/04
CPC Code(s): G06N3/063
Abstract: methods, apparatuses, and systems for in- or near-memory processing are described. spiking events in a spiking neural network may be processed via a memory system. a memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (snn), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.
Inventor(s): Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc., Lawrence D. Smith of Boise ID (US) for micron technology, inc., James S. Rehmeyer of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/22, G11C7/10, G11C17/16
CPC Code(s): G11C7/222
Abstract: fuses can store different delay states to cause execution of a command to be staggered for different memory dies of a memory package. fuse arrays can be included in the memory package and programmed to cause execution of a command to be delayed by different amounts for different dies. the fuse arrays can be fabricated and then programmed to cause different delays for different dies.
Inventor(s): Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Kamal M. Karda of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/402, G11C11/409, H01L29/22, H01L29/78, H10B99/00
CPC Code(s): G11C11/4023
Abstract: some embodiments include apparatuses and methods operating the apparatuses. one of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. the memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.
Inventor(s): BAOKANG WANG of Sagamihara (JP) for micron technology, inc., TAKUYA MIYAGI of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C11/4076
CPC Code(s): G11C11/4076
Abstract: apparatuses, systems, and methods for data timing alignment with fast alignment mode. a stacked memory device includes an interface die and a number of core die. the interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. the delay codes are adjusted based on a measured phase difference along a replica path. in a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. if one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. this may allow for correction of systemic errors such as voltage drift.
Inventor(s): Federica Paolini of Francavilla al Mare (IT) for micron technology, inc., Violante Moschiano of Avezzano (IT) for micron technology, inc., Marco Domenico Tiburzi of Avezzano (IT) for micron technology, inc., Leo Raimondo of Avezzano (IT) for micron technology, inc., Filippo Bruno of Padua (IT) for micron technology, inc., Shigekazu Yamada of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C16/08, G11C16/04, G11C16/26, G11C16/30
CPC Code(s): G11C16/08
Abstract: a system includes a memory device having one or more planes and a first set of voltage regulators coupled to each plane of the one or more planes, where the first set of voltage regulators is shared by the one or more planes. the system includes a second set of voltage regulators coupled to a plane of the one or more planes configured to supply a respective voltage to one or more conductive lines responsive to a memory access operation request. the system includes a switch, at the plane of the one or more planes, coupled with a first voltage regulator of the first set of voltage regulators, a second voltage regulator of the second set of voltage regulators, and a first conductive line, the switch configured to selectively couple the second voltage regulator of the second set of voltage regulators to the first conductive line.
Inventor(s): Matteo Impala' of Milano (IT) for micron technology, inc., Mattia Robustelli of Milano (IT) for micron technology, inc., Innocenzo Tortorelli of Milano (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G11C16/102
Abstract: methods, apparatuses and systems related to reading data from memory cells configured to store more than one bit are described. the apparatus may be configured to determine a polarity data associated with reading data stored at a target location. in reading the data stored at the target location, the apparatus may apply one or more voltage levels across different polarities according to the determined polarity data.
20240233836. POWER MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Liang Yu of Boise ID (US) for micron technology, inc., Jeremy Binfet of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/30, G11C16/04, G11C16/08, H01L23/00, H01L25/065
CPC Code(s): G11C16/30
Abstract: a memory device might include registers configured to store expected peak current magnitudes corresponding to a plurality of memory devices containing the memory device, and a controller configured to cause the memory device to determine whether to initiate a next phase of an access operation in response to at least a first sum of an expected peak current magnitude for the next phase of the access operation in a selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a first current demand budget, and a second sum of the expected peak current magnitude for the next phase of the access operation in the selected operating mode and the expected peak current magnitudes of each of the registers other than a respective register of the memory device relative to a second, lower, current demand budget.
Inventor(s): Chiara Cerafogli of Boise ID (US) for micron technology, inc., Kenneth William Marr of Boise ID (US) for micron technology, inc., Marco Domenico Tiburzi of Avezzano (IT) for micron technology, inc., Matthew Joseph Iriondo of Boise ID (US) for micron technology, inc., Warren Lee Boyer of Boise ID (US) for micron technology, inc., Brian James Soderling of Eagle ID (US) for micron technology, inc., James Eric Davis of Meridian ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/32
CPC Code(s): G11C16/32
Abstract: a digital thermometer includes a first oscillator to generate a first clock signal, wherein a period of the first clock signal remains constant in view of changes in a temperature of the apparatus and a first counter coupled to the first oscillator, the first counter to count a fixed number of cycles of the first clock signal associated with a measurement period. the digital thermometer further includes a second oscillator to generate a second clock signal, wherein a period of the second clock signal varies with changes in the temperature and a second counter coupled to the second oscillator, the second counter to generate an output representing a count of a number of cycles of the second clock signal that occur during the measurement period. in addition, the digital thermometer includes calibration circuitry coupled to the second counter, the calibration circuitry to calibrate the output of the second counter to generate a value representing the temperature of the apparatus.
20240233842. MANAGING TRAP-UP IN A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Pitamber Shukla of Boise ID (US) for micron technology, inc., Chi Ming W. Chu of Boise ID (US) for micron technology, inc., Avinash Rajagiri of Boise ID (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Kenneth W. Marr of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/28
CPC Code(s): G11C16/3495
Abstract: methods, systems, and devices for managing trap-up in a memory system are described. a request to erase a block of a memory device may be received. based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (p/e) cycle may be determined. the first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior p/e cycles performed on the block. the block of memory may be managed based on whether the p/e cycling with the debiasing operation having the voltage level is performed.
Inventor(s): Zhongguang Xu of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34
CPC Code(s): G11C16/3495
Abstract: a system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. the processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. the processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. the processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.
Inventor(s): Justin Eno of Boise ID (US) for micron technology, inc., Sean S. Eilert of Boise ID (US) for micron technology, inc., Ameen D. Akel of Boise ID (US) for micron technology, inc., Kenneth M. Curewitz of Boise ID (US) for micron technology, inc.
IPC Code(s): G16B30/10, G06F16/903
CPC Code(s): G16B30/10
Abstract: associative processing memory (apm) may be used to align reads to a reference sequence. the apm may store shifted permutations and/or other permutations of the reference sequence. a read may be compared to some or all of the permutations of the reference sequence and the apm may provide an output for each comparison. in some examples, the apm may compare the read to many permutations of the reference sequence to the read in parallel. inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.
Inventor(s): Justin Eno of Boise ID (US) for micron technology, inc., Sean S. Eilert of Boise ID (US) for micron technology, inc., Ameen D. Akel of Boise ID (US) for micron technology, inc., Kenneth M. Curewitz of Boise ID (US) for micron technology, inc.
IPC Code(s): G16B30/10, G16B50/00
CPC Code(s): G16B30/10
Abstract: associative processing memory (apm) may be used to align reads to a reference sequence. the apm may store shifted permutations and/or other permutations of the reference sequence. a read may be compared to some or all of the permutations of the reference sequence and the apm may provide an output for each comparison. in some examples, the apm may compare the read to many permutations of the reference sequence to the read in parallel. inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.
Inventor(s): Michael A. Smith of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Vladimir Mikhalev of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L21/8238, H01L27/092, H01L29/66, H01L29/78, H10B10/00
CPC Code(s): H01L23/528
Abstract: a memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. the memory device includes a memory subsystem having first and second memory circuits. each first memory circuit can be disposed laterally adjacent to a second memory circuit. each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc.
IPC Code(s): H01L23/535, H01F17/00, H01L23/48, H01L23/522
CPC Code(s): H01L23/535
Abstract: a semiconductor device comprising a substrate is provided. the device further comprises a through-substrate via (tsv) extending into the substrate, and a substantially helical conductor disposed around the tsv. the substantially helical conductor can be configured to generate a magnetic field in the tsv in response to a current passing through the helical conductor. more than one tsv can be included, and/or more than one substantially helical conductor can be provided.
Inventor(s): Shiro Uchiyama of Tokyo (JP) for micron technology, inc.
IPC Code(s): H01L25/065, H01L21/50, H01L23/544, H01L25/00
CPC Code(s): H01L25/0657
Abstract: semiconductor device assemblies having features that are used to align semiconductor dies, and associated systems and methods, are disclose herein. in some embodiments, a semiconductor device assembly includes substrate that has a top surface and an alignment structure at the top surface. a first die is disposed over the top surface of the substrate, and the first die has a first channel that extends between a top side and a bottom side of the first die. the first channel is vertically aligned with and exposes the alignment structure at the top surface of the substrate.
Inventor(s): Seng Kim Dalson Ye of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/16, H01L23/498
CPC Code(s): H01L25/16
Abstract: a microelectronic device package includes a stack of semiconductor dies positioned over a substrate. the microelectronic device package further includes an interposer structure coupled to the stack of semiconductor dies. the microelectronic device package further includes an electronic component directly coupled to the interposer structure and electrically coupled to the substrate through an electrical connection between the interposer structure and the substrate.
Inventor(s): Seng Kim Dalson Ye of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/18, H01L21/48, H01L23/498, H01L25/00, H10B80/00
CPC Code(s): H01L25/18
Abstract: a microelectronic device package includes a microelectronic device coupled to a substrate. the microelectronic device package further includes a stack of semiconductor dies positioned over the microelectronic device. the microelectronic device package also includes an interposer positioned between the microelectronic device and the stack of semiconductor dies. the interposer includes a conductive structure electrically connecting the microelectronic device and a ground circuit of the substrate. the interposer further includes an insulative structure positioned between the conductive structure and the stack of semiconductor dies.
Inventor(s): Sanket S. Kelkar of Sunnyvale CA (US) for micron technology, inc., Michael Mutch of Chardon OH (US) for micron technology, inc., Luca Fumagalli of Rio Rancho NM (US) for micron technology, inc., Hisham Abdussamad Abbas of Meridian ID (US) for micron technology, inc., Brenda D. Kraus of Boise ID (US) for micron technology, inc., Dojun Kim of Boise ID (US) for micron technology, inc., Christopher W. Petz of Boise CA (US) for micron technology, inc., Darwin Franseda Fan of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L49/02, H01G4/008, H01G4/12, H01L27/108
CPC Code(s): H01L28/75
Abstract: a microelectronic device comprises an access device comprising a source region and a drain region spaced from the source region, an insulative material vertically adjacent to the access device, and a capacitor within the insulative material and in electrical communication with the access device. the capacitor comprises a material comprising silicon oxynitride or titanium silicon nitride over surfaces of the insulative material, a first electrode comprising titanium nitride on the material, a dielectric material over the first electrode, and a second electrode on the dielectric material. related methods of forming the microelectronic device and an electronic system including the microelectronic devices are also described.
Inventor(s): Martin F. Schubert of Boise ID (US) for micron technology, inc., Vladimir Odnoblyudov of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L33/50, H01L33/32, H01L33/46
CPC Code(s): H01L33/50
Abstract: solid state transducer (“sst”) devices with selective wavelength reflectors and associated systems and methods are disclosed herein. in several embodiments, for example, an sst device can include a first emitter configured to emit emissions having a first wavelength and a second emitter configured to emit emissions having a second wavelength different from the first wavelength. the first and second emitters can be sst structures and/or converter materials. the sst device can further include a selective wavelength reflector between the first and second emitters. the selective wavelength reflector can be configured to at least substantially transmit emissions having the first wavelength and at least substantially reflect emissions having the second wavelength.
Inventor(s): Chandrakanth Rapalli of Hyderabad (IN) for micron technology, inc., Yoav Weinberg of Toronto (CA) for micron technology, inc., Tal Sharifie of Lehavim (IL) for micron technology, inc.
IPC Code(s): H03M13/09, H03M13/00
CPC Code(s): H03M13/095
Abstract: methods, systems, and devices for error protection for managed memory devices are described. in some examples, a memory system may receive data units from a host device. the data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. a first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. the protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. the second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.
Inventor(s): Jordan D. Greenlee of Nampa ID (US) for micron technology, inc., Andrea Gotti of Boise ID (US) for micron technology, inc., David McShannon of Meridian ID (US) for micron technology, inc., Silvia Borsari of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C5/06
CPC Code(s): H10B12/31
Abstract: a method used in forming an array of capacitors comprises forming horizontally-spaced openings into sacrificial material and through insulative material that is between a top and bottom of the sacrificial material. the insulative material at least predominately comprises at least one of a silicon nitride, a silicon boronitride, and a silicon carbonitride. the insulative material with horizontally-spaced openings there-through comprises an insulative horizontal lattice. an insulative lining is deposited within the horizontally-spaced openings and directly above the sacrificial material. the insulative lining at least predominately comprises at least one of a silicon oxide and a silicon oxynitride. during the depositing, the insulative lining is intermittently exposed to a nitrogen-containing plasma. first capacitor electrodes that are individually within individual of the horizontally-spaced openings are formed laterally over the insulative lining that is in the horizontally-spaced openings. the sacrificial material is removed and a capacitor insulator is formed over the first capacitor electrodes and the insulative horizontal lattice. second-capacitor-electrode material is formed over the capacitor insulator. structure independent of method is disclosed.
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc., John D. Hopkins of Meridian ID (US) for micron technology, inc., Matthew J. King of Boise ID (US) for micron technology, inc., Roger W. Lindsay of Boise ID (US) for micron technology, inc., Kevin Y. Titus of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H01L23/522, H10B41/27
CPC Code(s): H10B43/27
Abstract: a microelectronic device includes a pair of stack structures. the pair comprises a lower stack structure and an upper stack structure overlying the lower stack structure. the lower stack structure and the upper stack structure each comprise a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. a source region is vertically interposed between the lower stack structure and the upper stack structure. a first array of pillars extends through the upper stack structure, from proximate the source region toward a first drain region above the upper stack structure. a second array of pillars extend through the lower stack structure, from proximate the source region toward a second drain region below the lower stack structure. additional microelectronic devices are also disclosed, as are related methods and electronic systems.
Inventor(s): Paolo Fantini of Vimercate (MB) (IT) for micron technology, inc., Corrado Villa of Sovico (MB) (IT) for micron technology, inc., Stefan Frederik Schippers of Peschiera del Garda (VR) (IT) for micron technology, inc., Efrem Bolandrina of Fiorano al Serio (BG) (IT) for micron technology, inc.
IPC Code(s): H10B63/00, G11C13/00
CPC Code(s): H10B63/34
Abstract: the present disclosure provides a memory device and accessing/de-selecting methods thereof. the memory device comprises a memory layer including a vertical three-dimensional (3d) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (tfts) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a tft is configured for each pillar.
20240237360. ARCHITECTURE FOR MULTIDECK MEMORY ARRAYS_simplified_abstract_(micron technology, inc.)
Inventor(s): Riccardo Muzzetto of Arcore (MB) (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc., Umberto di Vincenzo of Capriate San Gervasio (BG) (IT) for micron technology, inc.
IPC Code(s): H10B63/00, G11C13/00, H10N70/20
CPC Code(s): H10B63/84
Abstract: an array of memory cells in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. the connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels.
Inventor(s): James Brian Johnson of Boise ID (US) for micron technology, inc., Brent Keeth of Boise ID (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Amy Rae Griffin of Boise ID (US) for micron technology, inc., Eiichi Nakano of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B80/00, H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: methods, systems, and devices for modular die configurations for multi-channel memory are described. a semiconductor component (e.g., a semiconductor wafer) may be configured with multiple rows and multiple columns of memory arrays, and associated channels. a row of memory arrays may be associated with a contact region extending along the row direction. the semiconductor component may also include control regions extending along the column direction between at least some of the columns of memory arrays. each control region may include control circuitry for operating memory arrays on one or both sides of the control region. the channels and memory arrays of the semiconductor wafer may be grouped into one or more independently-operable memory dies, with each memory die having at least a portion of a control region and at least a portion of a contact region for operating the memory arrays of the memory die.
Inventor(s): Hernan A. Castro of Shingle Springs CA (US) for micron technology, inc., Stephen W. Russell of Boise ID (US) for micron technology, inc., Stephen H. Tang of Fremont CA (US) for micron technology, inc.
IPC Code(s): H10B99/00, G11C8/10, G11C8/12, H01L21/027, H01L21/311, H01L29/40, H01L29/417, H01L29/423, H01L29/66, H01L29/786, H10B53/20, H10B53/40, H10B63/00
CPC Code(s): H10B99/00
Abstract: methods and apparatuses for thin film transistors and related fabrication techniques are described. the thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. the fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.
Inventor(s): Paolo Fantini of Vimercate (IT) for micron technology, inc., Lorenzo Fratin of Buccinasco (IT) for micron technology, inc., Paolo Tessariol of Arcore (IT) for micron technology, inc.
IPC Code(s): H10B99/00, H01L21/768
CPC Code(s): H10B99/00
Abstract: a method for manufacturing a 3d vertical array of memory cells is disclosed. the method comprises: forming on a substrate a stack of dielectric material layers comprising first and second dielectric material layers alternated to each other; forming holes through the stack of dielectric material layers, said holes exposing the substrate; selectively removing the second material layers through said holes to form cavities between adjacent first dielectric material layers; filling said cavities with a conductive material through said holes to form corresponding conductive material layers; forming first memory cell access lines from said conductive material layers; carrying out a conformal deposition of a chalcogenide material through said holes; forming memory cell storage elements from said deposed chalcogenide material; filling said holes with conductive material to form corresponding second memory cell access lines.
Inventor(s): Jun Liu of Boise ID (US) for micron technology, inc., Gurtej Sandhu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10N50/10, G11C11/16, H10N50/01, H10N50/80, H10N50/85
CPC Code(s): H10N50/10
Abstract: techniques for reducing damage in memory cells are provided. memory cell structures are typically formed using dry etch and/or planarization processes which damage certain regions of the memory cell structure. in one or more embodiments, certain regions of the cell structure may be sensitive to damage. for example, the free magnetic region in magnetic memory cell structures may be susceptible to demagnetization. such regions may be substantially confined by barrier materials during the formation of the memory cell structure, such that the edges of such regions are protected from damaging processes. furthermore, in some embodiments, a memory cell structure is formed and confined within a recess in dielectric material.
Micron Technology, Inc. patent applications on July 11th, 2024
- Micron Technology, Inc.
- G06F1/26
- CPC G06F1/26
- Micron technology, inc.
- G06F1/28
- G06F1/10
- CPC G06F1/28
- G06F3/06
- CPC G06F3/0604
- CPC G06F3/0608
- CPC G06F3/0613
- G06F21/56
- CPC G06F3/0616
- G06F12/1009
- CPC G06F3/0619
- CPC G06F3/0632
- CPC G06F3/064
- CPC G06F3/0644
- CPC G06F3/065
- CPC G06F3/0653
- CPC G06F3/0659
- G06F11/10
- CPC G06F3/0689
- G06F9/38
- G06F9/30
- G06F9/345
- G06F9/355
- G06F15/80
- CPC G06F9/3824
- G06F9/50
- G06N20/00
- H04W88/08
- CPC G06F9/5083
- G06F11/07
- CPC G06F11/076
- CPC G06F11/079
- CPC G06F11/1068
- G06F13/16
- G06F11/14
- CPC G06F11/108
- G06F11/16
- CPC G06F11/1612
- G06F12/0891
- CPC G06F12/0891
- G06F13/28
- CPC G06F13/1689
- G06F13/364
- G06F30/3953
- CPC G06F13/364
- G06K19/06
- H04L9/08
- CPC G06K19/06037
- G06N3/063
- G06F12/06
- G06N3/04
- CPC G06N3/063
- G11C7/22
- G11C7/10
- G11C17/16
- CPC G11C7/222
- G11C11/402
- G11C11/409
- H01L29/22
- H01L29/78
- H10B99/00
- CPC G11C11/4023
- G11C11/4076
- CPC G11C11/4076
- G11C16/08
- G11C16/04
- G11C16/26
- G11C16/30
- CPC G11C16/08
- G11C16/10
- G11C16/34
- CPC G11C16/102
- H01L23/00
- H01L25/065
- CPC G11C16/30
- G11C16/32
- CPC G11C16/32
- G11C16/28
- CPC G11C16/3495
- G16B30/10
- G06F16/903
- CPC G16B30/10
- G16B50/00
- H01L23/528
- H01L21/8238
- H01L27/092
- H01L29/66
- H10B10/00
- CPC H01L23/528
- H01L23/535
- H01F17/00
- H01L23/48
- H01L23/522
- CPC H01L23/535
- H01L21/50
- H01L23/544
- H01L25/00
- CPC H01L25/0657
- H01L25/16
- H01L23/498
- CPC H01L25/16
- H01L25/18
- H01L21/48
- H10B80/00
- CPC H01L25/18
- H01L49/02
- H01G4/008
- H01G4/12
- H01L27/108
- CPC H01L28/75
- H01L33/50
- H01L33/32
- H01L33/46
- CPC H01L33/50
- H03M13/09
- H03M13/00
- CPC H03M13/095
- H10B12/00
- G11C5/06
- CPC H10B12/31
- H10B43/27
- H10B41/27
- CPC H10B43/27
- H10B63/00
- G11C13/00
- CPC H10B63/34
- H10N70/20
- CPC H10B63/84
- CPC H10B80/00
- G11C8/10
- G11C8/12
- H01L21/027
- H01L21/311
- H01L29/40
- H01L29/417
- H01L29/423
- H01L29/786
- H10B53/20
- H10B53/40
- CPC H10B99/00
- H01L21/768
- H10N50/10
- G11C11/16
- H10N50/01
- H10N50/80
- H10N50/85
- CPC H10N50/10
