Micron Technology, Inc. patent applications on February 29th, 2024
Patent Applications by Micron Technology, Inc. on February 29th, 2024
Micron Technology, Inc.: 242 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (51), G06F3/0679 (38), H01L23/00 (28), H01L27/11582 (27), H01L27/11556 (24)
With keywords such as: memory, device, data, material, semiconductor, include, cells, die, read, and conductive in patent application abstracts.
See the following report for Micron Technology, Inc. patent applications published on February 29th, 2024:
Micron Technology, Inc. patent applications on February 29th, 2024
Patent Applications by Micron Technology, Inc.
Inventor(s): Theodore G. DOROS of Fairfax VA (US) for micron technology, inc.
IPC Code(s): G01N21/88, G06T7/00
Abstract: in some implementations, a test device may initiate a set of measurements by a set of sensors of the test device and of a device under test (dut), wherein the dut is a memory device. the test device may obtain the set of measurements of the dut from the set of sensors based on initiating the set of measurements. the test device may analyze the set of measurements of the dut, using a first model, to identify one or more defects present with the dut. the test device may determine, using a second model, that the one or more defects present with the dut satisfy a failure threshold. the test device may provide, based on the failure threshold being satisfied for the dut, an output indicating that the failure threshold is satisfied for the dut.
Inventor(s): Suresh Reddy Yarragunta of Bangalore (IN) for micron technology, inc., Deepu Narasimiah Subhash of Yeshwanthpu (IN) for micron technology, inc., Ramesh Nallavelli of Sangareddy (IN) for micron technology, inc.
IPC Code(s): G05D23/19, G06F1/20, G06F12/02
Abstract: some memory sub-systems are operated in high temperature and low airflow environments. as a safeguard, thermal throttling may limit throughput on a memory sub-system when a predetermined temperature is reached or exceeded. improving heat dissipation increases the amount of time a memory sub-system can operate without initiating thermal throttling. adding a phase-change material (pcm) with a melting temperature above the ambient temperature but below the thermal throttling temperature to a memory sub-system increases the amount of heat the memory sub-system can generate before the temperature reaches the thermal throttling temperature. thermally coupling components with a heat spreading sheet causes the temperature of the components to vary less than when the components transfer heat by air. thus, a component that generates less heat may be used to absorb heat generated by another component, increasing the amount of time before any component reaches the thermal throttling temperature.
20240069589.MEMORY DEVICE CLOCK MAPPING_simplified_abstract_(micron technology, inc.)
Inventor(s): Kallol Mazumder of Dallas TX (US) for micron technology, inc., Navya Sri Sreeram of McKinney TX (US) for micron technology, inc., Scott E. Smith of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F1/08, G06F1/10
Abstract: an example memory apparatus includes clock circuitry. the clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. the apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. the apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. the processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.
20240069721.MEMORY WITH SWITCHABLE CHANNELS_simplified_abstract_(micron technology, inc.)
Inventor(s): Sundararajan Sankaranarayanan of Fremont CA (US) for micron technology, inc., Chulbum Kim of San Jose CA (US) for micron technology, inc., Xiangyu Tang of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: memory with switchable channels is disclosed herein. in one embodiment, a system comprises a controller, a plurality of memory dies, and a switch matrix. the switch matrix is coupled to the controller via two or more controller-side channels, and to the plurality of memory dies via a set of memory-side channels. the switch matrix is configured to selectively couple each controller-side channel of the two or more controller-side channels to each memory-side channel of the set of memory-side channels to provide dynamically configurable connections between the controller and one or more memory dies of the plurality of memory dies.
20240069726.MEMORY DEVICE LOG DATA STORAGE_simplified_abstract_(micron technology, inc.)
Inventor(s): Scheheresade VIRANI of Frisco TX (US) for micron technology, inc., Jeffrey Lee MUNSIL of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: implementations described herein relate to memory device log data storage. in some implementations, a memory device may store a first data stream associated with a first type of log data in a circular buffer. the memory device may store a second data stream associated with a second type of log data in another memory location. the memory device may detect an event included in the second data stream that is associated with an attribute level that satisfies a threshold. the memory device may write data stored in the circular buffer after a time at which the event is detected to a non-volatile memory based on the attribute level satisfying the threshold, wherein the data stored in the circular buffer is stored in the non-volatile memory in connection with data associated with the event.
Inventor(s): Brian Toronyi of Boulder CO (US) for micron technology, inc., Scheheresade Virani of Frisco TX (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/1009
Abstract: an example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. the processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.
Inventor(s): Sriteja Yamparala of Boise ID (US) for micron technology, inc., Tawalin Opastrakoon of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block, receiving a request to write data subsequent to erasing the candidate memory blocks, and, responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks. the block characteristics of the candidate memory block can include a program erase count and/or a temperature of the candidate memory block.
Inventor(s): Raja V.S. Halaharivi of Gilroy CA (US) for micron technology, inc., Prateek Sharma of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system includes a memory device, a first interface port and a second interface port operatively coupled with the memory device, and a processing device, operatively coupled with the memory device, to perform operations including: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message; and allocating, by the processing device, one or more resources to the first interface port according to the configuration setting.
20240069733.MULTIPLE MEMORY BLOCK ERASE OPERATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Caixia Yang of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block and a second set of memory cells of a second memory block of a memory device. one or more erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. a first erase verify sub-operation of the erase operation is caused to be performed to verify the first memory block is erased and a second erase verify sub-operation of the erase operation is caused to be performed to verify the second memory block is erased.
Inventor(s): Kyungjin Kim of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: an example method of performing read operation with respect to a memory device comprises: receiving a request to perform a read operation with respect to a memory page of a memory device; identifying a block family associated with a block comprising the memory page; determining a block family-based read voltage level associated with the block family; performing, using the block family-based read voltage level, a read operation with respect to the memory page; determining, by performing an error correction operation with respect to the memory page, a new read voltage level associated with the block family; and associating, by a last successful read voltage level memory data structure, the new read voltage level as a last the successful read voltage level with the block family.
20240069735.MEMORY BLOCK ERASE PROTOCOL_simplified_abstract_(micron technology, inc.)
Inventor(s): Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Deping He of Boise ID (US) for micron technology, inc., Ting Luo of Santa Clara CA (US) for micron technology, inc., Guang Hu of Mountain View CA (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: described are systems and methods related to a memory block erase protocol. an example system includes a memory device having a memory array including a plurality of memory cells. the system further includes a processing device coupled to the memory device. the processing device is to determine a value of a metric associated with the memory array. responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. the processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. the processing device is further to receive a programming command directed to the first set of memory cells. the processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.
Inventor(s): Chulbum Kim of San Jose CA (US) for micron technology, inc., Sundararajan Sankaranarayanan of Fremont CA (US) for micron technology, inc., Xiangyu Tang of Mountain View CA (US) for micron technology, inc., Dustin J. Carter of Placerville CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
Abstract: an input/output (i/o) write request directed at memory devices is received by a processing device. the write request includes a data object. the memory devices include groups of memory cells corresponding to sequential logical addresses. the data object is appended to a compound data object associated with one of the memory devices. the compound data object is associated with the groups of memory cells. a first group of memory cells is in the not-full state, and one or more subsequent, in an order corresponding to the sequential logical addresses, groups of memory cells is identified as a free group of memory cells. the compound data object is caused to be written to the groups of memory cells, resulting in the full state of the first group of memory cells and resulting in the not-full state of at least one of the one or more subsequent groups of memory.
20240069741.DYNAMIC WEAR LEVELING TECHNIQUES_simplified_abstract_(micron technology, inc.)
Inventor(s): Luigi Esposito of Piano di Sorrento (NA) (IT) for micron technology, inc., Paolo Papa of Grumo Nevano (NA) (IT) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
Abstract: methods, systems, and devices for dynamic wear leveling techniques are described. a memory system may determine a type of data associated with data to be written to a block of the memory system. the memory system may determine the type of data based on a value of a counter associated with a segment of a mapping of the memory system that includes a logical address of the data. additionally, or alternatively, the memory system may determine the type of data based on determining a quantity of invalid data in a set of recently selected (e.g., opened) blocks of the memory system. the memory system may select the block for storing the data based on the type of data and a quantity of times that the block has been erased and write the data to the selected block.
20240069744.APPARATUS WITH SIGNAL QUALITY FEEDBACK_simplified_abstract_(micron technology, inc.)
Inventor(s): Jackson Callaghan of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, apparatuses, and systems related to operations for measuring the quality of a signal received by a memory device and providing feedback. the memory device can sample signal data using a predetermined sequence of timing offsets relative to a reference signal. additionally or alternatively, the memory device can sample the signal data using a predetermined sequence of reference voltages. the memory device can provide feedback results to a controller regarding the quality of the sampled signal data.
Inventor(s): Hyungseok Kim of Santa Clara CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Sampath K. Ratnam of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: an example method of performing read operation comprises: receiving a read request with respect to a set of memory cells of a memory device; determining a value of a media endurance metric of the set of memory cells; determining a programing temperature associated with the set of memory cells; determining a current operating temperature of the memory device; determining a voltage adjustment value based on the value of the media endurance metric, the programming temperature, and the current operating temperature; adjusting, by the voltage adjustment value, a bitline voltage applied to a bitline associated with the set of memory cells; and performing, using the adjusted bitline voltage, a read operation with respect to the set of memory cells.
20240069748.REDUCING BIT ERROR RATE IN MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Tingjun Xie of Milpitas CA (US) for micron technology, inc., Yang Liu of San Jose CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Juane Li of Milpitas CA (US) for micron technology, inc., Aaron Lee of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page. the processing device further performs a second media scan operation with respect to a plurality of memory pages addressable by the mandatory wordline, wherein each page of the plurality of memory pages is contained by the respective management unit, and responsive to determining that a value of the data state metric of a memory page of the plurality of memory page addressable by the mandatory wordline satisfies the specified condition, performs a second media management operation with respect to the management unit containing the memory page.
Inventor(s): Augusto Benvenuti of Lallio (IT) for micron technology, inc., Giovanni Maria Paolucci of Milano (IT) for micron technology, inc., Alessio Urbani of Roma RM (IT) for micron technology, inc., Gianpietro Carnevale of Bottanuco (IT) for micron technology, inc., Aurelio Giancarlo Mauri of Meda (MB) (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory access operation is initiated to read a set of target memory cells of a target wordline of the memory device. during the memory access operation, a read voltage level is caused to be applied to the target wordline. during the memory access operation, a first pass through voltage level is caused to be applied to a first wordline adjacent to the target wordline. during the memory access operation, a second pass through voltage is caused to be applied to a second wordline adjacent to the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level.
Inventor(s): Qi Dong of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06, G06F21/57, G06F21/60
Abstract: a system for providing memory chip test pad access management to facilitate data security is disclosed. a host issues a command to access a non-volatile memory of a memory chip system via a test pad. a controller acknowledges the command by transmitting a response to the host to authenticate the host for access. the host then issues an authenticated command to modify a reserved byte of a protected memory partition of the non-volatile memory. the controller responds to the authenticated command and the reserved byte is modified. firmware of the memory chip system monitors the modification of the reserved byte and notifies the memory chip system to activate a switch in an access control unit controlling access to the non-volatile memory. the switch is then activated, thereby closing a circuit to connect the test pad with the non-volatile memory. the host then access the non-volatile memory via the test pad.
Inventor(s): Michael Burk of Orangevale CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: the present disclosure includes apparatuses, methods, and systems for partitioning system data from user data in memory. in an example, a method can include receiving system data at a memory, assigning the system data a first address within a first range of memory addresses, storing the system data in a first portion of the memory operated with a first set of trim settings in response to the system data having the first address within the first range of memory addresses, receiving user data, assigning the user data a second address within a second range of memory addresses, and storing the user data in a second portion of the memory operated with a second set of trim settings in response to the user having the second address within the second range of addresses.
20240069758.SHARED MEMORY SNAPSHOTS_simplified_abstract_(micron technology, inc.)
Inventor(s): John Groves of Austin TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system can include a memory device and a processing device operatively coupled with the memory device, to perform operations including receiving, from a first host application, a data object to store on the memory device and associating an object identifier with physical address ranges. the operations can further include associating the object identifier with a snapshot identifier to define a snapshot and mapping the physical address ranges to corresponding virtual address ranges of a second host application. the operations can also include responsive to receiving, from the first host application, a request to write to the data object recording, in a change log, an entry reflecting a change made to the data object, and responsive to receiving, from the first host application, a request to read a part of the data object, retrieving the part from the entry of the change log.
Inventor(s): Kwang-Ho Cho of Boise ID (US) for micron technology, inc., Miki Matsumoto of Boise ID (US) for micron technology, inc., Kevin J. Ryan of Elizabeth CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for triple activate command row address latching are described. for instance, a memory device may receive a first activate command that indicates a first set of bits of a row address, a second activate command that indicates a second set of bits of the row address, and a third activate command that indicates a third set of bits of the row address. the memory device may activate a page of memory based on receiving the first activate command, the second activate command, and the third activate command, where the page of memory is addressed according to the first set of bits, the second set of bits, and the third set of bits.
Inventor(s): Kwang-Ho Cho of Boise ID (US) for micron technology, inc., Miki Matsumoto of Tokyo (JP) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for row address latching for multiple activate command protocol are described. a memory device may receive a first activate command that indicates a first set of bits of a row address and may store the first set of bits to obtain a first delayed signal of the first set of bits. the memory device may receive a second activate command that indicates a second set of bits of the row address and may store the second set of bits to obtain a first delayed signal of the second set of bits. the memory device may store the first delayed signal of the first set of bits to obtain a second delayed signal of the first set of bits and may activate a page of memory addressed according to the second delayed signal and the first delayed signal of the second set of bits.
Inventor(s): Matthew A. Prather of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: an apparatus, comprising a plurality of memories and a single integrated circuit (ic) that is configured to be coupled to a host device by a host bus and that is coupled to the plurality of memories by a memory bus, wherein the ic comprises a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the plurality of memories, and a power management integrated circuit (pmic) module that is configured to regulate voltage and monitor current provided to the plurality of memories.
Inventor(s): Scott E. SCHAEFER of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: implementations described herein relate to single-bit error indication for a memory built-in self-test. a memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. the memory device may perform the memory built-in self-test for one or more memory sections of the memory device based on reading the one or more bits that are stored in the mode register of the memory device. the memory device may identify a number of single-bit errors associated with the one or more memory sections of the memory device based on performing the memory built-in self-test. the memory device may transmit an indication of the number of single-bit errors based on repairing one or more of the single-bit errors associated with the one or more memory sections of the memory device.
20240069765.TWO-TIER DEFECT SCAN MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Robert Loren O. Ursua of Folsom CA (US) for micron technology, inc., Sead Zildzic of Rancho Cordova CA (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Lakshmi Kalpana K. Vakati of Fremont CA (US) for micron technology, inc., Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. each scan operation can be performed using a corresponding predetermined read-time parameter value. the operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. the operations can also include performing the remedial operation with respect to the management unit.
20240069766.SELECTIVE DATA MAP UNIT ACCESS_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco REDAELLI of Munich (DE) for micron technology, inc., Gaurav SINHA of Oberschleißheim (DE) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: implementations described herein relate to selective data map unit access. a memory device may receive a request from a host device to access a resource associated with a data map unit. the memory device may identify whether the data map unit is in a locked state or an unlocked state. the data map unit may be in the locked state when another host device currently has exclusive access to the resource or may be in the unlocked state when no other host device currently has exclusive access to the resource. the memory device may selectively grant the host device exclusive access to the resource based on identifying whether the data map unit is in the locked state or the unlocked state.
Inventor(s): Marco Redaelli of Munchen (DE) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory device controller for a non-volatile memory device can be configured to allow exclusive access to initiate or increment a refresh routine based on an earlier-received one of a refresh command from a host device or an interval-triggered refresh command from the controller. the memory device controller can be configured to lock out access to the refresh routine from a later-received one of the refresh command from the host device or the interval-triggered refresh command from the controller. the memory device controller can release a lock on access to the refresh routine upon completion of a block refresh routine for a memory block of the memory device. in some examples, the refresh command from the host device can be based on a power cycle status of the host device.
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allow a memory device to efficiently mark memory extents involved in an enhanced memory operation. an extent is marked if a meta state associated with the extent indicates that the extent is included in the enhanced memory operation. the largest memory extents of the operation are maintained in the memory device as a list of unmarked extents. when a primitive memory operation is received, the memory address is compared to the unmarked extents in the list to the meta state for that memory line. if the address is covered by the list of extents, or that line's meta state is marked, then the memory operation is performed including the enhanced memory operation.
20240069771.READ OPERATIONS FOR MIXED DATA_simplified_abstract_(micron technology, inc.)
Inventor(s): Scheheresade VIRANI of Frisco TX (US) for micron technology, inc., Raja V.S. HALAHARIVI of Gilroy CA (US) for micron technology, inc., Ning ZHAO of Milpitas CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: in some implementations, a memory device may receive, from a host device, a read command indicating data and one or more logical block addresses to be read from a memory of the memory device. the memory device may obtain a memory unit from the memory based on the read command. the memory device may determine status information associated with the one or more logical block addresses based on information indicated by the memory unit. the memory device may generate a single data transfer request associated with the one or more logical block addresses, where the single data transfer request indicates status indicators associated with respective logical block addresses of the one or more logical block addresses. the memory device may provide, to the host device, one or more responses to the read command, where the one or more responses are based on the status indicators.
Inventor(s): Oyvind Haehre of Loveland CO (US) for micron technology, inc., Nathaniel Wessel of Longmont CO (US) for micron technology, inc., Byron Harris of Mead CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: various embodiments provide for deferring adjustment of a zone in a memory system or sub-system that supports zones. in particular, some embodiments provide for deferred adjustment of a zone based on detection of an error in a block of an unassigned block set, which can be tracked using a counter.
Inventor(s): Xiangang Luo of Fremont CA (US) for micron technology, inc., Jianmin Huang of San Carlos CA (US) for micron technology, inc., Hong Lu of San Jose CA (US) for micron technology, inc., Kulachet Tanpairoj of Santa Clara CA (US) for micron technology, inc., Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc., Nitul Gohain of Bangalore (IN) for micron technology, inc., Uday Bhasker V. Vudugandla of Telangana (IN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. the operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system includes a memory device and a processing device coupled to the memory device, and the processing device is to perform operations including determining, by monitoring accesses to the memory device, a plurality of values of one or more memory usage statistics reflecting memory usage by a plurality of requestors connected to the memory sub-system; generating memory usage data by processing the plurality of values of the one or more memory usage statistics; and transmitting, to a requestor of the plurality of requestors, the memory usage data.
Inventor(s): Francesco Basso of Portici (NA) (IT) for micron technology, inc., Antonino Pollio of Vico Equense (NA) (IT) for micron technology, inc., Francesco Falanga of Quarto (NA) (IT) for micron technology, inc., Massimo Iaculo of San Marco Evangelista (CE) (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for idle mode temperature control for memory systems are described. a memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. for example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. the memory system may measure the temperature of the memory device during the idle mode. if the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.
Inventor(s): Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Thomas Lentz of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system includes a memory device containing multiple dies that each have multiple pages, and a processing device, operatively coupled with the memory device, to perform various operations including scanning a group of pages residing on a die and determining a value of one data state metric and a corresponding value of another state metric. the operations can also include recording a set of values of the first metric and a corresponding set of values of the second metric, as well as calculating the value of the second metric corresponding to a predetermined value of the first metric associated with a failure condition of the die. additionally, the operations can include identifying a particular criterion that is satisfied by the calculated value, assigning, to the die, a rating corresponding to the identified criterion, and performing scans on the die at a frequency determined by the assigned rating.
20240069788.FILTERING METRICS ASSOCIATED WITH MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Dung Viet NGUYEN of San Jose CA (US) for micron technology, inc., Shantilal Rayshi DORU of San Diego CA (US) for micron technology, inc., Jun WAN of San Jose CA (US) for micron technology, inc., Sampath RATNAM of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: in some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. the controller may apply a function to the first metric to obtain a second memory read configuration. the controller may obtain a second metric associated with the memory using the second memory read configuration. the controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. the controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. the controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.
Inventor(s): Giovanni Maria Paolucci of Milan (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory device includes a memory array and control logic to perform operations including identifying a target cell and a set of cells adjacent to the target cell. each cell of the set of cells is associated with a respective adjacent cell state. the operations further include determining, for each adjacent cell state, a respective interference value, assigning, based on the respective interference value, each adjacent cell state to a respective bin of a set of state information bins, and in response to determining that each bin of the set of state information bins has at least one adjacent cell state assigned to it, and determining a set of read level offsets for reading the target cell. each read level offset of the set of read level offsets is associated with a respective bin of the set of state information bins.
Inventor(s): Michael Keith Dugan of Richardson TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system includes a host device having a first buffer with ordered data. an accelerator device has a data movement processor and a reordering buffer. a multiple-channel interface couples the host device and the data movement processor of the accelerator device. the data movement processor is configured to issue a read command for a portion of the ordered data. in coordination with issuing the read command, an entry of the reordering buffer is allocated. a transaction identifier for the read command is allocated. unordered responses are received from the host device via the multiple-channel interface. the responses include respective portions of the ordered data and a respective transaction identifier. the responses are reordered in the reordering buffer based on the respective transaction identifiers and the allocated entry of the reordering buffer.
Inventor(s): Scheheresade VIRANI of Frisco TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: implementations described herein relate to memory device operations for unaligned write operations. in some implementations, a memory device may receive, from a host device, a write command indicating data having a first size that corresponds to a first write unit and a first logical address. the memory device may allocate a set of buffers for the write command. the memory device may determine a set of physical addresses corresponding to a physical address that is associated with the second size, where the set of physical addresses are each associated with the first size. the memory device may merge stored data from the set of physical addresses to one or more buffers, from the set of buffers, that do not include the data to generate a data unit having the second size. the memory device may write the data unit to memory indicated by the set of physical addresses.
20240069800.HOST-PREFERRED MEMORY OPERATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc., Dean E. Walker of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F9/38
Abstract: system and techniques for host-preferred memory operation are described herein. at a memory-side cache of a memory device that includes accelerator hardware, a first memory operation can be received from a host. a determination that the first memory operation corresponds to a cache set based on an address of the first memory operation is made. a second memory operation can be received from the accelerator hardware. another determination can be made that the second memory operation corresponds to the cache set. here, the first memory operation can be enqueued in a host queue of the cache set and the second memory operation can be enqueued in an internal request queue of the cache set. the first memory operation and the second memory operation can be executed as each is dequeued.
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc., Dean E. Walker of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: systems and techniques for a memory-side cache directory-based request queue are described herein. a memory request is received at an interface of a memory device. one or more fields of the memory request are written into an entry of a directory data structure. the identifier of the entry is pushed onto a queue. to perform the memory request, the identifier is popped off of the queue and a field of the memory request is retrieved from the entry of the directory data structure using the identifier. then, a process on the memory request can be performed using the field retrieved from the entry of the directory data structure.
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a method performed by a distributed computing system includes receiving a work packet from a separate computing device via a fabric interconnect at a command manager (cm) of a memory controller of a fabric attached memory (fam) device, wherein the work packet includes a memory access to be performed by a fam computing resource local to the fam device; determining a work class of the work packet; placing the work packet in a cm work queue local to the cm for the work class when space is available in the cm work queue for the work class; and when the cm work queue for the work class is full, placing the work packet in a destination work queue according to an address included in the work packet, wherein the destination queue is implemented in a memory array of the fam device external to the memory controller.
20240069804.CONTROL PARAMETER ADDRESS VIRTUALIZATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc., Michael Keith Dugan of Richardson TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: host and accelerator devices can be coupled using various interfaces, such as compute express link (cxl). in an example, user applications can have protected access to a shared set of control parameters for different queues. a protocol can allow an application to use a unique memory page at the accelerator device through which the application can access control parameters, such as can be used to control memory-based communication queues or other queues. in an example, there can be multiple sets of control parameters in a single memory page. the protocol can allow views of the single memory page from respective different application processes. in an example, the protocol can include or use an access check to detect and handle unauthorized accesses to particular parameters.
Inventor(s): Michael Keith Dugan of Richardson TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system includes a memory device and a command manager configured to reorder read requests. the command manager is configured to receive a read response associated with a transaction identifier for the read request. a free list entry for the read request is allocated from a free list. the free list entry is associated with a transaction identifier of the read request. a tail index of a reordering queue is written to a remapping queue based on the free list entry. the tail index is configured to provide a write address of the reordering queue that is allocated for the read request. a read response associated with the transaction identifier for the read request is received. the read response is written to the allocated entry of the reordering queue.
Inventor(s): Naveen Bolisetty of Suryapet (IN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system and method for managing data compaction in zones in memory devices. an example method includes receiving, by a processor of a memory device, receiving, by a processing device, a write command; identifying a zoned namespace (zns) zone specified with the write command; selecting a first subset of memory pages of a first management unit that is configured to store a first number of bits per memory cell, wherein the first management unit is associated with the zns zone; accessing a capacity counter associated with the zns zone that reflects an amount of data currently stored to the zns zone; and responsive to determining that the capacity counter satisfies a threshold criterion, causing the memory device to copy the data associated with the zns zone from the first subset of memory pages to a second subset of memory pages of a second management unit of the memory device.
Inventor(s): Raja V.S. Halaharivi of Gilroy CA (US) for micron technology, inc., Prateek Sharma of San Jose CA (US) for micron technology, inc., Venkat R. Gaddam of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving, from a host system, a memory access command; executing the memory access command; identifying a characteristic associated with the memory access command; identifying a threshold period of time corresponding to the characteristic associated with the memory access command; determining that a period of time associated with the memory access command satisfies the threshold period of time; and responsive to determining that the period of time associated with the memory access command satisfies the threshold period of time, notifying the host system of completion of execution of the memory access command.
Inventor(s): Shakeel Isamohiuddin BUKHARI of San Jose CA (US) for micron technology, inc., Mark ISH of Manassas VA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
Abstract: a memory device may include logical units configured to store data, wherein the logical units are identified by corresponding logical unit numbers (luns) and are associated with corresponding lun queue groups. each lun queue group may include lun queues that are each associated with a respective intra-lun priority level that indicates a priority of a lun queue within a lun queue group. the lun queues are each associated with a respective execution priority level that indicates a priority for execution of commands in a lun queue across lun queue groups. a quantity of intra-lun priority levels may be greater than a quantity of execution priority levels. a lun scheduler may be configured to select and transfer commands from lun queue groups to the execution queue group based on intra-lun priority levels. a command executor may be configured to execute commands from the execution queue group based on execution priority levels.
Inventor(s): Tyler L. Betz of Meridian ID (US) for micron technology, inc., Sundararajan N. Sankaranarayanan of Fremont CA (US) for micron technology, inc., Roberto Izzi of Caserta (IT) for micron technology, inc., Massimo Zucchinali of Torre Boldone (IT) for micron technology, inc., Xiangyu Tang of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory device includes an interface to communicate with a host, an array of memory cells, and a controller. the controller is configured to access the array of memory cells in response to commands from the host. the controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. the controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. the controller is further configured to predict the length of a subsequent idle time based on the history.
Inventor(s): Tingjun Xie of Milpitas CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Charles Kwong of Redwood City CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C16/34
Abstract: a processing device of a memory sub-system is configured to perform a plurality of write operations on a memory device comprising a plurality of memory units, the processing device is configured to maintain state information of the memory device in response to performing each write operation of a plurality of write operations on the memory device; identify, in view of the state information, a candidate memory unit of the plurality of memory units that has been written to by at least a threshold fraction of the plurality of write operations performed on the memory device; and responsive to determining that a number of write operations performed on the memory device satisfies a threshold refresh criterion and that one or more of the plurality of memory units that are proximate to the candidate memory unit satisfy a failed bit threshold criterion, refresh data stored at the one or more of the plurality of memory units that are proximate to the candidate memory unit.
Inventor(s): Bryan Hornung of Plano TX (US) for micron technology, inc., David Patrick of McKinney TX (US) for micron technology, inc.
IPC Code(s): G06F9/48, G06F9/30
Abstract: devices and techniques for handling breakpoints in a multi-element processor are described herein. a compute node includes a hybrid threading processor and hybrid threading fabric, where the hybrid threading fabric comprises a plurality of memory-compute tiles, where each of the memory-compute tiles include respective processing and storage elements used to execute a kernel, and where each of the memory-compute tiles includes a breakpoint controller to initiate a breakpoint for the plurality of memory-compute tiles.
Inventor(s): Christopher Baronne of Allen TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F9/54, G06F9/30
Abstract: devices and techniques for asynchronous event message handing in a processor are described herein. a barrel multithreaded processor may include an asynchronous event handler to receive an indication of a thread create instruction from a parent thread, determine a return value size of return values from the indication of the thread create instruction, determine whether sufficient space exists in the memory to store the return values, allocate space in the memory to store the return parameters in response to determining that there is sufficient space in the memory to store the return values, and provide access to the return values from the allocated space to the parent thread based at least in part on a thread return instruction from the child thread.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F9/54, G06F13/16
Abstract: a storage product manufactured as a standalone computer component, having a bus connector to an external processor, a storage device, a random-access memory, a computational storage processor, and a processing device to identify, among storage access messages from a computer network, first messages, second messages, and third messages. the random-access memory hosts first queues shared between the processing device and the external processor, and second queues shared between the processing device and the computational storage processor. the processing device can place the first messages in the first queues for the external processor to generate fourth messages, place the second messages in the second queues for the computational storage processor to generate fifth messages, and provide the third messages to the storage device. the storage device can process the third messages, the fourth messages, and the fifth messages to implement requests in the storage access messages.
Inventor(s): Shakeel Isamohiuddin BUKHARI of San Jose CA (US) for micron technology, inc., Mark ISH of Manassas VA (US) for micron technology, inc.
IPC Code(s): G06F11/00, G06F12/12
Abstract: in some implementations, a memory device may cache a subset of one or more block family error avoidance (bfea) lookup tables associated with a block family associated with host data in a first memory location. the block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. the memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more bfea tables, a threshold voltage offset associated with the host data. the memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. the memory device may read, using the modified threshold voltage, the host data from the first memory location.
Inventor(s): Hao Ge of Fremont CA (US) for micron technology, inc., Jaeil KIM of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/07, H04L1/00
Abstract: methods, systems, and devices for auto-calibration of error detection signals are described. an error may be injected into a data signal obtained from a memory array. after injecting the error into the data signal, the data signal may be applied to an error detection circuit of the memory array, where the error detection circuit may output an error signal for the data signal. the error signal may be delayed relative to a control signal by a first amount. a timing signal that controls the propagation of the error signal may be obtained based on delaying the control signal by a second amount. based on a comparison of the error signal and the timing signal, a third amount for delaying the control signal may be determined.
Inventor(s): Aaron Jannusch of Boise ID (US) for micron technology, inc., Mow Yiak Goh of Boise ID (US) for micron technology, inc., Robin K. Mitra of Buda TX (US) for micron technology, inc.
IPC Code(s): G06F11/07
Abstract: memory with fail indicators, and associated systems, devices, and methods are disclosed herein. in one embodiment, a system includes a plurality of memory systems and a host device. at least one of the memory systems includes a fail indicator connected to the host device via a side channel of the system. the host device is configured to detect an occurrence of a failure on the at least one memory system and to initiate activation of the fail indicator. the side channel can be an i2c or i3c side channel. the fail indicator, when activated, can provide a visual indication of the failure. for example, the fail indicator can include an led that can be activated to emit light and provide an indication of the failure. a color of the light can correspond to a type, occurrence, or location of the failure on the at least one memory system.
Inventor(s): Jay Sarkar of San Jose CA (US) for micron technology, inc., Ipsita Ghosh of New Garia (IN) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F11/07
Abstract: systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. the processing device can perform operations including receiving log data related to a first order of a set of error-handling operations performed on data residing in a segment of a memory device; applying an optimization model to the log data, wherein the optimization model is based on probability data of error recovery and latency data of the set of error-handling operations; and responsive to applying the optimization model to the log data, obtaining, as an output of the optimization model, a second order of the set of error-handling operations, wherein the second order adjusts an order of one or more error-handling operations of the set of error-handling operations in the first order.
Inventor(s): Christopher Baronne of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F11/07, G06F9/38
Abstract: devices and techniques for parking threads in a barrel processor for managing hazard clearing are described herein. a barrel processor includes hazard management circuitry that is used to receive an indication of an instruction executing in a compute pipeline of the barrel processor, the instruction having encountered a hazard and unable to progress through the compute pipeline; store the indication of the instruction in a hazard memory; receive a signal indicating that the hazard has cleared; and cause the instruction to be rescheduled at the beginning of the compute pipeline in response to the signal.
Inventor(s): Francesco Lupo of München (DE) for micron technology, inc.
IPC Code(s): G06F11/08, G06F3/06
Abstract: systems, methods, and apparatus related to error correction in memory devices. in one approach, a memory device uses dedicated op-codes to generate, during programming operations, a pattern including known requested data errors. during reading operations on the memory device, the calibrated errors will be detected by the ecc engine of the memory device as read errors. this permits a host device to observe, in a controlled environment, how the ecc engine behaves and performs in a final manufactured memory product.
20240070015.Read Data Path_simplified_abstract_(micron technology, inc.)
Inventor(s): Nicola Del Gatto of Cassina de Pecchi (IT) for micron technology, inc., Emanuele Confalonieri of Segrate (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: described apparatuses and methods relate to a read data path for a memory system. the memory system may include logic that receives data and associated metadata from a memory. the logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. if the data is determined not to include an error, the data may be transmitted to a requestor. if the data is determined to include an error, however, a data recovery process may be initiated to recover the data. this may reduce a likelihood the memory system returns corrupted data to a requestor. the memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. in some cases, the data recovery process may involve one or more techniques related to redundant array of disks (raid) technology.
Inventor(s): Sanjay Subbarao of Irvine CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07, G06F11/14
Abstract: various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a rain (redundant array of independent nand-type flash memory devices) technique for data error-correction. for some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.
20240070021.PROXIMITY BASED PARITY DATA MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Wei Wang of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/14, G06F11/34
Abstract: a method includes generating parity data corresponding to a plurality of word lines coupled to blocks of a memory device and generating additional parity data for a block based on a physical location of the block. the method can further include performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.
Inventor(s): Steffen Buch of Taufkirchen (DE) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
Abstract: methods, apparatuses, and non-transitory machine-readable media associated with a data inversion and unidirectional error detection are described. an apparatus for data inversion and unidirectional error detection can include a memory device and a processing device communicatively coupled to the memory device. the processing device can be configured to encode a plurality of binary data bits in an information word, encode the information word using a unidirectional error detecting code, write the encoded information word to the memory device, read the encoded information word from the memory device, and detect an error in the information word using a unidirectional error detecting code. the encoding can include inverting the plurality of binary data bits and adding an inversion data bit to the information word.
Inventor(s): Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Niccolo' Righetti of Boise ID (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Mark A. Helm of Santa Cruz CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Ugo Russo of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07, G06F11/14
Abstract: a method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.
20240070024.Read Data Path for a Memory System_simplified_abstract_(micron technology, inc.)
Inventor(s): Nicola Del Gatto of Boise ID (US) for micron technology, inc., Emanuele Confalonieri of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/00
Abstract: described apparatuses and methods relate to a read data path for a memory system. a memory system can include logic that receives data from a memory. the data may include first data, parity data, and metadata that enables a reliability check of the data. the logic may perform the reliability check of the data to determine an accuracy of the data. if the data is determined not to include an error, the data may be transmitted for accessing by a requestor. if the data is determined to include an error, however, a data recovery process may be initiated to recover the corrupted data along a separate data path. in doing so, the apparatuses and methods related to a read data path for a memory system and described herein may reduce the likelihood that a memory system returns corrupted data to a requestor.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
Abstract: apparatuses, systems, and methods for module level error correction. multiple memory devices a packaged together in a memory module. the module includes a module error correction code (ecc) circuit which pools information multiple memory devices on the module. in an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. the codewords may include data bits provided along a data bus and parity bits provided along a parity bus. the ecc circuit pools the codewords and detects errors in the pooled codewords.
20240070049.SECURELY MODIFYING ACCESS TO A DEBUG PORT_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): G06F11/36
Abstract: in some aspects, the techniques described herein relate to a device including: a debug port; a trusted execution environment (tee), the tee storing a public key; and a controller, the controller configured to: receive a command to access the debug port, the command including a signature generated using a private key corresponding to the public key; provide the command to the tee, wherein the tee validates the command by validating the signature using the public key to obtain a validation result; and modify access to the debug port based on the validation result.
20240070050.AUTOMATED GUI-DRIVEN OPROM VALIDATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Shiva Pahwa of Bangalore (IN) for micron technology, inc., Harsha Vardhana Gonchigara Vemanna of Bangalore (IN) for micron technology, inc., Sathyashankara Bhat Muguli of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F11/36, G06F1/3225
Abstract: a method for performing automated gui-driven oprom validation starts with a processor executing an automated test script; and in response to executing the automated test script, the processor is caused to remotely accessing a memory sub-system using a web driver and an interface. the processor causes a bios terminal window of the memory sub-system to be displayed on a display screen. the processor captures a screenshot of the bios terminal window and generating an image based on the screenshot. the processor converts the image to text using ocr and generates an output comprising bios configuration details based on the text using a machine-learning algorithm. the processor then analyzes the output to validate the memory sub-system when no errors are detected in the output or to flag the memory sub-system when errors are detected in the output. other embodiments are described herein.
Inventor(s): Domenico Punzo of Volla (IT) for micron technology, inc., Marco Di Pasqua of Naples (IT) for micron technology, inc.
IPC Code(s): G06F12/02
Abstract: a memory card can include memory and a memory controller. the controller can receive a general command to increase the busy time of any subsequent access command. subsequently, the controller can receive an access command from a host to access the memory. the controller can then place the memory in a busy state for a time duration based on the general command, such that the memory refrains from processing read or write commands for the time duration. the timeout measure is the busy time between the time when the access command is issued and the host timeout.
20240070058.READ CONTROL SIGNAL GENERATION FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Jaeil Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02, G11C11/22, G11C11/4096
Abstract: a system includes memory having a bank area and a channel area. the system further includes control circuitry to receive a command to access the memory. responsive to receiving the command to access the memory, the control circuitry can provide a bank strobe signal for accessing memory in the bank area and at least two channel strobe signals for accessing memory in the channel area. the channel strobe signal may process a smaller amount of data than that processed by the bank strobe signal.
Inventor(s): Vikas Rana of Pehowa (IN) for micron technology, inc., Kalyan Chakravarthy Kavalipurapu of Telangana (IN) for micron technology, inc.
IPC Code(s): G06F12/02, G06F11/10, G11C16/04, G11C16/08, G11C16/24, G11C16/26
Abstract: a memory device includes a first array of non-volatile memory (nvm) cells, a second array of logic nvm cells, and a controller. the second array of logic nvm cells stores instructions for accessing the first array of nvm cells. the controller is configured to execute the instructions stored in the second array of logic nvm cells to perform access operations in the first array of nvm cells.
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc., Dean E. Walker of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/0831, G06F12/0893
Abstract: system and techniques for synchronized request handling at a memory device are described herein. a request is received at the memory device. here, the request indicates a memory address corresponding to a set of cache lines and a single cache line in the set of cache lines. the memory device maintains a deferred list for the set of cache lines and a set of lists with each member of the set of lists corresponding to one cache line in the set of cache lines. the memory device tests the deferred list to determine that the deferred list is not empty and places the request in the deferred list.
Inventor(s): Steven R. NARUM of Meridian ID (US) for micron technology, inc., Huapeng GUAN of Redwood City CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F1/3225
Abstract: a memory device may detect a memory operation that updates a level two volatile (l2v) entry stored in an l2v table. each l2v entry in the l2v table may indicate a mapping between a respective logical block address (lba) and a respective user data physical address in non-volatile memory. the memory operation may cause a mapping between an lba indicated in the l2v entry and a user data physical address indicated in the l2v entry to become invalid. the memory device may store, in a volatile memory log, an indication of an lba region that includes the lba. the memory device may detect that an l2 transfer condition, associated with the volatile memory log, is satisfied. the memory device may copy, from volatile memory to non-volatile memory, every l2v entry that indicates an lba included in the lba region based on detecting that the l2 transfer condition is satisfied.
20240070063.SEQUENTIAL GARBAGE COLLECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): David A. Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
Abstract: an example apparatus for sequential garbage collection can include a memory device including a plurality of memory blocks associated with a plurality of logical block addresses (lbas). the example apparatus can include a controller coupled to the memory device. the controller can be configured to monitor a quantity of read operations and a quantity of write operations associated with a plurality of command sizes performed on a portion of the plurality of memory blocks. the controller can be configured to monitor a quantity of read operations and a quantity of write operations associated with a particular lba. the controller can be configured to determine a type of garbage collection operation to perform based on the monitoring.
20240070069.MEMORY DEVICE INTERFACE AND METHOD_simplified_abstract_(micron technology, inc.)
Inventor(s): Brent Keeth of Boise ID (US) for micron technology, inc., Owen Fay of Meridian ID (US) for micron technology, inc., Chan H. Yoo of Boise ID (US) for micron technology, inc., Roy E. Greeff of Boise ID (US) for micron technology, inc., Matthew B. Leslie of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/06, G06F12/02, G11C11/4093, G11C29/12, H01L25/065, H01L25/18
Abstract: apparatus and methods are disclosed, including memory devices and systems. example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a dram interface side. the slower, and wider dram interface may be configured to substantially match the capacity of the narrower, higher speed host interface. in some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. selected example memory devices, systems and methods include an individual dram die, or one or more stacks of dram dies coupled to a buffer die.
20240070072.TELEMETRY-CAPABLE MEMORY SUB-SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F12/0815
Abstract: an access counter associated with a segment of a memory device is maintained. an access notification for a first line of the segment is received. an access type associated with the access notification is identified. a first value of the access counter is changed by a second value based on the access type. based on the first value of the access counter, a memory management scheme is implemented.
20240070074.VARIABLE EXECUTION TIME ATOMIC OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Dean E. Walker of Allen TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F9/345, G06F9/30, G06F9/38
Abstract: system and techniques for variable execution time atomic operations are described herein. when an atomic operation for a memory device is received, the run length of the operation is measured. if the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. a result of the operation is queued until it can be written to the cache line. at that point, the cache line is unlocked.
20240070077.MEMORY SIDE CACHE REQUEST HANDLING_simplified_abstract_(micron technology, inc.)
Inventor(s): Dean E. Walker of Allen TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F12/0855
Abstract: system and techniques for memory side cache request handling are described herein. when a memory request is received, a cache set for the memory request is determined. here, the cache set has multiple ways and each way corresponds to a cache line. it can be detected that a way of the multiple ways is not ready for the memory request. in this case, a representation of the memory request is stored in a queue of multiple queues based on an interface upon which the memory request was received and the present ways of the cache set. entries from the multiple queues can be dequeued in a defined order to determine a next memory request to process. the defined order gives priority to memory requests for a present way and then for external over internal requests.
20240070078.RECALL PENDING CACHE LINE EVICTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Dean E. Walker of Allen TX (US) for micron technology, inc., Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F12/0855, G06F12/0891
Abstract: system and techniques for recall pending cache line eviction are described herein. a queue that includes a deferred memory request is kept for a cache line. metadata for the queue is stored in a cache line tag. when a recall is needed, the metadata is written from the tag to a first recall storage, referenced by a memory request id. after the recall request is transmitted, the memory request id is written to a second recall storage referenced by the message id of the recall request. upon receipt of a response to the recall request, the queue for the cache line can be restored by using the message id in the response to lookup the memory request id from the second recall storage, then using the memory request id to lookup the metadata from the first recall storage, and then writing the metadata into the tag for the cache line.
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc., Dean E. Walker of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F12/0891
Abstract: system and techniques for evicting a cache line with pending control request are described herein. a memory request—that includes an address corresponding to a set of cache lines—can be received. a determination can be made that a cache line of the set of cache lines will be evicted to process the memory request. another determination can be made that a control request has been made to a host from the memory device and that the control request pending when it is determined that the cache line will be evicted. here, a counter corresponding to the set of cache lines can be incremented (e.g., by one) to track the pending control request in face of eviction. then, the cache line can be evicted.
20240070083.SILENT CACHE LINE EVICTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc., Dean E. Walker of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F12/0891, G06F9/38
Abstract: system and techniques for silent cache line eviction are described herein. a memory device receives a memory operation from a host. the memory operation establishes data and metadata in a cache line of the memory device upon receipt. the metadata is stored in a memory element that corresponds to the cache line. later, an eviction trigger to evict the cache line is identified. then, in response to the eviction trigger, current metadata of the cache line is compared with the metadata in the memory element to determine whether the metadata has changed. the cache line can be evicted without writing to backing memory in response to the metadata being unchanged.
Inventor(s): Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G06F12/0891, G06F12/0831, G06F13/16
Abstract: a victim management unit (mu) for performing a media management operation is identified. the victim mu stores valid data. a flush command is received from a host system. a cached data item is retrieved from a volatile memory. the cached data item and at least a subset of the valid data stored at the victim mu are written to a target mu.
Inventor(s): Christopher Baronne of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F12/126
Abstract: devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. a barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.
20240070089.MEASUREMENT COMMAND FOR MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Lance W. Dover of Fair Oaks CA (US) for micron technology, inc.
IPC Code(s): G06F12/14, H04L9/32
Abstract: methods, systems, and devices for a measurement command for memory systems are described. a memory system and a host system may support a measure command to calculate a cryptographic value of data stored in a region of the memory system. in some cases, a region indicated by the measure command may correspond to a protected region of the memory system. in such cases, the measure command may include a cryptographic signature from the host system. upon receiving the measure command, the memory system may perform a hashing operation on the data to generate the cryptographic value. in some cases, the memory system may transmit the digest to the host. additionally or alternatively, the memory system may extend the digest into a register indicated by the command. further, the measure command may be used to generate a key pair associated with the memory system.
Inventor(s): Hyun Yoo Lee of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc., Jason McBride Brown of Austin TX (US) for micron technology, inc., Venkatraghavan Bringivijayaraghavan of Hyderabad (IN) for micron technology, inc., Vijayakrishna J. Vankayala of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F13/16, G06F13/40
Abstract: apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. the asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. the “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. the orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. with asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.
20240070094.CONTROLLING AGGREGATION FOR HRAM_simplified_abstract_(micron technology, inc.)
Inventor(s): John Maroney of Irvine CA (US) for micron technology, inc.
IPC Code(s): G06F13/16, G06F12/02, G06F13/18
Abstract: a method for controlling aggregation for hram comprises a processing device, using a buffer manager, to receive instructions that include smaller-sized block write instructions from a host system. the processing device, using an aggregation engine, aggregates the smaller-sized block write instructions from the buffer manager into a plurality of larger-sized write instructions. the processing device issues a burst write instruction comprising the larger-sized write instructions to the memory component via the interface. the memory component can be hram and the interface can be a modified ddr-l5 interface for hram. other embodiments are described herein.
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Creston M. Dupree of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/16, G06F11/07
Abstract: described apparatuses and methods relate to erroneous select die access (sda) detection for a memory system. a memory system may include a memory controller and a memory device that are capable of implementing an sda protocol that enables selective memory die access to multiple memory devices that couple to a command bus. a memory device can include logic that determines if signaling that conflicts with the sda protocol is detected. if it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. in doing so, the erroneous sda detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.
20240070101.Bus Training with Interconnected Dice_simplified_abstract_(micron technology, inc.)
Inventor(s): Francesco Douglas Verna-Ketel of Boise ID (US) for micron technology, inc., Hyun Yoo Lee of Boise ID (US) for micron technology, inc., Smruti Subhash Jhaveri of Boise ID (US) for micron technology, inc., John Christopher Sancon of Boise ID (US) for micron technology, inc., Yang Lu of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/40, G06F13/16
Abstract: described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. a controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. in some situations, however, individualized training may be infeasible. to accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. a timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. the multiple dice may be stacked or linked.
20240070102.Bus Training with Interconnected Dice_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Creston M. Dupree of San Jose CA (US) for micron technology, inc., Smruti Subhash Jhaveri of Boise ID (US) for micron technology, inc., Hyun Yoo Lee of Boise ID (US) for micron technology, inc., John Christopher Sancon of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc., Francesco Douglas Verna-Ketel of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/40, G06F13/16
Abstract: described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. a controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. in some situations, however, individualized training may be infeasible. to accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. a timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. the multiple dice may be stacked or linked.
Inventor(s): Dmitri Yudanov of Rancho Cordova CA (US) for micron technology, inc., Troy Allen Manning of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F13/42, G06F13/32
Abstract: systems, methods, and apparatus related to memory devices. in one approach, a memory device includes memories that store data received from a host device. the memory device includes a memory interface to the host device. the memory device further includes one or more processing devices to perform, using a portion of the data stored in one or more of the memories, computations for a neural network. an output of the neural network is stored in one of the memories. the memory device has a controller that controls memory access by the host device and the processing devices to avoid a conflict. the memory device communicates with the host device over the memory interface using a dram bus protocol. this communication includes sending the output of the neural network to the host device.
Inventor(s): Bryan Hornung of Plano TX (US) for micron technology, inc., Douglas Vanesko of Dallas TX (US) for micron technology, inc., David Patrick of McKinney TX (US) for micron technology, inc.
IPC Code(s): G06F15/80, G06F9/30
Abstract: devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. a system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.
20240070115.Multi-Threaded, Self-Scheduling Processor_simplified_abstract_(micron technology, inc.)
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F15/82, G06F9/30, G06F9/48, G06F9/50, G06F12/0875, G06F13/40
Abstract: representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. in another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.
Inventor(s): Carla L. Christensen of Garden Valley ID (US) for micron technology, inc., Venkata Kiran Kumar Matturi of Milpitas CA (US) for micron technology, inc., Tara Gordon of San Francisco CA (US) for micron technology, inc.
IPC Code(s): G06F16/9535, G06F16/9536, G06F16/9538, G06N3/063, G06N3/08
Abstract: a processor of a host can define a plurality of relationships in a virtual environment. the processor of the host can also provide the plurality of inputs describing look preferences to an ai accelerator. the ai accelerator can receive the inputs. the ai accelerator can also generate a plurality of looks based on the plurality of relationships and the plurality of inputs.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): G06F21/53, G06F21/64
Abstract: in some aspects, the techniques described herein relate to a device including: a storage device, the storage device including a first physically unclonable function (puf) and configured to generate a storage device public key and a storage device private key; and a secure environment, the secure environment including a controller configured for: transmitting a nonce value to the storage device; receiving a response from the storage device, the response including a unique identifier (uid) and a digital signature, the digital signature generated using the uid and the nonce value; validating the digital signature using a public key of the storage device; and issuing a command to the storage device after validating the digital signature.
20240070283.SECURE BOOT PROCEDURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Alessandro Orlando of Milano (IT) for micron technology, inc., Niccolò Izzo of Vignate (IT) for micron technology, inc., Angelo Alberto Rovelli of Agrate Brianza (IT) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc., Federica Cresci of Milan (IT) for micron technology, inc., Craig A. Jones of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F21/57
Abstract: protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. while the boot firmware is being verified and executed at a secure sub-system, an open sub-system can be put into a halt state, during which the open sub-system is prevented from performing the boot procedure. the open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified and/or executed unless the open sub-system is put into the resume state again.
20240070284.SECURE BOOT PROCEDURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Alessandro Orlando of Milano (IT) for micron technology, inc., Niccolò Izzo of Vignate (IT) for micron technology, inc., Angelo Alberto Rovelli of Agrate Brianza (IT) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc., Federica Cresci of Milan (IT) for micron technology, inc., Craig A. Jones of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F21/57
Abstract: protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. while the boot firmware is being verified, an open sub-system can be placed into a halt state, during which the open sub-system is prevented from performing the boot procedure. the open sub-system can be subsequently placed into a resume state to further perform the boot procedure when the boot firmware is verified. the open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified unless the open sub-system is placed into the resume state again.
Inventor(s): Saideep TIKU of Folsom CA (US) for micron technology, inc., Poorna KALE of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F40/274, G06V30/244, G06F3/01, G06T19/00
Abstract: in some implementations, an extended reality (xr) device may detect, using a scene captured by the xr device, text associated with a document, wherein the text associated with the document is within a field of view of the xr device. the xr device may determine one or more keywords of the text and a context associated with the text. the xr device may generate, using a language model, predicted text based on the one or more keywords of the text and the context associated with the text, wherein the predicted text is related to the text associated with the document. the xr device may provide, via an interface of the xr device, the predicted text as a visual overlay to the text associated with the document, wherein the predicted text is visually overlayed in proximity to the text associated with the document.
Inventor(s): Mritunjay Kumar of Bhagalpur (IN) for micron technology, inc., Tejashri Kelhe of Pune (IN) for micron technology, inc., Nidhi Nika of Sitamarhi (IN) for micron technology, inc.
IPC Code(s): G06N20/00
Abstract: a system includes a memory and a processing device, operatively coupled to the memory, to perform operations including obtaining a set of base features associated with tabular data, selecting, from the set of base features, a set of relevant features using attention-based feature selection, wherein the set of relevant features is a subset of the set of base features, generating, from the set of relevant features using feature interaction, a set of interaction features, and generating a prediction using the set of interaction features.
Inventor(s): Saideep TIKU of Folsom CA (US) for micron technology, inc., Poorna KALE of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06Q10/08, G06Q30/02, G06Q30/06
Abstract: in some implementations, an extended reality (xr) device may receive, from a server, a request to resolve an item that is misplaced in a physical retail store, wherein the request indicates a misplaced location associated with the item. the xr device may provide, via an interface, a notification of the request, wherein the notification includes an option to accept the request. the xr device may receive, via the interface, an indication that the request has been accepted. the xr device may transmit, to the server, the indication that the request has been accepted. the xr device may provide, via the interface, an in-store navigation path to direct a user of the xr device via overlayed audio-visual cues to the misplaced location to pick up the item.
Inventor(s): Saideep TIKU of Folsom CA (US) for micron technology, inc., Poorna KALE of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06Q30/02, G06Q10/08, G06Q30/06
Abstract: in some implementations, an extended reality (xr) device may receive, via an interface of the xr device, an indication of items to be purchased. the xr device may identify one or more physical retail stores that carry the items. the xr device may identify one or more recommended items based on the theme. the xr device may provide, via the interface, a list of the one or more physical retail stores. the xr device may detect that the xr device is within a physical retail store, of the one or more physical retail stores, based on a geographic location associated with the xr device. the xr device may provide, via the interface, an in-store navigation path to direct a user of the xr device via overlayed audio-visual cues to locations within the physical retail store at which the items are held.
Inventor(s): John D. Hopkins of Milpitas CA (US) for micron technology, inc., Mohad Baboli of Boise ID (US) for micron technology, inc.
IPC Code(s): G06Q30/06, G06Q20/32, G06Q20/40, G06T19/00, G06V20/20
Abstract: methods, apparatus, and non-transitory machine-readable media associated with sale of virtual goods based on physical location are described. an apparatus can include a memory device and a processing device communicatively coupled to the memory device. the processing device can detect a computing device within a threshold radius of a first physical location, display a virtual environment associated with the physical location via a user interface of the computing device, and provide a virtual good for sale via the user interface based on a second physical location of the computing device within the first physical location.
Inventor(s): Xinyu Wu of Boise ID (US) for micron technology, inc., Timothy Paul Finkbeiner of Boise ID (US) for micron technology, inc., Peter Lawrence Brown of Eagle ID (US) for micron technology, inc., Troy Dale Larsen of Meridian ID (US) for micron technology, inc., Glen Earl Hush of Boise ID (US) for micron technology, inc., Troy Allen Manning of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06T1/60, G06N3/063, G06T7/10, G06V10/82
Abstract: systems, methods, and apparatus related to memory devices. in one approach, an artificial intelligence system uses a memory device to provide inference results. image data from a camera is provided to the memory device. the memory device stores the image data received from the camera. the memory device includes dynamic random access memory (dram), and static random access memory (sram). the memory device also includes a processor to run a neural network. the neural network uses the image data as input. an output from the neural network provides an inference result. in one example, the memory device has a same form factor as a conventional dram device. the memory device includes a multiply-accumulate (mac) engine that supports computations for the neural network.
20240070893.OBJECT LOCATION DETERMINATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Maithilee Motlag of Boise ID (US) for micron technology, inc., Hope Henry of Boise ID (US) for micron technology, inc., Nkiruka Christian of Bristow VA (US) for micron technology, inc., Chiara Cerafogli of Boise ID (US) for micron technology, inc.
IPC Code(s): G06T7/70, G06T1/60, G06V10/44, G06V10/74
Abstract: methods, apparatuses, and non-transitory machine-readable media associated with determining a location of an object are described. an object location determination can include receiving a user request associated with an object, receiving first signaling from a first image source, and receiving second signaling from a second image source. the object location determination can include writing data that is based at least in part on a combination of the user request, the first signaling, and the second signaling and determining a confidence level of identification of the object associated with the user request based on the user request, the first signaling, and the second signaling. the object location determination can include identifying output data representative of a location of the object based on the confidence level and transmitting the output data representative of the location of the object via third signaling.
Inventor(s): Saideep TIKU of Folsom CA (US) for micron technology, inc., Poorna KALE of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06T19/00, G06Q30/06, G06V20/68
Abstract: in some implementations, an extended reality (xr) device may receive, via an interface of the xr device, an input associated with meals of a user associated with the xr device. the xr device may determine, based on the input, a meal plan for the user of the xr device, wherein the meal plan is associated with target meals. the xr device may determine, based on recipes for the target meals, a list of food items for preparing the target meals associated with the meal plan. the xr device may provide, via the interface, the list of food items and the target meals. the xr device may provide, via the interface, an in-store navigation path to direct the user of the xr device via overlayed audio-visual cues to locations within a physical retail store to pick up the food items.
Inventor(s): Saideep TIKU of Folsom CA (US) for micron technology, inc., Poorna KALE of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06T19/20, G06V20/20, G06V20/64
Abstract: in some implementations, an extended reality (xr) device may detect, using a camera of the xr device, a clothing item, wherein the clothing item is associated with an identifier. the xr device may transmit, to a server, a request that indicates the identifier. the xr device may receive, from the server, metadata associated with the clothing item, wherein the metadata is associated with the identifier. the xr device may retrieve, from the server, a three-dimensional model of a user associated with the xr device. the xr device may generate a three-dimensional model of the user wearing the clothing item using the three-dimensional model of the user and the metadata. the xr device may provide, via an interface of the xr device, the three-dimensional model of the user wearing the clothing item.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Mingdong Cui of Folsom CA (US) for micron technology, inc., Richard E. Facekenthal of Carmichael CA (US) for micron technology, inc.
IPC Code(s): G11C5/02, G11C5/06, G11C8/14, H01L27/108
Abstract: methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. a memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. for example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.
Inventor(s): Hirokazu Ato of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C5/06, H01L23/522, H01L23/528, H01L23/532
Abstract: apparatuses and methods including folded digit lines are disclosed. an example apparatus includes a first digit line portion extending in a first direction, a second digit line portion extending in the first direction, and a third digit line portion between the first and second digit line portions and extending in the first direction. a folded portion is coupled to the first and second digit line portions, and extends in a second direction and traverses the third digit line portion.
Inventor(s): Andrea Giovanni Xotta of Cornedo Vicentino (IT) for micron technology, inc., Umberto Siciliani of Rubano (IT) for micron technology, inc., Tommaso Vali of Sezze (IT) for micron technology, inc.
IPC Code(s): G11C7/04, G11C7/10
Abstract: control logic in a memory device receives, from a requestor, a request to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored and performs, using previously configured read operation parameters, a first read operation to read the data and a write temperature associated with the data from the memory array. the control logic determines whether the previously configured read operation parameters satisfy a temperature criterion and responsive to determining that the previously configured read operation parameters do not satisfy the temperature criterion, configures the memory device with updated read operation parameters, and performs, using the updated read operation parameters, a second read operation to read the data from the memory array.
Inventor(s): Jiewei Chen of Meridian ID (US) for micron technology, inc., Mithun Kumar Ramasahayam of Meridian ID (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.
Inventor(s): Si Hong Kim of Boise ID (US) for micron technology, inc., John D. Porter of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/22, G11C8/08
Abstract: systems and method for sensing an accessed voltage value associated with a memory cell is described. in different embodiments, a memory array may include a different number of sense components. moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. for example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.
20240071434.DRIFT COMPENSATION FOR CODEWORDS IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Luca Barletta of Gallarate (IT) for micron technology, inc., Marco Pietro Ferrari of Milano (IT) for micron technology, inc., Antonino Favano of Brolo (IT) for micron technology, inc.
IPC Code(s): G11C7/10, G11C11/56
Abstract: systems, methods, and apparatuses are provided for drift compensation for codewords in memory. a memory device comprises memory cells and circuitry configured to sense a codeword stored in the memory cells. the circuitry is further configured to determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on a summation of a threshold voltage value of each of the memory cells, a mean of the threshold voltage values of the memory cells, and a value proportional to the mean of the threshold voltage values of the memory cells. the circuitry is further configured to determine which cell metric of each of the memory cells has a lowest value, input that cell metric into a pearson detector, and determine the originally programmed data of the codeword using the pearson detector.
Inventor(s): Phong Sy Nguyen of Livermore CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc., Dung Viet Nguyen of San Jose CA (US) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc.
IPC Code(s): G11C7/10
Abstract: systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. the control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.
Inventor(s): Kallol Mazumder of Dallas TX (US) for micron technology, inc., Navya Sri Sreeram of Plano TX (US) for micron technology, inc.
IPC Code(s): G11C7/10
Abstract: a memory device includes a command interface configured to receive write commands from a host device. the memory device also includes an input buffer configured to buffer data from the host device. additionally, the memory device includes a state machine configured to receive a command into a first partition of the state machine and to enable a data strobe (dqs) input buffer in response to the indication. the state machine is also configured to maintain the enablement of the dqs input buffer while the command traverses the state machine. furthermore, the state machine is configured to disable the dqs input buffer after a set duration of time.
20240071437.Die Disablement_simplified_abstract_(micron technology, inc.)
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/20
Abstract: described apparatuses and methods relate to selectively disabling a die that may be included in a multiple-die package without necessarily disabling all the remaining dies within the package. a nonvolatile circuit, such as one or more fuses, may be included within individual dies and/or otherwise incorporated within the package. the nonvolatile circuit maintains a value for the die that is indicative of the operability of the die. die disablement logic is operatively coupled to the nonvolatile circuit and can disable the die based on the value indicating that the die is unusable. the disabling of the die by the die disablement logic may be controlled by an override signal that allows the disabling or prevents the logic from disabling the die. thus, the die disablement logic can prevent a defective die from functioning, but the die disablement logic may be overridden for testing or debugging.
Inventor(s): Robert W. Mason of Boise ID (US) for micron technology, inc., Pitamber Shukla of Boise ID (US) for micron technology, inc., Steven Michael Kientz of Westminster CO (US) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/22
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.
Inventor(s): Abhilash Ramamurthy Nag of Bangalore (IN) for micron technology, inc., Suresh Reddy Yarragunta of Bangalore (IN) for micron technology, inc., Shiva Pahwa of Bangalore (IN) for micron technology, inc.
IPC Code(s): G11C7/10, G06N20/00, G11C29/52
Abstract: exemplary methods, apparatuses, and systems include an environmental operations manager for controlling memory access of the memory device. the environmental operations manager receives a set of data bits for programming to a memory location. the environmental operations manager receives environmental condition data. the environmental operations manager delays programming of the set of data bits to the memory location and writing the set of data bits to a buffer location in response to determining that the environmental condition data satisfies a threshold.
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc.
IPC Code(s): G11C7/24, G11C7/10
Abstract: systems, apparatus, and methods related to configurable data protection circuitry. a memory includes a plurality of memory devices and a memory controller that can be coupled to the memory via a plurality of channels. the channels comprise respective subsets of the plurality of memory devices. the memory controller comprises data protection circuitry to accommodate a first codeword configuration of a number of codewords responsive to the plurality of memory devices having a first operating mode corresponding to a first input/output (i/o) width and accommodate a second codeword configuration of the number of codewords responsive to the plurality of memory devices having a second operating mode corresponding to a second i/o width, as well as switch between the first operating mode of the plurality of memory devices and the second operating mode of the plurality of memory devices.
20240071454.Word Line Precharging Systems and Methods_simplified_abstract_(micron technology, inc.)
Inventor(s): Angelo Visconti of Appiano (IT) for micron technology, inc.
IPC Code(s): G11C11/22
Abstract: systems and methods described herein may enable a memory system to selectively provide a signal boost to a word line to precharge the word line. a memory device may include voltage shaping circuitry and a memory controller. the memory controller may cause the voltage shaping circuitry to adjust a characteristic of a word line select control signal transmitted via the word line prior to the word line select control signal being transmitted to a memory cell.
Inventor(s): Si Hong Kim of Boise ID (US) for micron technology, inc., John D. Porter of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/22
Abstract: systems and method for sensing an accessed voltage value associated with a memory cell is described. in different embodiments, a memory array may include a different number of sense amplifiers. moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. for example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. as such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.
20240071459.ROW TRACKING FOR ROW HAMMER MITIGATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Emanuele Confalonieri of Segrate (IT) for micron technology, inc., Yaw Fann of San Jose CA (US) for micron technology, inc., Yu-Sheng Hsu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C11/406, G06F3/06
Abstract: a control mechanism may be implemented in a back-end of a memory sub-system to refresh rows of a memory device. rows of the memory device can be refreshed based on a quantity of times the rows have been updated in a duration of time. rows of the memory device can also be updated based on a duration of time between receipt of the activation command for the row and a pre-charge command for the row. row of the memory device clan further be updated utilizing a pair of counters that implement a ping pong mechanism to retain data between different consecutive durations of time.
20240071461.Adaptive Memory Registers_simplified_abstract_(micron technology, inc.)
Inventor(s): John Christopher Sancon of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc., Yang Lu of Boise ID (US) for micron technology, inc., Hyun Yoo Lee of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/4096
Abstract: described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. to help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. the values indicate whether an associated memory block has been refreshed within a refresh interval. other logic can read the registers to determine whether a block has been refreshed. the device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. the register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. these techniques can reduce the number of refresh operations performed, saving power and reducing costs.
Inventor(s): Tingjun Xie of Milpitas CA (US) for micron technology, inc., Yang Liu of San Jose CA (US) for micron technology, inc., Juane Li of Milpitas CA (US) for micron technology, inc., Aaron Lee of Sunnyvale CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/4096
Abstract: a processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. for every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. a non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. for every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.
20240071464.Dynamic Address Scramble_simplified_abstract_(micron technology, inc.)
Inventor(s): Erik T. Barmon of Boise ID (US) for micron technology, inc., Yang Lu of Boise ID (US) for micron technology, inc., Nathaniel J. Meier of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C7/24, G11C29/18, G11C29/56
Abstract: described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. the address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. in aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. the described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Mingdong Cui of Folsom CA (US) for micron technology, inc., Richard E. Fackenthal of Carmichael CA (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C5/02, G11C11/4091
Abstract: methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. a memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. for example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include a gate material operable to modulate a conductivity between the first portions and the second portions. each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material may couple the word lines with the respective second portion of the semiconductor material. such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Mingdong Cui of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C11/22, H01L23/00, H01L25/00, H01L25/065, H01L25/18
Abstract: methods, systems, and devices for word line drivers for multiple-die memory devices are described. a memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. the second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. for example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Mingdong Cui of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C11/408, H10B80/00
Abstract: methods, systems, and devices for word line drivers for multiple-die memory devices are described. a memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. the second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. for example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.
Inventor(s): Fatma Arzum SIMSEK-EGE of Boise ID (US) for micron technology, inc., Mingdong CUI of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C11/22, H01L23/00, H01L25/00, H01L25/065, H01L25/18
Abstract: methods, systems, and devices for word line drivers for multiple-die memory devices are described. a memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. the second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. for example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.
Inventor(s): Tae H. Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C11/4074, G11C11/4093
Abstract: memory with single transistor sub-word line drivers, and associated systems, devices, and methods are disclosed herein. in one embodiment, an apparatus comprises a plurality of first sub-word line drivers and a plurality of second sub-word line drivers. each sub-word line driver of the plurality of first sub-word line drivers is coupled to (a) a first global word line and (b) a corresponding one of a plurality of first local word lines. each sub-word line driver of the plurality of second sub-word line drivers is coupled to (a) a second global word line different from the first global word line and (b) a corresponding one of a plurality of second local word lines. in addition, individual ones of the plurality of first local word lines are interleaved with individual ones of the plurality of second local word lines.
Inventor(s): Jaeil Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/409, G06F11/10, G11C11/408
Abstract: a memory device comprises memory and control circuitry. the control circuitry can receive a command to access the memory. responsive to receiving the command to access the memory, the control circuitry can provide command data of the command to pipelatch circuitry and error correction code (ecc) circuitry. the memory device further includes pipelatch circuitry to receive command data of the command from the control circuitry and maintain the command data for a period of time of a duration longer than error calculation time of the ecc circuitry.
Inventor(s): KYOICHI NAGATA of Kawasaki (JP) for micron technology, inc.
IPC Code(s): G11C11/4091
Abstract: an apparatus that includes a sense amplifier including first and second cross-coupled transistors to amplify a potential difference between first and second digit lines, a compensation circuit configured to compensate a threshold difference between the first and second transistors, first and second local i/o lines coupled to the first and second digit lines, respectively, and an equalizing circuit configured to equalize the first and second local i/o lines. the equalizing circuit is configured to change a precharge level of the first and second local i/o lines from a first potential to a second potential before a compensation operation of the compensation circuit is completed.
Inventor(s): Yuan He of Boise ID (US) for micron technology, inc., Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/408
Abstract: a microelectronic device is disclosed that incudes array regions individually comprising memory cells comprising access devices and storage node devices; digit lines coupled to the access devices that extend in a first direction; and word lines coupled to the access devices that extend in a second direction orthogonal to the first direction. digit line exit regions horizontally alternate with the array regions in the first direction; sense amplifier sections comprising sense amplifier circuitry vertically overlie and horizontally overlapping the digit line exit regions; and routing structures within horizontal areas of the digit line exit regions, couple the sense amplifier circuitry of the sense amplifier sections to the digit lines.
Inventor(s): Andrea Martinelli of Bergamo (BG) (IT) for micron technology, inc., Christophe Vincent Antoine Laurent of Agrate Brianza (MB) (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc., Efrem Bolandrina of Fiorano al Serio (BG) (IT) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/408, G11C11/4091
Abstract: systems, methods, and apparatus for a memory device. in one approach, a memory device selectively enters a streaming mode when accessing memory cells in a memory array. a controller determines for new read operations whether memory cells will be accessed in a streaming mode or in a random mode. first memory cells addressed using a wordline are read by the controller. the wordline is charged to an initial voltage for reading the first memory cells. when in the streaming mode, instead of discharging the wordline after reading the first memory cells, as is done for a random mode, the controller keeps a minimum bias on the wordline and returns the wordline again to the initial voltage for performing a next read operation to read second memory cells. this saves memory device power.
Inventor(s): Christophe Vincent Antoine Laurent of Agrate Brianza (MB) (IT) for micron technology, inc., Francesco Mastroianni of Melzo (MI) (IT) for micron technology, inc., Andrea Martinelli of Bergamo (BG) (IT) for micron technology, inc., Efrem Bolandrina of Fiorano al Serio (BG) (IT) for micron technology, inc., Lucia Di Martino of Monza (MB) (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (MB) (IT) for micron technology, inc., Zhongyuan Lu of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Nevil N. Gajera of Meridian ID (US) for micron technology, inc.
IPC Code(s): G11C11/56, G06F3/06, G06F12/02
Abstract: disclosed are techniques for correcting drift accumulation in memory cells. in some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.
Inventor(s): Massimo Ernesto Bertuccio of San Donato Milanese (IT) for micron technology, inc., Sead Zildzic, JR. of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C11/56, G11C16/04, G11C16/10
Abstract: a memory device includes an array of memory cells, a plurality of access lines, and a controller. the array of memory cells includes a plurality of strings of series-connected memory cells. each access line is connected to a control gate of a respective memory cell of each string of series-connected memory cells. the controller is configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a first target level. the controller is further configured to apply a first voltage level to a first access line connected to the selected memory cell, and apply a second voltage level higher than the first voltage level to a second access line adjacent to the first access line. the controller is further configured to apply a third voltage level between the first voltage level and the second voltage level to a third access line adjacent to the first access line and connected to an erased memory cell, and sense a first threshold voltage of the selected memory cell.
20240071486.DRIFT COMPENSATION FOR CODEWORDS IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Luca Barletta of Gallarate (IT) for micron technology, inc., Marco Pietro Ferrari of Milano (IT) for micron technology, inc., Antonino Favano of Brolo (IT) for micron technology, inc.
IPC Code(s): G11C11/56, G11C5/14
Abstract: the present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. an embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a derivative value of a cell metric for each cell of the codeword based on a threshold voltage of that respective cell, a mean of threshold voltage values of each cell of the codeword, and a value proportional to a total quantity of the cells of the codeword and a position of the threshold voltage value of that respective cell in the threshold voltage values of each cell of the codeword, determine the cell metric for which the determined derivative value changes from a first polarity to a second polarity, input the determined cell metric to a pearson detector, and determine originally programmed data of the codeword using the pearson detector.
20240071487.DRIFT COMPENSATION FOR CODEWORDS IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Luca Barletta of Gallarate (IT) for micron technology, inc., Marco Pietro Ferrari of Milano (IT) for micron technology, inc., Antonino Favano of Brolo (IT) for micron technology, inc.
IPC Code(s): G11C11/56, G11C11/4074, G11C11/4099
Abstract: systems, methods, and apparatuses are provided for drift compensation for codewords in memory. a memory device comprises memory cells and circuitry configured to sense a codeword stored in the array of memory cells using a reference voltage and determine an amount by which to adjust the reference voltage used to sense the codeword based on an estimated weight of the original codeword, a mean of threshold voltage values of each memory cell of the sensed codeword, and a total quantity of memory cells of the sensed codeword. the circuitry can further be configured to adjust the reference voltage used to sense the codeword by the determined amount.
Inventor(s): Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc.
IPC Code(s): G11C13/00
Abstract: systems and methods for reading a first and second plurality of memory cells include applying a first ramping voltage with a first increment for each ramping step to read the first plurality of cells, counting, among the first plurality of cells at each ramping step, a first number of logic 1 cells, comparing the first number with a threshold at each ramping step of the first ramping voltage, determining a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the threshold for the first time, applying a second voltage lower than the first voltage to read the second plurality of cells, and applying a second ramping voltage ramping up from the second voltage with a second predetermined increment lower than the first predetermined increment for each ramping step to read the second plurality of cells.
Inventor(s): Umberto di Vincenzo of Capriate San Gervasio (BG) (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc., Michele Maria Venturini of Milan (MI) (IT) for micron technology, inc., Claudia Palattella of Cologno Monzese (MI) (IT) for micron technology, inc.
IPC Code(s): G11C13/00
Abstract: systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.
Inventor(s): Zhongyuan Lu of Boise ID (US) for micron technology, inc., Robert John Gleixner of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C13/00
Abstract: systems, methods, and apparatus to select an enhanced write pulse for a write operation in a memory device. in one approach, stronger reset pulses are triggered when there is an increased risk of memory cell threshold voltage degradation. memory cells read by a relatively higher number of read operations are recorded by a controller of a memory device by updating a lookup table with addresses of the memory cells read. for a new write operation, the controller determines if a reset on set write operation is to be performed. the controller also searches the lookup table to determine if an address for the target bits or codeword of the write operation are in the lookup table. if both conditions are satisfied, then the magnitude of the write pulse is increased for programming the memory cells.
Inventor(s): Jiewei Chen of Meridian ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc., Shuangqiang Luo of Boise ID (US) for micron technology, inc., Silvia Borsari of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L23/522, H01L23/528, H01L27/11565, H01L27/1157, H01L27/11582
Abstract: memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. the insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. the stair-step region comprises a cavity comprising a flight of stairs having insulative material atop treads of the stairs. individual of the treads comprise conducting material of one of the conductive tiers. conductive vias extend through the insulative material. individual of the conductive vias are directly above and directly against the conducting material of the respective individual tread. a lining is over sidewalls of the individual conductive vias. the lining has a bottom. the individual conductive vias are directly under the bottom of the lining directly above the conducting material of the respective individual tread. other embodiments, including method, are disclosed.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L27/11519, H01L27/11524, H01L27/11556, H01L27/11565, H01L27/1157, H01L27/11582
Abstract: memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. the insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. the stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. the cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction. the multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls. methods are disclosed.
20240071497.SELF-SUPPORTING SGD STADIUM_simplified_abstract_(micron technology, inc.)
Inventor(s): Anna Maria Conti of Milano (IT) for micron technology, inc., Umberto Maria Meotto of Dietlikon (CH) for micron technology, inc., Domenico Tuzi of Balsorano (IT) for micron technology, inc.
IPC Code(s): G11C16/04, H01L27/11524, H01L27/11556, H01L27/1157, H01L27/11582
Abstract: a variety of applications can include apparatus having memory devices, where at least one of the memory devices is a three-dimensional memory device having levels of pillars to support pillars of memory cells and one or more drain-end select gate (sgd) transistors of the memory array of the memory device. the levels of pillars are structured as a progression of pillars, where each pillar of one level is structured on and extending vertically from a different pillar of a level on which the one level is located. sgd select lines for coupling to the one or more sgd transistors are structured in a sgd stadium, where the sgd stadium is located within at least a portion of the progression of pillars.
Inventor(s): Yongjun Jeff Hu of Boise ID (US) for micron technology, inc., Pengyuan Zheng of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L23/522, H01L23/528, H01L27/11519, H01L27/11524, H01L27/11556, H01L27/11565, H01L27/1157, H01L27/11582
Abstract: a memory array comprising strings of memory cells comprises a conductor tier. the conductor tier comprises upper conductor material directly above and directly against lower conductor material of different composition from that of the upper conductor material. the channel-material strings directly electrically couple to the upper and lower conductor materials of the conductor tier. a through-array-via (tav) region is included and comprises tavs. the tavs individually comprise the upper conductor material, the lower conductor material, and a conducting material that is directly below the conductor tier. the lower conductor material is directly against the upper conductor material and directly against the conducting material. the lower conductor material comprises a metal-rich refractory metal nitride directly above and directly against a non-metal-rich refractory metal nitride that is directly against the conducting material. the lower conductor material may also comprise a first elemental-form metal directly above and directly against a second elemental-form metal that is directly against the conducting material methods are also disclosed.
Inventor(s): Jae Kyu Choi of Boise ID (US) for micron technology, inc., Jin Yue of Boise ID (US) for micron technology, inc., Kyubong Jung of Boise ID (US) for micron technology, inc., Albert Fayrushin of Boise ID (US) for micron technology, inc., Jae Young Ahn of Boise ID (US) for micron technology, inc., Jun Kyu Yang of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
Abstract: memory array structures, and methods of their formation, might include a first memory cell having a first control gate and an adjacent first portion of a charge-blocking structure, a second memory cell having a second control gate and an adjacent second portion of the charge-blocking structure, and a first dielectric material between the first control gate and the second control gate, and adjacent to a third portion of the charge-blocking structure that is between the first and second portions of the charge-blocking structure. the third portion of the charge-blocking structure might include a second dielectric material and a third dielectric material different than the second dielectric material, and the first portion of the charge-blocking structure and the second portion of the charge-blocking structure might each include the third dielectric material and a fourth dielectric material different than the second dielectric material. apparatus might include such memory array structures.
Inventor(s): Lifang Xu of Boise ID (US) for micron technology, inc., Umberto Maria Meotto of Dietlikon (CH) for micron technology, inc., Aaron S. Yip of Los Gatos CA (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L23/528, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
Abstract: microelectronic devices include a stack having a vertically alternating sequence of insulative and conductive structures arranged in tiers. slit structures extend through the stack, dividing the stack into blocks. a first series of stadiums—within the stack of a first block of a pair of the blocks—includes at least one stadium having multiple parallel sets of staircases. a second series of stadiums—within the stack of a second block of the pair of blocks—includes at least one additional stadium having additional multiple parallel sets of staircases that are mirrored, across one of the slit structures, to the multiple parallel sets of staircases of the first series. in methods of fabrication, common mask openings are used to form the mirrored staircase profiles once stadiums are already at substantially their final depths in the stack structure. electronic systems are also disclosed.
20240071502.STAIRCASE FORMATION IN A MEMORY ARRAY_simplified_abstract_(micron technology, inc.)
Inventor(s): Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/08, H01L21/768, H01L27/1157, H01L27/11578
Abstract: methods, systems, and devices for staircase formation in a memory array are described. a first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. a second liner material may be deposited over the first liner and a portion of the second liner material may be doped. after doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. the doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).
20240071503.PADDING IN FLASH MEMORY BLOCKS_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/08, G11C16/04, G11C16/10
Abstract: a method includes determining a boundary word line in a partial block of a flash memory device, where the partial block includes blank word lines after the boundary word line; determining a single predefined level of pure data to write in at least one of the blank word lines after the boundary word line; and writing the single predefined level of pure data to at least one of the blank word lines after the boundary word line.
Inventor(s): Jiewei Chen of Meridian ID (US) for micron technology, inc., Mithun Kumar Ramasahayam of Meridian ID (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., June Lee of Sunnyvale CA (US) for micron technology, inc., Luyen Vu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08
Abstract: control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. the control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. in addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.
20240071506.PARTIAL BLOCK READ VOLTAGE OFFSET_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhongguang XU of San Jose CA (US) for micron technology, inc., Murong LANG of San Jose CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc., Ugo RUSSO of Boise ID (US) for micron technology, inc., Niccolo' RIGHETTI of Boise ID (US) for micron technology, inc., Nicola CIOCCHINI of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/16, G11C16/28
Abstract: a memory device may include a memory and a controller. the controller may be configured to receive a read command associated with a block of the memory. the controller may be configured to determine a block type associated with the block. the controller may be configured to identify, based on the block type, one or more read voltage offsets for a read operation associated with the block. the controller may be configured to perform the read operation based on the one or more read voltage offsets.
Inventor(s): Koichi Kawai of Yokohama (JP) for micron technology, inc., Yoshihiko Kamata of Yokohama (JP) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C16/10, G11C7/10, G11C16/34, H03K19/017
Abstract: memories might include a controller configured to cause the memory to apply a first voltage level indicative of a data state of a memory cell of an array of memory cells to a control gate of a transistor, retain the first voltage level on the control gate of the transistor, connect a first source/drain of the transistor to a data line corresponding to the memory cell while applying a second voltage level to a second source/drain of the transistor and while retaining the first voltage level on the control gate of the transistor, and apply a programming pulse to a control gate of the memory cell while the data line is connected to the first source/drain of the transistor.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Giovanni Maria Paolucci of Milano (IT) for micron technology, inc., Dave Scott Ebsen of Minnetonka MN (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc., Umberto Siciliani of Rubano (IT) for micron technology, inc., Daniel J. Hubbard of Boise ID (US) for micron technology, inc., Walter Di Francesco of Avezzano (IT) for micron technology, inc., Michele Incarnati of Avezzano (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/34
Abstract: exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. the programming manager receives a first set of data bits for programming to memory. the programming manager writes a first subset of data bits to a first wordline during a first pass of programming. the programming manager writes a second subset of data bits of the first set of data bits to a buffer. the programming manager receives a second set of data bits for programming. the programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.
20240071511.DRIFT COMPENSATION FOR CODEWORDS IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Luca Barletta of Gallarate (IT) for micron technology, inc., Marco Pietro Ferrari of Milano (IT) for micron technology, inc., Antonino Favano of Brolo (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/12, G11C16/34
Abstract: the present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. an embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a threshold voltage value of each cell of the codeword, sort the threshold voltage values, determine a second derivative value of a cell metric for a number of the cells of the codeword based on the threshold voltage value of that respective cell, the threshold voltage value immediately preceding the threshold voltage value of that respective cell in the sorted values, and a value proportional to a total quantity of the cells of the codeword, determine the cell metric for which the determined second derivative value has a greatest value, input the determined cell metric to a pearson detector, and determine originally programmed data of the codeword using the pearson detector.
Inventor(s): Phil REUSSWIG of Fremont CA (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/24, G11C16/34
Abstract: aspects of the present disclosure configure a memory sub-system processor to manage memory erase operations. the processor accesses a configuration register to identify a quantity of memory slices to erase. the processor divides a set of memory components into a plurality of portions based on the identified quantity of memory slices to erase and performs one or more read operations in association with the memory sub-system between erasure of each of the plurality of portions of the set of memory components.
20240071514.NAND DETECT EMPTY PAGE SCAN_simplified_abstract_(micron technology, inc.)
Inventor(s): Christina PAPAGIANNI of San Jose CA (US) for micron technology, inc., Murong LANG of San Jose CA (US) for micron technology, inc., Peng ZHANG of Los Altos CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/08, G11C16/34
Abstract: a controller of a memory device may identify a plurality of word line groups, included in a block of a memory of the memory device, that include erased pages of the block. the controller may identify a subset of word line groups, of the plurality of word line groups, for a nand detect empty page (ndep) scan operation. the controller may perform, based on identifying the subset of word line groups, the ndep scan operation for the subset of word line groups. a voltage threshold for the ndep scan may be based on an offset voltage that can be adaptive based on parameters such as quantity of program-erase cycles, memory cell type, and/or operating temperature, among other examples.
Inventor(s): Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Vinh Quang Diep of Hayward CA (US) for micron technology, inc., Avinash Rajagiri of Boise ID (US) for micron technology, inc., Yingda Dong of Los Altos CA (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/04
Abstract: control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. during a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. during the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. during a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line. during the subset of erase loops, a first adjusted erase bias voltage is caused to be applied to the first select gate and a second adjusted erase bias voltage is caused to be applied to the second select gate.
20240071516.DISCHARGE CIRCUITS_simplified_abstract_(micron technology, inc.)
Inventor(s): Kenneth W. Marr of Boise ID (US) for micron technology, inc., James E. Davis of Meridian ID (US) for micron technology, inc., Chiara Cerafogli of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/22, G11C16/04, G11C16/16
Abstract: a discharge circuit includes a transistor and a metal resistor connected to the transistor. the transistor includes a plurality of unit cells. the metal resistor includes a plurality of resistor portions corresponding to the plurality of unit cells. each unit cell of the plurality of unit cells has a footprint and a corresponding resistor portion of the plurality of resistor portions is arranged within the footprint.
Inventor(s): Curtis Egan of Brighton CO (US) for micron technology, inc.
IPC Code(s): G11C16/26, G11C11/56
Abstract: methods, systems, and devices for coding to decrease error rate discrepancy between pages are described. for example, to identify a unit-distance code for operating a memory device, voltage drifts of a set of read voltages after a duration may be identified and each of the read voltages may be mapped to one of a set of pages of the memory cell using various possible unit-distance codes. thus, for each unit-distance code the set of pages may be associated with respective subsets of the set of read voltages. then, for each unit-distance code a set of average read voltage drifts corresponding to one of the set of pages may be identified. the memory device may be operated using a unit-distance code associated with a smaller range of the set of average read voltage drifts than ranges of sets of average read voltage drifts associated with other unit-distance codes.
Inventor(s): Shakeel Isamohiuddin BUKHARI of San Jose CA (US) for micron technology, inc., Mark ISH of Manassas VA (US) for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/16, G11C16/32
Abstract: implementations described herein relate to suspending memory erase operations to perform high priority memory commands. in some implementations, a memory device may detect, while an active stage of an erase operation is being performed by the memory device, a pending memory command with a higher priority than the erase operation. the memory device may selectively suspend the active stage of the erase operation, to allow the pending memory command to be executed, based on the active stage of the erase operation that is being performed and/or a value of a suspend determination timer associated with suspending the active stage of the erase operation.
Inventor(s): Dung Viet Nguyen of San Jose CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Zhengang Chen of San Jose CA (US) for micron technology, inc., Dheeraj Srinivasan of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/32, G11C29/52
Abstract: described are memory devices producing metadata characterizing the applied read voltage level with respect to voltage distributions. an example memory sub-system comprises: a memory device comprising a plurality of memory cells; and a controller coupled to the memory device, the controller to perform operations comprising: performing, using a read voltage level, a read strobe with respect to a subset of the plurality of memory cells; and receiving, from the memory device, one or more metadata values characterizing the read voltage level with respect to threshold voltage distributions of the subset of the plurality of memory cells, wherein the one or more metadata values reflect a conductive state of one or more bitlines connected to the subset of the plurality of memory cells.
Inventor(s): Nicola Ciocchini of Boise ID (US) for micron technology, inc., Animesh R. Chowdhury of Boise ID (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Jung Sheng Hoei of Newark CA (US) for micron technology, inc., Niccolo' Righetti of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/26
Abstract: methods, systems, and apparatuses include receiving a read command including a logical address. the read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. the physical address for the read command is identified using the logical address. the wordline group is determined using the physical address. a slope factor is retrieved using the wordline group. a read counter is incremented using the slope factor.
Inventor(s): Robert W. Mason of Boise ID (US) for micron technology, inc., Scott Anthony Stoller of Boise ID (US) for micron technology, inc., Pitamber Shukla of Boise ID (US) for micron technology, inc., Ekamdeep Singh of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.
Inventor(s): Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Hong-Yan Chen of San Jose CA (US) for micron technology, inc., Yingda Dong of Los Altos CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/10
Abstract: a program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. during a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. a pass through read voltage level associated with the target wordline is identified. during the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.
Inventor(s): Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., Hong-Yan Chen of San Jose CA (US) for micron technology, inc., Pamela Castalino of Boise ID (US) for micron technology, inc., Priya Vemparala Guruswamy of Boise ID (US) for micron technology, inc., Jun Xu of San Jose CA (US) for micron technology, inc., Gianluca Nicosia of Boise ID (US) for micron technology, inc., Ji-Hye Gale Shin of Palo Alto CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10, G11C16/12
Abstract: a memory device includes an array of memory cells and a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a target level based on a compensation value of a program command. the controller is further configured to sense a threshold voltage of the selected memory cell. the controller is further configured to in response to the compensation value having a first value and the threshold voltage being greater than a first program verify level, inhibit programming of the selected memory cell. the controller is further configured to in response to the compensation value having a second value different from the first value and the threshold voltage being greater than a second program verify level less than the first program verify level, inhibit programming of the selected memory cell.
Inventor(s): Nagendra Prasad Ganesh Rao of Folsom CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/12, G11C16/26
Abstract: control logic in a memory device receives a request to perform a read operation to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, initiates a failed byte count read operation on the segment of the memory array to determine a failed byte count, and reads metadata stored in a flag byte corresponding to the segment of the memory array concurrently with the failed byte count read operation. the control logic further configures one or more parameters associated with the read operation based on the failed byte count and at least a portion of the metadata read from the flag byte.
Inventor(s): Guang Hu of Mountain View CA (US) for micron technology, inc., Nicola Ciocchini of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/32
Abstract: a memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C7/10, G11C29/32
Abstract: apparatuses, systems, and methods for module level error correction. multiple memory devices a packaged together in a memory module. the module includes a module error correction code (ecc) circuit which pools information multiple memory devices on the module. in an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. the codewords may include data bits provided along a data bus and parity bits provided along a parity bus. the ecc circuit pools the codewords and detects errors in the pooled codewords.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/42
Abstract: apparatuses, systems, and methods for module level error correction. multiple memory devices a packaged together in a memory module. the module includes a module error correction code (ecc) circuit which pools information multiple memory devices on the module. in an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. the codewords may include data bits provided along a data bus and parity bits provided along a parity bus. the ecc circuit pools the codewords and detects errors in the pooled codewords.
Inventor(s): Li-Te Chang of San Jose CA (US) for micron technology, inc., Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Michael G. Miller of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C16/08, G11C16/10, G11C16/34
Abstract: an example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (bfea) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-bfea threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default bfea threshold voltage value, the sub-bfea threshold voltage value, and a corresponding base voltage level.
Inventor(s): Guang Hu of Mountain View CA (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/02, G11C29/04
Abstract: a method includes, in response to detecting a power on event, selecting a block from a set of blocks, causing a first scan to be performed using a set of read level offsets to select, from a set of bins in accordance with a scan order, a first bin assigned with a first read level offset resulting in a first bit error metric value, in response to determining that the first bin is not an initial bin of the scan order, causing, using a second read level offset assigned to a second bin, a second scan to be performed to obtain a second bit error metric value, wherein the second bin immediately precedes the first bin in the scan order, and selecting, based on first bit error metric value and the second bit error metric value, an optimal bin from the set of bins.
Inventor(s): James Brian Johnson of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Brent Keeth of Boise ID (US) for micron technology, inc., Eiichi Nakano of Boise ID (US) for micron technology, inc., Amy Rae Griffin of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/56, G11C7/10
Abstract: methods, systems, and devices for memory with parallel main and test interfaces are described. a memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). for example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. the memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. by implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.
Inventor(s): Alan John Wilson of Boise ID (US) for micron technology, inc., Donald M. Morgan of Meridian ID (US) for micron technology, inc., John David Porter of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/00, G11C29/54
Abstract: apparatus and methods for page-based soft post package repair are disclosed. based on data stored in a storage element, an address may be decoded to a prime row, a row-based redundant row, or a page-based redundant row. a match logic circuit may determine whether the address corresponds to a defective prime row and generate a match signal. a decoder can select a redundant row to be accessed instead of a prime row in response to the match signal indicating that the address data corresponding to the address to be accessed matches defective address data stored in a volatile memory. a page-based redundant row allows for page-by-page substitution for defective memory, allowing functional portions of memory to continue to be used.
Inventor(s): Yoshinori Fujiwara of Boise ID (US) for micron technology, inc., Takuya Tamano of Boise ID (US) for micron technology, inc., Jason M. Johnson of Nampa ID (US) for micron technology, inc., Kevin G. Werhane of Kuna ID (US) for micron technology, inc., Daniel S. Miller of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/00, G11C29/44, G11C29/46
Abstract: an electronic device includes multiple memory elements including multiple redundant memory elements. the electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. the repair circuitry includes multiple fuse latches configured to implement the remapping. the repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. the latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.
20240071679.CONDUCTIVE NODE INDUCTION APPARATUS_simplified_abstract_(micron technology, inc.)
Inventor(s): Carlos Franco of Boise ID (US) for micron technology, inc.
IPC Code(s): H01F27/28, H01F41/04
Abstract: systems, methods, and apparatus are provided for a conductive node induction apparatus. a particular induction apparatus can include a first plurality of conductive nodes that include a corresponding first edge and second edge, a second plurality of conductive nodes that include a corresponding first edge and second edge, wherein the first plurality of conductive nodes are separated from the second plurality of conductive nodes by a space, a first conductive trace coupled to a first edge a first conductive node of the first plurality of conductive nodes and coupled to a second edge of a first conductive node of the second plurality of conductive nodes, and a second conductive trace coupled to a first edge of the first conductive node of the second plurality of conductive nodes and coupled to a second edge of a second conductive node of the first plurality of conductive nodes.
20240071816.STAIRCASE FORMATION IN A MEMORY ARRAY_simplified_abstract_(micron technology, inc.)
Inventor(s): Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/535, H01L27/11526, H01L27/11573
Abstract: methods, systems, and devices for staircase formation in a memory array are described. a liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. after doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. after converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. after exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.
Inventor(s): Chandra S. Tiwari of Boise ID (US) for micron technology, inc., Jivaan Kishore Jhothiraman of Meridian ID (US) for micron technology, inc., Rutuparna Narulkar of Boise ID (US) for micron technology, inc., Nayan Chakravarty of Tualatin OR (US) for micron technology, inc., Pengyuan Zheng of Boise ID (US) for micron technology, inc., Hiroaki Iuchi of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/522
Abstract: a variety of applications can include apparatus having a memory device structured with a three-dimensional array of memory cells and one or more vertical metal contacts extending through levels of the memory device, where the one or more vertical metal contacts are formed with reduced stress. each of the one or more vertical metal contacts can be constructed by forming a liner on walls of an opening in a dielectric, where the opening extends through the levels for the memory device, and forming a metal composition adjacent the liner and filling the opening with the metal composition. the liner can be removed from at least a portion of the walls of the dielectric, where the liner has a composition correlated to the metal composition such that removal of the liner reduces stress on the metal composition.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Terrence B. McDaniel of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/00, H01L23/48, H01L23/522, H01L23/532
Abstract: a semiconductor assembly is described that includes a semiconductor die having first circuitry. the semiconductor die further includes second circuitry with a reservoir of conductive material and an interlayer dielectric having one or more openings between the first circuitry and the reservoir of conductive material. the reservoir of conductive material is heated effective to cause the reservoir of conductive material to volumetrically expand through the one or more openings to create one or more vias that electrically couples the first circuitry and the reservoir of conductive material. in doing so, a connected semiconductor device may be assembled.
Inventor(s): Charles E. Siko of Boise ID (US) for micron technology, inc., Kaleb A. Wilson of Caldwell ID (US) for micron technology, inc., Bradley R. Bitz of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/40, H01L23/498, H01L25/065
Abstract: a printed wiring board assembly is disclosed that includes a printed wiring board with a first side and a second side opposite first side. magnet structures are in physical contact with the printed wiring board and a microelectronic device component is coupled to the first side of the printed wiring board. a heat spreader overlies and is in thermal communication with the microelectronic device component, and posts are coupled to the heat spreader and horizontally neighbor the microelectronic device component, where the posts are in magnetic communication with the magnet structures. related methods and electronic systems are also disclosed.
Inventor(s): Hong Wan Ng of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/48, H01L21/768, H01L23/528
Abstract: a semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.
Inventor(s): Seng Kim Ye of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L25/065, H01L25/16
Abstract: this document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. a semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. the package-level substrate has a first surface at which first contact pads are disposed in a first configuration. the packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. the additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. in doing so, an adaptively compatible semiconductor device may be assembled.
Inventor(s): Ling Pan of Singapore (SG) for micron technology, inc., Wei Yu of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/498, H01L21/48, H01L23/00
Abstract: a semiconductor device assembly includes a semiconductor die and a substrate coupled to the semiconductor die. the substrate includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. the substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. the substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the second solder mask layer through the secondary layer to the bond pad of the inner layer. by attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
Inventor(s): Hong Wan Ng of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Kelvin Aik Boo Tan of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/00, H01L23/29, H01L23/31, H01L25/065
Abstract: methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. in some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. an integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. in some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.
Inventor(s): Thiagarajan Raman of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/00, H01L25/065
Abstract: a semiconductor device assembly having face-to-face subassemblies is provided. the assembly includes a first and second semiconductor device subassembly. both subassemblies include a substrate, a stack of semiconductor dies, and an interconnect structure. the interconnect structures include a conductive pillar surrounded by dielectric material. both substrates form opposing outer sides of the assembly, while the interconnect structures are disposed on the inside surface of their respective substrates and are directly coupled to one another. the die stacks are shorter than their respective interconnect structures, and therefore can also be disposed on the inside surface of their respective substrates. an encapsulant material—comprising a different material than the dielectric material—at least partially encapsulates the stacks and the interconnect structures.
20240071902.FOLDED STAIRCASE VIA ROUTING FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Shuangqiang Luo of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/522, H01L21/768, H01L27/11519, H01L27/11524, H01L27/11551, H01L27/11565, H01L27/1157, H01L27/11578
Abstract: methods, systems, and devices for folded staircase via routing for memory are described. for instance, a memory device may include a set of word lines extending in first direction. additionally, the memory device may include a first via, a second via, and a third via in a trench that extends through at least a portion of the set of word lines the first via, the second via, and the third via may extend in a second direction different than the first, where the second via is between the first via and the third via along the first direction, and where the second via is coupled with a word line of the set of word lines. additionally, the first via and the third via may be electrically isolated from the word line of the set of word lines.
Inventor(s): Martin J. Barclay of Middleton ID (US) for micron technology, inc., Mojtaba Asadirad of Boise ID (US) for micron technology, inc., Yiping Wang of Boise ID (US) for micron technology, inc., Matthew Holland of Victor NY (US) for micron technology, inc., Mohad Baboli of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/522, H01L21/768
Abstract: a microelectronic device comprises a stack structure, a staircase structure, a first liner material, an etch stop structure, and conductive contact structures. the stack structure includes conductive structures and insulative structures arranged in tiers. the stack structure includes sidewalls horizontally bounding the staircase structure. the staircase structure has steps includes edges of tiers of the stack structure. the first liner material is on the steps and the sidewalls and includes horizontally extending portions on the steps and vertically extending portions on the sidewalls. the etch stop structure is on the horizontally extending portions of the first liner material, the vertically extending portions of the first liner material being free of the etch stop structure. the conductive contact structures extend through the etch stop structure and the first liner material and to the conductive structures. memory devices, electronic systems, and methods of forming microelectronic devices are also described.
Inventor(s): Thiagarajan Raman of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L21/56, H01L23/00, H01L23/31, H01L23/532
Abstract: a semiconductor device assembly is provided. the assembly includes a substrate with an inner and outer surface, a plurality of semiconductor devices disposed on the inner surface, a central interconnect structure disposed between the devices, a plurality of peripheral interconnect structures disposed around the devices, and an encapsulant material at least partially encapsulating the devices and the interconnects. the central interconnect structure includes a plurality of conductors and a sheath of dielectric material that surrounds and electrically isolates each of the plurality of conductors. each of the peripheral interconnect structures is electrically coupled to at least one of the semiconductor devices. the encapsulant comprises a different material than the dielectric material.
Inventor(s): Lifang Xu of Boise ID (US) for micron technology, inc., Sidhartha Gupta of Boise ID (US) for micron technology, inc., Indra V. Chary of Boise ID (US) for micron technology, inc., Richard J. Hill of Boise ID (US) for micron technology, inc., Umberto Maria Meotto of Dietlikon (CH) for micron technology, inc.
IPC Code(s): H01L23/528, H01L23/535, H01L27/11556, H01L27/11582
Abstract: a microelectronic device includes a stack structure having tiers each including conductive material vertically neighboring insulative material and conductive contact structures. the stack structure is divided into blocks horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction by insulative slot structures. at least one of the blocks includes a lower stadium structure having steps including edges of some of the tiers, and an upper stadium structure vertically overlying the lower stadium structure and having additional steps including edges of some other of the tiers vertically overlying the some of the tiers. the additional steps have greater tread widths in the first direction than the steps. conductive contact structures are in contact with the additional steps of the upper stadium structure of the at least one of the blocks. memory devices and electronic systems are also described.
Inventor(s): Mohad Baboli of Boise ID (US) for micron technology, inc., Yiping Wang of Boise ID (US) for micron technology, inc., Xiao Li of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc., John M. Meldrim of Boise ID (US) for micron technology, inc., Jivaan Kishore Jhothiraman of Meridian ID (US) for micron technology, inc., Shuangqiang Luo of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L21/768, H01L23/535
Abstract: a microelectronic device includes a stack structure comprising blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. at least one of the blocks comprising a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers; and a filled trench vertically overlying and within horizontal boundaries of the stadium structure of the at least one of the blocks. the filled trench includes a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions and at least one dielectric structure doped with one or more of carbon and boron on the dielectric liner material, the at least one dielectric structure horizontally overlapping the steps of the stadium structure.
Inventor(s): Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/532, H01L21/768, H01L23/522, H01L23/528, H10B41/27, H10B41/35, H10B43/27, H10B43/35
Abstract: a microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. related microelectronic devices, electronic systems, and methods are also described.
Inventor(s): Tom George of Boise ID (US) for micron technology, inc., Rita J. Klein of Boise ID (US) for micron technology, inc., Daniel Billingsley of Meridian ID (US) for micron technology, inc., Pengyuan Zheng of Boise ID (US) for micron technology, inc., Yongjun Jeff Hu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/535, H01L27/11556, H01L27/11582
Abstract: a memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. strings of memory cells comprising channel-material strings extend through the insulative tiers and the conductive tiers. the conductor tier comprises upper conductor material directly above and directly against lower conductor material of different composition from that of the upper conductor material. a through-array-via (tav) region is included and comprises tavs individually comprising the upper conductor material, the lower conductor material, and a conducting material that is directly below the conductor tier. the lower conductor material is directly against the conducting material and comprises at least one of (a) and (b), where, (a): a metal-rich refractory metal nitride; and (b): a stoichiometric or non-stoichiometric refractory metal nitride directly above and directly against one of (1), (2), or (3), where: (1): an elemental metal; (2): an alloy of at least two elemental metals; and (3): a metal-rich refractory metal nitride of different composition from that of the stoichiometric or non-stoichiometric refractory metal nitride. methods are also disclosed.
Inventor(s): Jivaan Kishore Jhothiraman of Meridian ID (US) for micron technology, inc., Chandra Tiwari of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/535, H01L23/528, H01L23/532, H01L27/11556, H01L27/11582
Abstract: a method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. the stack extends from a memory-array region into a stair-step region. the stack in the stair-step region comprises a cavity comprising a flight of stairs in a vertical cross-section along a first direction. the first tiers are conductive and the second tiers are insulative in a finished-circuitry construction. an insulating lining is formed in the cavity atop treads of the stairs and laterally-over sidewalls of the cavity that are along the first direction. individual of the treads comprise conducting material of one of the conductive tiers in the finished-circuitry construction. the insulating lining is thicker in a bottom part of the cavity than over the sidewalls of the cavity that are above the bottom part. insulative material is formed in the cavity directly above the insulating lining. conductive vias are formed through the insulative material and the insulating lining. individual of the conductive vias are directly above and directly against the conducting material of the tread of individual of the stairs. other embodiments, including structure, are disclosed.
Inventor(s): Yun Ting Hsu of Taichung (TW) for micron technology, inc., Chong Leong Gan of Taichung (TW) for micron technology, inc., Min Hua Chung of Taichung (TW) for micron technology, inc., Yung Sheng Zou of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/498
Abstract: a semiconductor device assembly is provided. the assembly includes a package substrate which has a tunneled interconnect structure. the tunneled interconnect structure has a solder-wettable surface, an interior cavity, and at least one microvia extending from the surface to the cavity. the assembly further includes a semiconductor device disposed over the substrate and a solder joint coupling the device and the substrate. the joint comprises the solder between the semiconductor device and the interconnect structure, which includes the solder on the surface, the solder in the microvia, and the solder within the interior cavity.
Inventor(s): Shyam Surthi of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065, H01L25/18
Abstract: memory array structures might include a first data line selectively connected to a first plurality of memory cells, a second data line selectively connected to a second plurality of memory cells, a solid first dielectric extending between a first portion of the first data line and a first portion of the second data line, a second dielectric containing a void extending between a second portion of the first data line and a second portion of the second data line, and a top contact overlying and in contact with the first portion of the first data line.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Terrence B. McDaniel of Boise ID (US) for micron technology, inc., Wei Zhou of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: this document discloses techniques, apparatuses, and systems for semiconductor device interconnects formed through volumetric expansion. a semiconductor assembly is described that includes two semiconductor dies. the first semiconductor die and the second semiconductor die are bonded at a dielectric layer of the first semiconductor die and a dielectric layer of the second semiconductor die to create one or more interconnect openings. the first semiconductor die includes a reservoir of conductive material located adjacent to the one or more interconnect openings and having a width greater than a width of the one or more interconnect openings. the reservoir of conductive material is heated to volumetrically expand the reservoir of conductive material through the one or more interconnect openings to form one or more interconnects electrically coupling the first semiconductor die and the second semiconductor die. in this way, a connected semiconductor device may be assembled.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Bret K. Street of Meridian ID (US) for micron technology, inc., Bang-Ning Hsu of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/00, H01L25/065
Abstract: semiconductor devices and semiconductor device assemblies, and related systems and methods, are disclosed herein. in some embodiments, the semiconductor device includes a support substrate, a first die package carried by the support substrate, and a second die package carried by the first die package. each of the first and second die packages can include a first die, a second die hybrid bonded a surface of the first die, and a third die hybrid bonded to a surface of the second die. the first die is coupled to the third die via an interconnect portion of the second die. further, the third die can include an array of active cells for each of the packages, the second die can include complementary-metal-oxide-semiconductor (cmos) circuitry accessing the active cells, and the first die can include backend of line (beol) circuitry associated with the active cells and cmos circuitry.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L25/065
Abstract: a semiconductor device assembly is described that includes two semiconductor dies. the semiconductor dies each include a layer of dielectric material and a reservoir of conductive material located adjacent to openings in the layer of dielectric material. the opening at the layer of dielectric material of the first semiconductor die and the opening at the layer of dielectric material of the second semiconductor die are aligned to create an interconnect opening. the reservoirs of conductive material are heated to volumetrically expand the reservoirs of conductive material past one another such that they contact at respective non-horizontal surfaces to form an interconnect electrically coupling the semiconductor dies. in this way, a connected semiconductor device may be assembled.
Inventor(s): Hidenori Yamaguchi of Higashihiroshima (JP) for micron technology, inc., Keizo Kawakita of Higashi Hiroshima City (JP) for micron technology, inc., Bang-Ning Hsu of Tainan (TW) for micron technology, inc.
IPC Code(s): H01L23/00, H01L25/065, H01L25/18
Abstract: apparatus and methods are disclosed, including stacked die devices and systems. example stacked die devices and methods include an array of interconnect pillars that includes more than one pillar height. example stacked die devices and methods include an array of interconnect pillars that includes a pillar height distribution mapped to a known warpage profile.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: a semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. the semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of tsvs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of tsvs. the first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of tsvs.
Inventor(s): Bong Woo Choi of Singapore (SG) for micron technology, inc., Venkateswarlu Bhavanasi of Singapore (SG) for micron technology, inc., Wen How Sim of Singapore (SG) for micron technology, inc., Harjashan Veer Singh of San Jose CA (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L23/498, H01L25/065
Abstract: substrates with spacers, including substrates with solder resist spacers, and associated devices, systems, and methods are disclosed herein. in one embodiment, a substrate comprises a first surface, a solder resist layer disposed over at least a portion of the first surface, and a plurality of electrical contacts at the first surface of the substrate. electrical contacts of the plurality are configured to be coupled to corresponding electrical contacts at a surface of an electronic device. the substrate further includes a solder resist spacer disposed on the solder resist layer. the solder resist spacer can have a height corresponding to a thickness of the electronic device. the solder resist spacer can be configured as a dam to limit bleed out of underfill laterally away from the plurality of electrical contacts along the first surface and toward the solder resist spacer.
20240071976.SEMICONDUCTOR DEVICE WITH A POLYMER LAYER_simplified_abstract_(micron technology, inc.)
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/29, H01L23/31, H01L25/065
Abstract: this document discloses techniques, apparatuses, and systems for a semiconductor device with a polymer layer. a semiconductor assembly is described that includes two semiconductor dies. the first semiconductor die has a first active side with first circuitry and a first back side opposite the first active side. contact pads and a layer of polymer material are disposed at the first back side such that the layer of polymer material includes openings that expose the contact pads. the second semiconductor die has second circuitry disposed at a second active side. interconnect structures are also disposed at the second active side such that the interconnect structures extend into the openings and couple to contact pads. a passivation layer (e.g., dielectric material) is disposed at the second active side and directly bonded to the layer of polymer material to reliably couple the two semiconductor dies.
Inventor(s): Chen Yu Huang of Taichung City (TW) for micron technology, inc., Chong Leong Gan of Taichung City (TW) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/24, H01L25/00, H01L25/065
Abstract: a semiconductor package having a fillet is provided. the semiconductor package includes a trace disposed within a solder mask that has a top surface. a first die is over the solder mask and mechanically couples with the trace. a first adhesive is between the trace and the first die where sides of the first die and the first adhesive define a die edge. the semiconductor package includes a fillet adjacent the die edge and a second die above the first die. the semiconductor package also includes a second adhesive having a bottom surface where the second adhesive is between the first die and the second die. the solder mask top surface, the first die surface, and the second adhesive bottom surface define a cavity where the fillet is within the cavity at the die edge.
Inventor(s): Chin Hui Chong of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Suresh K. Upadhyayula of San Jose CA (US) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: an assembly comprising a substrate with a first and second bond pad at a top surface; and a semiconductor die with a lower surface coupled to the top surface, an upper surface with a third and fourth bond pad thereat, and a side surface perpendicular to the upper and lower surfaces. the first bond pad can be a first distance, the second bond pad can be a second distance, the third bond pad can be a third distance, and the fourth bond pad can be a fourth distance, respectively, from the side surface. the first and third distances summed can be the same as the second and fourth distances summed. a first wire can extend between the first and third bond pads, and a second wire can extend between the second and fourth bond pads.
Inventor(s): Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/48, H01L23/498, H01L25/065
Abstract: stacked semiconductor devices, and related systems and methods, are disclosed herein. in some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. each of the sections can be directly coupled together. further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. the wirebonds can be directly coupled to the exposed surface of the uppermost section.
Inventor(s): Byung Hoon Moon of Taichung (TW) for micron technology, inc., Kyle K. Kirby of Eagle ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: a semiconductor die is provided, comprising a semiconductor substrate; a dielectric layer over the semiconductor substrate; a bond pad in the dielectric layer, the bond pad including an exposed top surface that is recessed with respect to a surface of the dielectric layer opposite to the semiconductor substrate; and a region of piezoelectric material in the dielectric layer, wherein the region is located proximate to the bond pad to supply thermal energy to the bond pad in response to exposing the piezoelectric material to an externally-applied field.
Inventor(s): Bang-Ning Hsu of Taichung (TW) for micron technology, inc., Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Byung Hoon Moon of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: a semiconductor die is provided, comprising a semiconductor substrate, a dielectric layer over the semiconductor substrate, a bond pad in the dielectric layer, the bond pad including an exposed top surface that is recessed with respect to a surface of the dielectric layer opposite to the semiconductor substrate, and a region including a plurality of embedded nanoparticles in the dielectric layer, wherein the region is located proximate to the bond pad to supply thermal energy to the bond pad in response to exposing the plurality of embedded nanoparticles to an externally-applied field.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Terrence B. McDaniel of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: this document discloses techniques, apparatuses, and systems for semiconductor device circuitry formed from remote reservoirs. a semiconductor assembly includes a first semiconductor die with a layer of dielectric material having an opening. the first semiconductor die further includes a reservoir of conductive material having a first portion located adjacent to the opening, a second portion remote from the opening, and a third portion coupling the first portion and the second portion. a second semiconductor die includes a layer of dielectric material and a contact pad corresponding to the opening. the reservoir of conductive material is heated to volumetrically expand the second portion into the third portion, the third portion into the first portion, and the first portion through the opening to form an interconnect electrically coupling the first semiconductor die and the second semiconductor die at the contact pad. in this way, a connected semiconductor device may be assembled.
Inventor(s): Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/48, H01L23/498
Abstract: a semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.
Inventor(s): Raj K. Bansal of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/00, H01L25/00
Abstract: a semiconductor device assembly can include an assembly substrate having a top surface with a die stack thereat. the die stack can include a first and a second die, and each dies can include a die substrate with a top and a bottom surface. the top surface can include a first region a first distance from the bottom surface, and a second region a second distance, greater than the first distance, from the bottom surface and with a bond pad thereat. the bottom surface of the first die can bond with the top surface of the assembly substrate, and the bottom surface of the second die can bond with the first region of the first die top surface. in some embodiments, the assembly can further include additional die stacks and/or additional dies within one or more die stacks.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/00
Abstract: a semiconductor assembly is described that includes two semiconductor dies. the first semiconductor die includes a first layer of dielectric material at which a first portion of conductive material implementing a first portion of a passive circuit component is at least partially disposed. the second semiconductor die includes a second layer of dielectric material at which a second portion of conductive material implementing a second portion of the passive circuit component is at least partially disposed. a first contact pad at the first layer of dielectric material and a second contact pad at a second layer of dielectric material are coupled to create an interconnect electrically coupling the first semiconductor die and the second semiconductor die. a metal-metal bond is formed between the first portion of the passive circuit component and the second portion of the passive circuit component to create the passive circuit component.
Inventor(s): Seng Kim Ye of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/16, H01G2/06, H01G13/00, H01L23/00, H01L25/065, H01L25/18
Abstract: semiconductor devices, and related systems and methods, are disclosed herein. in some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. the die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. the stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.
Inventor(s): Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/16, H01L21/48, H01L23/00, H01L23/13, H01L23/498
Abstract: modular systems in packages, and associated devices, systems, and methods, are disclosed herein. in one embodiment, a system comprises a main module package and an upper module package. the main module package includes a first substrate and a first electronic device mounted on a first side of the first substrate. the upper module package includes a second substrate and one or more second electronic devices mounted on a first side of the second substrate. the second substrate includes a cavity at a second side of the second substrate opposite the first side, and the upper module package is mountable on the first side of the first substrate of the main module package such that the first electronic device is positioned within the cavity and the second substrate generally surrounds at least a portion of a perimeter of the first electronic device.
Inventor(s): Michael A. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/40, H01L29/423
Abstract: semiconductor devices including an adjusted bottom/deep well embedded in a semiconductor substrate. the adjusted bottom/deep well having one or more characteristics resulting from being formed using or through a temporary masked layer.
20240072138.CONTACT ARRANGEMENTS FOR TRANSISTORS_simplified_abstract_(micron technology, inc.)
Inventor(s): Yoshikazu Moriwaki of Hiroshima (JP) for micron technology, inc.
IPC Code(s): H01L29/417, H01L29/49, H10B12/00
Abstract: a variety of applications can include apparatus having one or more transistors with a contact arrangement to significantly mitigate a parasitic capacitance between one or more contacts to an active area of the transistor and a gate of the transistor. one or more contact arrangements can include a contact to an active area in a position beyond a boundary of an end of the gate along a first direction, where the gate is structured along the first direction. one or more other contact arrangements can include two contacts to an active area in positions beyond boundaries of two opposite ends of the gate along a first direction. arrangements can include a metal silicide region coupling two contacts to each other in an active region with the two contacts in positions beyond boundaries of two opposite ends of the gate along a first direction.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Anthony J. Kanago of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc., Soichi Sugiura of Bristow VA (US) for micron technology, inc.
IPC Code(s): H01L29/786, H10B12/00
Abstract: a variety of applications can include an apparatus having an electronic device including a number of transistors in a pair-wise arrangement that can address a floating body effect associated with the type of transistor implemented in the pair-wise arrangement. the transistors can be structured as thin film transistors having one-gate separated by a gate dielectric from a vertical channel structure. the pair-wise arrangement can include a conductive shield between a channel structure of a transistor of the pair and a channel structure of the other transistor of the other pair. a conductive body can be located below the conductive shield and shorted to the conductive shield, where the conductive body contacts the channel structures of the transistors of the pair-wise arrangement. the conductive shield can be coupled to node to be set at a constant voltage in operation.
Inventor(s): Yoshihito Morishita of Shibuya-ku (JP) for micron technology, inc.
IPC Code(s): H03K3/0232, G01R31/317, H03K3/014, H03K3/017
Abstract: systems and techniques to offset conditions affecting propagation delay of a clock signal in a memory device. these include a device that includes a clock adjustment circuit, comprising a differential amplifier, an inverter coupled to a first output of the differential amplifier, and a swing oscillator driver coupled to a second output of the inverter and an input of the differential amplifier. the swing oscillator driver includes a series of transistors, a signal path coupled to at least a first transistor of the series of transistors, wherein the signal path when in operation transmits a signal having a first voltage, and a strength control circuit coupled to the signal path, wherein the strength control circuit when in operation adjusts the first voltage of the signal to a second voltage.
20240072999.CLOUD STORAGE WITH ENHANCED DATA PRIVACY_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): H04L9/08, H04L9/32
Abstract: in some aspects, the techniques described herein relate to a method including: generating a digital certificate using a public key of a secure environment; storing the digital certificate in a storage device of a cloud service; generating, by the secure environment, a signed command to access the storage device, the signed command signed using a private key corresponding to the public key of the secure environment; and issuing the signed command to the storage device to access data stored by the storage device.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): H04L9/08, H04L9/32
Abstract: in some aspects, the techniques described herein relate to a method including: transmitting, by a user device, a public key of a client device to a key management server (kms); generating, by the kms, a digital certificate using the public key of the client device; storing the digital certificate in a storage device of a cloud service; generating, by the client device, a signed command to access the storage device, the signed command signed using a private key corresponding to the public key of the client device; and issuing the signed command to the storage device to access data stored by the storage device.
Inventor(s): Lance W. Dover of Fair Oaks CA (US) for micron technology, inc.
IPC Code(s): H04L9/08, H04L9/32
Abstract: methods, systems, and devices for techniques for generating a shared secret for an electronic system are described. a memory system may identify an initial key pair and exchange a public key of the key pair with a public key associated with a server. the memory system and the server may each generate a shared secret. in some cases, the memory system and the server may use the shared secret to generate a device identifier for the memory system, for example by incorporating the device identifier into a cryptographic representation of a software layer of the memory system. the memory system and the server may use the device identifier to generate one or more asymmetric key pairs, which may be used by the server to authenticate the memory system.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): H04L9/32, H04L9/30
Abstract: in some aspects, the techniques described herein relate to a device including: a processor; and a storage medium for tangibly storing thereon logic for execution by the processor, the logic including instructions for: storing a group digital certificate, the group digital certificate including a plurality of unique identifier (uid) values and a plurality of corresponding public keys; receiving onboarding data and a digital signature from a client device, the onboarding data including a uid of the client device and a public key of the client device and the digital signature generated using the onboarding data and a private key corresponding to the public key; validating the digital signature using the public key; confirming that the uid matches at least one uid in the group digital certificate; and onboarding the client device.
Inventor(s): Ling Pan of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc.
IPC Code(s): H05K1/11, H01L23/00, H01L25/065, H05K1/18, H05K3/46
Abstract: a semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (pcb) coupled to the substrate. the pcb includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. the substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. the substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. by attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
20240074055.SUBSTRATES WITH CONTINUOUS SLOT VIAS_simplified_abstract_(micron technology, inc.)
Inventor(s): Walter L. Moden of Boise ID (US) for micron technology, inc., Stephen F. Moxham of Boise ID (US) for micron technology, inc., Travis M. Jensen of Boise ID (US) for micron technology, inc.
IPC Code(s): H05K1/11, H01L21/48, H01L23/48, H01L23/498, H05K3/00, H05K3/40
Abstract: substrates with continuous slot vias are disclosed herein. in one embodiment, a substrate comprises a first design layer, a second design layer, and an intermediary layer between the first and second design layers. the substrate further includes first and second signaling vias extending vertically through the intermediary layer between the first and second design layers. the first and second signaling vias route first and second data signals, respectively, between the first and second design layers. the substrate further includes a slot via that is positioned between the first and second signaling vias within the intermediary layer and extends laterally within the intermediary layer along a path that passes between the first signaling via and the second signaling via. the slot via can have a continuous shape such that the slot via shields the first and second data signals on the first and second signaling vias from crosstalk with one another.
Inventor(s): Shiva Pahwa of Bangalore (IN) for micron technology, inc., Abhiash Ramamurthy Nag of Bangalore (IN) for micron technology, inc., Suresh Reddy Yarragunta of Bangalore (IN) for micron technology, inc.
IPC Code(s): H05K7/20, F28F3/04, G06F1/20
Abstract: example embodiments are directed to an input/output (io) bracket that may be used in a solid-state drive (ssd), the io bracket comprises a faceplate and at least one heat pipe coupled to the faceplate that extends horizontally from a surface of the faceplate. the at least one heat pipe is configured to be coupled to a controller of the ssd in order to transfer heat from the controller out of the ssd. by coupling the controller to the heat pipe instead of a main heatsink, the main heatsink can efficiently dissipate heat from remaining components of the ssd.
Inventor(s): Mitsunari Sukekawa of Hiroshima (JP) for micron technology, inc.
IPC Code(s): H01L27/11
Abstract: microelectronic devices include at least one memory cell, each with six transistors collectively comprising six pillars grouped in pillar pairs and formed from a semiconductor material. each of the pillar pairs includes a first and a second pillar. gate electrodes are also included, with each gate electrode extending between and horizontally around a portion of the first pillar and a portion of the second pillar of a respective one of the pillar pairs. conductive structures are electrically coupled to the six pillars. at least one of the conductive structures is in physical contact with more than one of the pillars of the microelectronic device. related methods and electrical systems are also disclosed.
Inventor(s): Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Kamal M. Karda of Boise ID (US) for micron technology, inc., Pankaj Sharma of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a first data line; a second data line adjacent the first data line and separated from the first data line by a first dielectric structure; and a memory cell formed over the first and second data lines. the memory cell includes a first transistor including a first channel region formed over and coupled to the first data line, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over and coupled to the second data line, wherein the charge storage structure is formed over and coupled to the second channel region; and a second dielectric structure between the first channel region and each of the second channel region and the charge storage structure.
Inventor(s): Yoshitaka Nakamura of Boise ID (US) for micron technology, inc., Yuanzhi Ma of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc., David K. Hwang of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/108, H01L29/66, H01L29/786
Abstract: methods and devices for a lateral three-dimensional memory device, are described herein. one method includes forming a thin film transistor including a first thermal process having a first range of temperatures, forming a capacitor bottom electrode of a capacitor structure including a second thermal process having a second range of temperature, wherein a maximum temperature in the second range of temperatures is less than a maximum temperature in the first range of temperatures, forming a cmos structure including a third thermal process having a third range of temperatures, wherein a maximum temperature in the third range of temperatures is less than a maximum temperature in the second range of temperatures, and forming at least one other part of the capacitor structure.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/108
Abstract: a microelectronic device comprises a vertical stack of memory cells. each vertical stack of memory cells comprises a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure in electrical communication with the vertical stack of access devices. the microelectronic device further comprises first global digit lines vertically neighboring the vertical stacks of memory cells, and second global digit lines horizontally interleaved with the first global digit lines in a horizontal direction, the second global digit lines vertically spaced from the vertical stacks of memory cells a greater distance than the first global digit lines. related memory devices, electronic systems, and methods are also described.
Inventor(s): Yuichi Yokoyama of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
Abstract: systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. the bottom electrode contact is formed in a periphery region. the bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.
20240074153.CONDUCTIVE STRUCTURES_simplified_abstract_(micron technology, inc.)
Inventor(s): Daniel Billingsley of Meridian ID (US) for micron technology, inc., Jaydip Guha of Boise ID (US) for micron technology, inc., Marko Milojevic of Boise ID (US) for micron technology, inc., Sau Ha Cheung of Boise ID (US) for micron technology, inc., Luca Fumagalli of Rio Rancho NM (US) for micron technology, inc.
IPC Code(s): H01L27/108, H01B1/02
Abstract: methods, apparatuses, and systems related to conductive structures are described. an example conductive structure includes a first conductive material including a conductive metal nitride, where the first conductive material has a thickness of at least 0.5 nanometers, and a second conductive material including a conductive metal, where the second conductive material is disposed on a first surface of the first conductive material.
20240074158.SHALLOW TRENCH ISOLATION RECESS CONTROL_simplified_abstract_(micron technology, inc.)
Inventor(s): Chunhua Yao of Boise ID (US) for micron technology, inc., Song Guo of Boise ID (US) for micron technology, inc., Vivek Yadav of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
Abstract: a variety of applications can include an apparatus having a memory device in which, during fabrication of the memory device, processing a dielectric isolation region about an active area of a memory cell is controlled to provide enhanced electric isolation of a data line contact to the memory cell with respect to a cell contact to the memory cell. a portion of the dielectric isolation region can be recessed, creating a corner between the dielectric isolation region and a conductive region, where the conductive region is material for the active area. the corner can be filled with a dielectric material and the data line contact can be formed contacting the dielectric material and coupled to the conductive region. the cell contact can be formed to the memory cell contacting the dielectric material such that the dielectric material is between the cell contact and the data line contact.
Inventor(s): Shivani Srivastava of Boise ID (US) for micron technology, inc., Russell Allen Benson of Boise ID (US) for micron technology, inc., Raghunath Singanamalla of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
Abstract: a variety of applications can include apparatus having a memory device with metal digit lines for various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region. in the integrated process flow, material of the metal digit lines can be used as the metal contacts to the transistors in the periphery to the memory array region. in various embodiments, a metal contact can contact a metal gate of a transistor in the periphery or contact a metal barrier region, where the metal barrier region is above and contacting the metal gate and is structured without including polysilicon. sacrificial polysilicon can be used to protect the gate of the transistor during processing in the memory array region.
20240074160.INTEGRATION OF MEMORY ARRAY WITH PERIPHERY_simplified_abstract_(micron technology, inc.)
Inventor(s): Shivani Srivastava of Boise ID (US) for micron technology, inc., Russell Allen Benson of Boise ID (US) for micron technology, inc., Raghunath Singanamalla of Boise ID (US) for micron technology, inc., Jaydeb Goswami of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
Abstract: a variety of applications can include apparatus having a memory device structured from integrated processing of a memory array of the memory device with a periphery to the memory array. the memory device can be implemented with transistors formed in the periphery, where metal gates of the transistors are structured without polysilicon regions between the metal gates and metal contacts for the metal gates. the integrated processing can provide step height reduction between the memory array and the periphery to the memory array of a memory device, with the elimination of polysilicon on the gate stack of transistors in the periphery. the step height reduction in the memory device can lower overlap capacitance.
Inventor(s): Russell Allen Benson of Boise ID (US) for micron technology, inc., Shivani Srivastava of Boise ID (US) for micron technology, inc., Jaydip Guha of Boise ID (US) for micron technology, inc., Raghunath Singanamalla of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
Abstract: a variety of applications can include apparatus having a memory device with digit line contacts disposed in a dielectric and metal digit lines coupled to various of the digit line contacts by at most one metal barrier above the dielectric. material of the metal digit lines is used as a contact metal to a transistor in a periphery to the memory array region, where the transistor is coupled to the metal contact by multiple barrier metals on polysilicon on the transistor. an integration flow of metallization for periphery devices to a memory array and digit lines can be implemented to allow separate barrier metal formation between the memory array and the periphery, while still using the same material as the main conductor. barrier metals can be formed for the periphery and the memory array region and then cleared from the memory array region before forming the main conductor.
Inventor(s): Shivani Srivastava of Boise ID (US) for micron technology, inc., Raghunath Singanamalla of Boise ID (US) for micron technology, inc., Russell Allen Benson of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
Abstract: a variety of applications can include apparatus having a memory device with metal digit lines coupled to various digit line contacts for a memory array in an integrated process flow of the metal lines with metal contacts of transistors in a periphery to the memory array region, with a metal silicide formed on the gates of the transistors. the metal silicide for each transistor can be coupled to the metal contact for the transistor. in the integrated process flow, material of the metal digit lines can be used as the metal contact to the transistors in the periphery to the memory array region. the metal silicide can be formed by conversion of polysilicon formed on the memory array region and the periphery to the memory array region in the integrated process flow.
Inventor(s): Paolo Fantini of Vimercate (IT) for micron technology, inc., Lorenzo Fratin of Milano (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/112
Abstract: memory devices, and associated systems and methods, are disclosed herein. a representative memory device comprises a substrate, an insulative layer over the substrate, and a memory array over the insulative layer. the memory device further comprises a fuse array positioned in the insulative layer and configured as a non-volatile memory that can store trimming and/or other factors. the fuse array can comprise a plurality of transistors configured as fuses and each including a source, a drain, and a gate. the transistors in a first subset of the transistors have a first resistance across one of the source, the drain, and the gate that represents a first logic state, and the transistors in a second subset of the transistors can have a second resistance across the one of the source, the drain, and the gate that is greater than the first resistance and that represents a second logic state.
Inventor(s): David H. Wells of Boise ID (US) for micron technology, inc., Justin D. Shepherdson of Meridian ID (US) for micron technology, inc., Swapnil A. Lengade of Boise ID (US) for micron technology, inc., Collin Howder of Boise ID (US) for micron technology, inc., Dheeraj Kumar of Boise ID (US) for micron technology, inc., Andrew L. Li of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/11582, H01L27/11556
Abstract: microelectronic devices include a region with a tiered stack that includes insulative, conductive, and non-conductive structures arranged in tiers. the insulative structures vertically alternate with both the conductive and the non-conductive structures. each of the conductive structures is vertically spaced from another of the conductive structures by at least one of the non-conductive structures and at least two of the insulative structures. a composition of the non-conductive structures differs from a composition of the insulative structures. in methods of fabrication, a precursor stack is formed to include the insulative structures vertically alternating with first and second non-conductive structures. in a region of the precursor stack, the first non-conductive structures are removed, forming voids between multi-structure tier groups. conductive structures are formed in the voids. electronic systems are also disclosed.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L27/11582, H01L27/11556
Abstract: an electronic device comprising one or more blocking regions. the electronic device also comprises a source stack comprising one or more conductive materials, a source contact vertically adjacent to the source stack, and a doped semiconductive material vertically adjacent to the source contact. tiers of alternating conductive materials and dielectric materials are vertically adjacent to the doped semiconductive material, and pillars extend through the tiers of alternating conductive materials and dielectric materials, the doped semiconductive material, and the source contact and into the source stack. the one or more blocking regions are laterally adjacent to the semiconductive material. additional electronic devices, electronic systems, and methods are also disclosed.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/11582, H01L23/535, H01L27/11556
Abstract: memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. the insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. the stair-step region comprises a flight of stairs extending along a first direction. multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. the multiple different-depth treads in the individual stairs comprise in lateral-succession along the second direction a first higher-depth tread, a lower-depth tread, and a second higher-depth tread. methods are also disclosed.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/11582, H01L23/535, H01L27/11556
Abstract: memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. the insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. the stair-step region comprises a flight of stairs extending along a first direction. multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. the multiple different-depth treads in the individual stairs comprise a first flight of the treads and a second flight of the treads. a landing is between and lower in the stack than each of the first and second flights of treads. the first and second flights of treads in the second direction face toward one another. methods are disclosed.
Inventor(s): Masaaki Higuchi of Tokyo (JP) for micron technology, inc., Yoshiaki Fukuzumi of Tokyo (JP) for micron technology, inc., Hirokazu Ishigaki of Tokyo (JP) for micron technology, inc.
IPC Code(s): H01L27/11582, G11C16/04, H01L27/11519, H01L27/11524, H01L27/11556, H01L27/11565, H01L27/1157
Abstract: an electronic device comprises memory pillars comprising a channel material. the memory pillars extend through both a cell region and a lateral contact region. a portion of the memory pillars in the lateral contact region comprise at least one first step and at least one second step. the electronic device comprises a source contact in direct contact with the channel material in the at least one second step of the portion of the memory pillars in the lateral contact region. additional electronic devices and methods of forming an electronic device are also disclosed.
Inventor(s): Shruthi Kumara Vadivel of Boise ID (US) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc., Richard T. Housley of Boise ID (US) for micron technology, inc., Zhenxing Han of Sunnyvale CA (US) for micron technology, inc., Scott L. Light of Boise ID (US) for micron technology, inc., Qinglin Zeng of Boise ID (US) for micron technology, inc., Hsiao-Kuan Yuan of Boise ID (US) for micron technology, inc., Jordan Chess of Boise ID (US) for micron technology, inc., Xiaosong Zhang of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes tiers located one over another; a first staircase structure formed in the tiers; a second staircase structure formed in the tiers adjacent the first staircase structure, respective portions of conductive materials in the tiers forming a part of the first and second staircase structure and a part of respective control gates associated with memory cells; a first trench structure formed in the tiers adjacent the first staircase structure and the second staircase structure, the first trench structure including length in a direction from the first staircase structure to the second staircase structure; and a second trench structure formed in the tiers adjacent the first trench structure, the second trench structure including a length in the direction from the first staircase structure to the second staircase structure.
Inventor(s): Matthew J. King of Boise ID (US) for micron technology, inc., Albert Fayrushin of Boise ID (US) for micron technology, inc., Sidhartha Gupta of Boise ID (US) for micron technology, inc., Jun Fujiki of Tokyo (JP) for micron technology, inc., Masashi Yoshida of Kanagawa (JP) for micron technology, inc., Yiping Wang of Boise ID (US) for micron technology, inc., Taehyun Kim of Boise ID (US) for micron technology, inc., Arun Kumar Dhayalan of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/1157, H01L27/11524, H01L27/11556, H01L27/11582
Abstract: a method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. the stack comprises lower channel-material strings extending through the first tiers and the second tiers. conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. upper channel-material strings of select-gate transistors are formed directly above the stack. individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. other embodiments, including structure, are disclosed.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/1157, H01L21/306, H01L21/308, H01L27/11578
Abstract: a method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. the stack extends from a memory-array region into a stair-step region. the stair-step region comprises a flight of stairs extending along a first direction. the first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. an anisotropically-etched spacer is formed extending along the first direction directly above the flight of stairs. the anisotropically-etched spacer is used as a mask while etching through one of the first tiers and one of the second tiers in individual of the stairs to form multiple different-depth treads in the individual stairs along a second direction that is orthogonal to the first direction. individual of the treads comprise conducting material of individual of the first tiers in the finished-circuitry construction. other aspects, including structure independent of method, are disclosed.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Chandra Mouli of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B63/00, G11C5/06, H10B63/10, H10N70/00
Abstract: some embodiments include apparatuses and methods of operating the apparatuses. one of the apparatuses includes a conductive region; a memory cell including a memory element, a first portion, a second portion, a dielectric portion, and a third portion; and a data line formed over the second and third portions of the memory cell. the memory element is formed over the conductive region. the first portion is formed over the memory element and includes a first conductive material. the second portion is formed over the first portion and includes a second conductive material. the dielectric portion includes a first side adjacent the memory element, the first portion, and the second portion. the third portion includes a third conductive material and is adjacent a second side of the dielectric portion and separated from the memory element, the first portion, and the second portion by the dielectric portion.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Yi Fang Lee of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Ramanathan Gandhi of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc., Sameer Chhajed of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B99/00, H01L27/092, H01L27/12, H01L29/24, H01L29/267, H01L29/423, H01L29/66, H01L29/786
Abstract: some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. the second semiconductor material is a different composition than the first semiconductor material. hydrogen is diffused within the first and second semiconductor materials. the conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. a transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. some embodiments include methods of forming integrated assemblies.
Micron Technology, Inc. patent applications on February 29th, 2024
- Micron Technology, Inc.
- G01N21/88
- G06T7/00
- Micron technology, inc.
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