Micron Technology, Inc. patent applications on February 1st, 2024
Patent Applications by Micron Technology, Inc. on February 1st, 2024
Micron Technology, Inc.: 43 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (8), G06F3/0679 (5), G06F3/0604 (4), H01L27/11582 (4), G11C11/4078 (4)
With keywords such as: memory, device, data, voltage, devices, structure, include, configured, microelectronic, and cells in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20240035592.VARIABLE ROUTING CLAMP_simplified_abstract_(micron technology, inc.)
Inventor(s): Cristofer Anthony FARNETTI of Boise ID (US) for micron technology, inc., Maxwell Lewis BENNETT of Boise ID (US) for micron technology, inc.
IPC Code(s): F16L3/10
Abstract: implementations described herein relate to a variable routing clamp. in some implementations, a routing clamp may include a rigid body defining a channel. the routing clamp may include a flexible cushion that is configured to be inserted into the channel, where the flexible cushion includes two or more through holes extending through the flexible cushion that are configured to receive flexible lines, and where distances between the two or more through holes satisfy a threshold. the routing clamp may include a rigid cap that is configured to be fastened to the rigid body over an opening of the channel, where the rigid cap includes one or more lips that are configured to restrict movement of the flexible cushion after the flexible cushion is inserted into the channel.
20240036596.VOLTAGE REGULATION SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc., Leonid Minz of Beer Sheva (IL) for micron technology, inc., Ekram H. Bhuiyan of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G05F1/575, G11C5/14
Abstract: a first voltage regulation circuit is coupled to a second voltage regulation circuit. control circuitry is coupled to the first voltage regulation circuit and the second voltage regulation circuit. the control circuitry determines that a signal criterion is met, and controls application of a voltage signal generated by the second voltage regulation circuit to stabilize a voltage signal generated by the first voltage regulation circuit.
Inventor(s): Brandon Richard Nixon of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F1/14
Abstract: a known randomized data pattern at a predetermined reference voltage of the internal oscilloscope is inputted to an internal oscilloscope of the receiving device for each delay tap element of a plurality of consecutive delay tap elements applied to a system clock of a receiving device. a first delay tap element among the plurality of consecutive delay tap elements in which an output of the internal oscilloscope matches the known randomized data pattern is identified. responsive to identifying the first delay tap element, a last delay tap element among the plurality of consecutive delay tap elements in which the output of the internal oscilloscope matches the known randomized data pattern is identified.
20240036629.MEMORY DEVICE SENSORS_simplified_abstract_(micron technology, inc.)
Inventor(s): Debra M. Bell of Boise ID (US) for micron technology, inc., Roya Baghi of Boise ID (US) for micron technology, inc., Erica M. Gove of Boise ID (US) for micron technology, inc., Zahra Hosseinimakarem of Boise ID (US) for micron technology, inc., Cheryl M. O'Donnell of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F1/3234, G11C16/26, G11C11/56
Abstract: systems, apparatuses, and methods related to using memory device sensors are described. some memory system or device types include sensors embedded in their circuitry. for instance, a device can be coupled to a memory device with an embedded sensor. the memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. the memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a victim management unit (mu) for performing a media management operation is identified. the victim mu stores valid data. an ordered set cursors is maintained. a source cursor of the ordered set of cursors associated with the victim mu is identified. a target cursor of the ordered set of cursors referencing one or more available mus is identified as the cursor following the source cursor in the ordered set of cursors. the valid data is associated with the identified target cursor.
Inventor(s): Gil Golov of Backnang (DE) for micron technology, inc.
IPC Code(s): G06F3/06, G07C5/04
Abstract: a memory system has a controller (e.g., cpu, fpga, or gpu) and recording segments in a non-volatile memory (e.g., a flash memory device) used by the controller to store data. the controller is configured to: maintain data write counters for the recording segments; select a first segment of the recording segments for recording data from a host system, wherein selecting the first segment comprises scanning the data write counters to identify a first data write counter corresponding to the first segment; receive, from the host system, data to be recorded by the non-volatile memory; and write the received data to the selected first segment.
20240036743.DATA TRANSMISSION MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Carly M. Wantulok of Boise ID (US) for micron technology, inc., Sumana Adusumilli of Boise ID (US) for micron technology, inc., Chiara Cerafogli of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06N20/00
Abstract: methods, apparatuses, and non-transitory machine-readable media associated with data transmission are described. data transmission management can include receiving, from an edge device via a radio at a first device, instructions associated with data transmission between a second device in communication with the first device and a cloud service in communication with the first device. data transmission management can also include managing, at the first device and based on the instructions from the edge device, data received from a memory resource of the second device for transmission to the cloud service and data received from the cloud service for transmission to the memory resource of the second device. data transmission management can further include enabling transmission of some, none, or all of the data between the cloud service and the memory resource of the second device and vice versa based on the management of the data.
Inventor(s): Tomer Eliash of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide superblock management based on memory component reliabilities.
20240036753.WORDLINE LEAKAGE TEST MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Wai Leong Chin of Singapore (SG) for micron technology, inc., Francis Chee Khai Chew of Singapore (SG) for micron technology, inc., Trismardawi Tanadi of Folsom CA (US) for micron technology, inc., Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Lawrence Dumalag of Folsom CA (US) for micron technology, inc., Ekamdeep Singh of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a processing device in a memory sub-system determines whether a media endurance metric associated with a memory block of a memory device satisfies one or more conditions. in response to the one or more conditions being satisfied, a temperature of the memory block is compared to a threshold temperature range. in response to determining the temperature of the memory block is within the threshold temperature range, the processing device causes execution of a wordline leakage test of a wordline group of a set of wordline groups of the memory block. a result of the wordline leakage test of the target wordline group is determined and an action is executed based on the result of the wordline leakage test.
20240036762.BLOOM FILTER INTEGRATION INTO A CONTROLLER_simplified_abstract_(micron technology, inc.)
Inventor(s): Edmund J. Gieske of Cedar Park TX (US) for micron technology, inc., Cagdas Dirik of Indianola WA (US) for micron technology, inc., Elliott C. Cooper-Balis of San Jose CA (US) for micron technology, inc., Robert M. Walker of Raleigh NC (US) for micron technology, inc., Amitava Majumdar of Boise ID (US) for micron technology, inc., Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Yang Lu of Boise ID (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Niccolò Izzo of Vignate (IT) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc., Markus H. Geiger of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0802
Abstract: systems, apparatuses, and methods related to bloom filter implementation into a controller are described. a memory device is coupled to a memory controller. the memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.
Inventor(s): Alex Frolikov of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a computer system having a host in communication with a data storage device is coupled to the host via a peripheral bus and a host interface. the data storage device has a controller, non-volatile storage media; and firmware containing instructions configures the operations of the controller. the host transmits a sequence of commands to the storage device to read data items from, or write data items to, the non-volatile storage media. the storage device examines a subset of the commands to determine whether or not data items identified in the subset are addressed sequentially and optimizes processing of at least a portion of the sequence of commands based on a result of a determination of whether or not data items identified in the subset are addressed sequentially.
Inventor(s): Sanjay Subbarao of Irvine CA (US) for micron technology, inc., Mark Ish of San Ramon CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a memory sub-system configured to partially execute write commands from a host system to optimize performance. after receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. the memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. the host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.
Inventor(s): Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Dung Viet Nguyen of San Jose CA (US) for micron technology, inc., Zixiang Loh of Folsom CA (US) for micron technology, inc., Sampath K. Ratnam of San Jose CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Thomas Herbert Lentz of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
Abstract: a request to access data programmed to a memory sub-system is received. a determination is made of whether memory cells of the memory sub-system that store the programmed data satisfy one or more cell degradation criteria. in response to a determination that the memory cells satisfy the one or more cell degradation criteria, an error correction operation to access the data is performed in accordance with the request.
Inventor(s): Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc., Ferdinando Pascale of Ottaviano (NA) (IT) for micron technology, inc., Roberto Izzi of Caserta (IT) for micron technology, inc., Marco Onorato of Villasanta (MB) (IT) for micron technology, inc., Erminio Di Martino of Quarto (NA) (IT) for micron technology, inc.
IPC Code(s): G06F11/14, G06F1/24, G06F9/4401
Abstract: methods, systems, and devices for hardware reset management for universal flash storage (ufs) are described. a ufs device may initiate a boot-up procedure that includes multiple phases. the ufs device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. the ufs device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. the ufs device may receive the second reset command during the second phase after initiating the portion of the second reset operation. the ufs device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.
20240037033.MANAGING POWER LOSS IN A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Huapeng G. Guan of Redwood City CA (US) for micron technology, inc., Frederick Adi of Castro Valley CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Yipei Yu of San Francisco CA (US) for micron technology, inc., Venkata Naga Lakshman Pasala of Milpitas CA (US) for micron technology, inc., Wei Wang of Dublin CA (US) for micron technology, inc.
IPC Code(s): G06F12/0804, G06F12/1009
Abstract: a system for managing power loss can include a number of memory devices including a volatile memory device and a non-volatile memory device and a processing device operatively coupled with the plurality of memory devices. the processor can save a snapshot of a logical-to-physical (l2p) table to a non-volatile memory device and maintain a journal of updates of the l2p. the processor can retrieve a sequence number from system metadata and save the most recent set of updates of the l2p table to a dedicated area of the non-volatile memory device, where the dedicated area is identified by the sequence number.
Inventor(s): Sanjay Subbarao of Irvine CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc.
IPC Code(s): G06F12/0882, G06F12/0811, G11C11/56, G06F12/02
Abstract: a memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. the memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. when an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. a next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.
Inventor(s): Abhishek Chaurasia of Redmond WA (US) for micron technology, inc., Shakti Nagnath Wadekar of West Lafayette IN (US) for micron technology, inc.
IPC Code(s): G06V10/96, G06V10/764, G06T7/11, G06V10/82, G06V10/80
Abstract: a system for providing an enhanced vision transformer block for mobile vision transformers to perform computer vision tasks, such as image classification, segmentation, and objected detection is disclosed. a local representation block of the block applies a depthwise-separable convolutional layer to vectors of an input image to facilitate creation of local representation outputs associated with the image. the local representation output is fed into a global representation block, which unfolds the local representation outputs, applies vision transformers, and folds the result to generate a global representation output associated with the image. the global representation output is fed to a fusion block, which concatenates the local representations with the global representations, applies a point-wise convolution to the concatenation to generate a fusion block output, and fuses input features of the image with the fusion block out to generate an output to facilitate performance of a computer vision tasks.
20240037960.AUTONOMOUS VEHICLE OBJECT DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Reshmi Basu of Boise ID (US) for micron technology, inc.
IPC Code(s): G06V20/58, G06V10/75, G06F18/24, G06V20/56
Abstract: methods, systems, and apparatuses related to autonomous vehicle object detection are described. an autonomous vehicle can capture an image corresponding to an unknown object disposed within a sight line of the autonomous vehicle. processing resources available to a plurality of memory devices associated with the autonomous vehicle can be reallocated in response to capturing the image and an operation involving the image corresponding to the unknown object to classify the unknown object can be performed using the reallocated processing resources.
20240038284.MEMORY ROW-HAMMER MITIGATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Bryan David Kerstetter of Kuna ID (US) for micron technology, inc., Alan J. Wilson of Boise ID (US) for micron technology, inc., Donald Martin Morgan of Meridian ID (US) for micron technology, inc.
IPC Code(s): G11C7/24, G11C7/10
Abstract: methods, systems, and devices for memory row-hammer mitigation are described. a memory device may operate based on a scheme that is continuous across power cycles. for example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “on” state). accordingly, the value of the counter may be maintained across power cycles.
Inventor(s): Osamu NAGASHIMA of Sagamihara (JP) for micron technology, inc., Yoshinori MATSUI of Sagamihara (JP) for micron technology, inc., Keun Soo SONG of Boise ID (US) for micron technology, inc., Hiroki TAKAHASHI of Tokyo (JP) for micron technology, inc., Shunichi SAITO of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C11/4076, G11C11/408, H03K5/135
Abstract: a clock generator circuit may generate internal data clock signals, such as quadrature phase clock signals, based at least in part, on one clock signal responsive, at least in part, to another clock signal. in some examples, the internal data clock signals may be generated from a system clock signal responsive to a data clock signal. in some examples, the internal data clock signal may be generated by sampling the system clock signal. in some examples, the sampling may be performed responsive to the data clock signal. in some examples, a latch may latch a state of the system clock signal responsive to the data clock signal. the latch may output the internal data clock signal.
Inventor(s): Michael A. Shore of Boise ID (US) for micron technology, inc., Nathaniel J. Meier of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4078, G11C11/406
Abstract: memory with partial array density security is disclosed herein. in one embodiment, an apparatus comprises a memory region including a plurality of memory rows, a plurality of memory columns, and a plurality of memory cells arranged at intersections of the plurality of memory rows and the plurality of memory columns. the plurality of memory rows includes a plurality of enabled memory rows and a plurality of disabled memory rows. sets of one or more disabled memory rows are interleaved with enabled memory rows within the memory region. to write data to or read data from the memory region, the apparatus can be configured to access only the enabled memory rows of the memory region. the apparatus may further be configured to refresh disabled memory rows of the memory region according to a different refresh protocol from a refresh protocol used to refresh the enabled memory rows of the memory region.
20240038291.SELECTABLE ROW HAMMER MITIGATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Edmund J. Gieske of Cedar Park TX (US) for micron technology, inc., Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Niccolò Izzo of Vignate (IT) for micron technology, inc.
IPC Code(s): G11C11/4078, G11C11/4096, G11C11/4076
Abstract: an apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. the controller can be configured to determine whether a quantity of row activations directed to a row of the memory devices exceeds a row hammer criterion. the controller can be configured to select, responsive to determining that the row hammer criterion is met, a row hammer mitigation response from a plurality of row hammer mitigation responses available for initiation. the controller can be configured to initiate the selected row hammer mitigation response.
20240038301.MEMORY CELL READ OPERATION TECHNIQUES_simplified_abstract_(micron technology, inc.)
Inventor(s): Riccardo Muzzetto of Arcore (MB) (IT) for micron technology, inc., Francesco Mastroianni of Melzo (MI) (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc., Nevil N. Gajera of Meridian ID (US) for micron technology, inc.
IPC Code(s): G11C13/00
Abstract: methods, systems, and devices for memory cell read operation techniques are described. a memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. for example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. in some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. as part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.
20240038311.RELIABILITY BASED DATA VERIFICATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Ankit V. Vashi of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Jung Sheng Hoei of Newark CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/08
Abstract: a method includes designating a first subset of non-volatile memory with a first reliability designation, designating a second subset of non-volatile memory blocks with a second reliability designation, configuring the first subset of non-volatile memory blocks and the second subset of non-volatile memory blocks in a first verification mode, writing data to first subset of non-volatile memory blocks and the second subset of non-volatile memory blocks in the absence of write verification.
Inventor(s): Meng Wei of Shanghai (CN) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/16, G11C16/32
Abstract: disclosed herein are methods, apparatuses and systems related to adjusting operation of memory dies according to reliability measures determined in real-time. the apparatus may be configured to determine the reliability measures based on (1) initiating and completing a programming operation within respective timings following an erase operation and (2) reading the programmed data within a window from completing the programming operation.
Inventor(s): Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Eric N. Lee of San Jose CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Tomoharu Tanaka of Kanagawa (JP) for micron technology, inc.
IPC Code(s): G11C29/12
Abstract: a memory device includes a memory array including wordlines and at least one string of cells. each cell of the at least one string of cells is addressable by a respective wordline. the memory device further includes control logic, operatively coupled to the memory array, to perform operations including generating gate-induced drain leakage (gidl) with respect to the at least one string of cells, and causing a grounding voltage to be applied to a set of wordlines to ground each cell of the at least one string of cells addressable by each wordline of the set of wordlines. the grounding voltage applied to the set of wordlines enables transport of positive charge carriers generated by the gidl. in some embodiments, the positive charge carriers neutralize a buildup of negative charge carriers generated during a seeding phase of a program refresh operation.
Inventor(s): Scott E. SCHAEFER of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/46, G11C29/42, G11C7/10
Abstract: implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test using a data mask inversion (dmi) bit. a memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. the memory device may identify a first dmi bit of the memory device that is associated with indicating a status of the memory built-in self-test and a second dmi bit of the memory device that is not associated with indicating the status of the memory built-in self-test. the memory device may set the first dmi bit to a first value based on the one or more bits indicating that the memory built-in self-test is enabled. the memory device may perform the memory built-in self-test based on setting the first dmi bit to the first value.
Inventor(s): Subhasis Sasmal of Hyderabad (IN) for micron technology, inc., Dong Pan of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/50, G11C29/12, G01R19/165
Abstract: an electronic device, such as a memory device, may include various circuit components. the electronic device may also include one or more voltage testing circuits to determine whether signals of one or more of the circuit components are within acceptable voltage ranges of the respective circuit components. systems and methods are described to improve correct voltage measurement of the received signals by a voltage testing circuit. in particular, multiple supply voltage levels are provided to different components of the voltage testing circuit to provide a sufficient headroom voltage gap between received signals and the supply voltages. for example, some active circuits (e.g., operational amplifiers) of the voltage testing circuit may receive a higher supply voltage of the electronic device compared to one or more other circuits of the voltage testing circuit.
20240038322.PERFORMING SENSE OPERATIONS IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Michele Maria Venturini of Milan (IT) for micron technology, inc., Umberto Di Vincenzo of Capriate San Gervasio (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc., Christophe Vincent Antoine Laurent of Agrate Brianza (IT) for micron technology, inc., Christian Caillat of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/50
Abstract: apparatuses, methods, and systems for performing sense operations in memory are disclosed. the memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. the second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.
20240038577.ISOLATION REGIONS WITHIN A MEMORY DIE_simplified_abstract_(micron technology, inc.)
Inventor(s): Raja Kumar Varma Manthena of Boise ID (US) for micron technology, inc., Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc.
IPC Code(s): H01L21/762, H01L27/11582, H01L27/11556, H01L21/311
Abstract: methods, systems, and devices for isolation regions within a memory die are described. during fabrication, memory pillars may be formed through a stack of material in a plurality regions of a memory die. in some cases, a first plurality of trenches extending in a first direction and a second plurality of trenches extending in a second direction may be formed through the stack of material (e.g., interposed between the plurality of regions). additionally or alternatively, first voids may be formed via the first plurality of trenches, and a dielectric material may be deposited in the first voids and the first plurality of trenches, forming first isolation regions. then, second voids may be formed via the second plurality of trenches, and a dielectric material may be deposited in the second voids and the second plurality of trenches, forming second isolation regions.
Inventor(s): Terrence B. McDaniel of Boise ID (US) for micron technology, inc., Vinay Nair of Boise ID (US) for micron technology, inc., Russell A. Benson of Boise ID (US) for micron technology, inc., Christopher W. Petz of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc., Silvia Borsari of Boise ID (US) for micron technology, inc., Ping Chieh Chiang of Boise ID (US) for micron technology, inc., Luca Fumagalli of Rio Rancho NM (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L27/108
Abstract: a method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. the sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. the sacrificial line structures are replaced with additional trenches. conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures. conductive line structures are formed within the additional trenches and in contact with the conductive contact structures.
Inventor(s): Tetsuji Takahashi of Inagi (JP) for micron technology, inc.
IPC Code(s): H01L23/522, H01L27/108
Abstract: disclosed herein is an apparatus that includes a plurality of signal wiring patterns, a plurality of shield patterns each provided between corresponding two of the signal wiring patterns, a common pattern coupled to each of the plurality of shield patterns, and a transistor coupled between the common pattern and a power line supplied with a fixed power potential.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/538, G11C5/06, H10B12/00
Abstract: a microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. the first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. the second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. the microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of digit lines, the second cross-sectional area smaller than the first cross-sectional area. related microelectronic devices, memory devices, electronic systems, and methods are also described.
Inventor(s): Faxing Che of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., Yeow Chon Ong of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: in some embodiments, a semiconductor device assembly can include a first semiconductor die, a second semiconductor die, and an interconnection structure therebetween. the interconnection structure can directly electrically couple the first and the second semiconductor dies. the interconnection structure can include an inner metallic pillar, an outer metallic shell, a continuous metallic bridging layer, and a dielectric liner. the outer metallic shell can surround and be spaced from the inner metallic pillar, the continuous metallic bridging layer can be over and connected with the inner metallic pillar and the outer metallic shell, and the dielectric liner can be between the inner metallic pillar and the outer metallic shell. in some embodiments, the second semiconductor die can be excluded and the interconnection structure can solely be coupled to the first semiconductor die.
Inventor(s): Andrew M. Bayless of Boise ID (US) for micron technology, inc., Cassie M. Bayless of Boise ID (US) for micron technology, inc., Brandon P. Wirz of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
Abstract: in some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. the interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. the first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. the first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. the second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. the second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Yuan He of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L25/18, H01L25/00
Abstract: a microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. the memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. the microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. related microelectronic devices, memory devices, electronic systems, and methods are also described.
Inventor(s): James E. Davis of Meridian ID (US) for micron technology, inc., Milind Nemchand Furia of Boise ID (US) for micron technology, inc., Michael D. Chaine of Boise ID (US) for micron technology, inc., Eric J. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/02, H01L21/8222, G11C16/30, G11C5/14
Abstract: an apparatus includes a protection circuit electrically connected to first and second voltage domains. the protection circuit includes a first silicon-controlled rectifier (scr) and a second scr connected in anti-parallel configuration. the first scr is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. the second scr is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. the protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.
20240039185.CONNECTION DESIGNS FOR MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Wei Yu of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc.
IPC Code(s): H01R12/52, H01R12/73, H01R12/71
Abstract: methods, systems, and devices for connection designs for memory systems are described. a memory system may include a package and a printed circuit board (pcb). an interface of the package may be coupled with the pcb via a set of springs, where each spring may include a material configured to deform based at least in part on a shape of the package, a shape of the pcb, or both. the memory system may also include a set of latches that may secure the package in a fixed position relative to the pcb. that is, the set of springs may provide an electrical connection between the package and the pcb, and the set of latches may provide a mechanical connection between the package and the pcb. in some examples, the package, the pcb, or both, may include one or more connection structures configured to receive the latches.
Inventor(s): Zhanqiang Su of Boise ID (US) for micron technology, inc., Junjun Wang of Boise ID (US) for micron technology, inc.
IPC Code(s): H04L1/00, H04L1/20, H04L1/18
Abstract: methods, systems, and devices for enhanced negative acknowledgment control (nac) frame are described. a device may generate and communicate an enhanced nac frame that includes additional error information to indicate to the device a cause for the error. the device may receive a data frame and determine an error condition associated with a set of layers of a protocol stack. the device may generate feedback indicating a cause for the determined error condition and transmit the feedback indicating the error cause. the feedback may be a nac that includes a first quantity of bits configured for indicating an existence of an error and a second quantity of bits configured for indicating the error cause. a format of the nac frame may include bits configured to identify multiple types of error causes associated with the different layers of the protocol stack.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Terrence B. McDaniel of Boise ID (US) for micron technology, inc., Beau D. Barry of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
Abstract: a method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. a second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. the second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. microelectronic devices, electronic systems, and additional methods are also described.
Inventor(s): SOSHI SATO of Sagamihara (JP) for micron technology, inc.
IPC Code(s): H01L27/112
Abstract: according to one or more embodiments of the disclosure, an antifuse is provided. the antifuse includes a semiconductor substrate, a dielectric oxide layer on the semiconductor substrate, and a conductive gate layer on the dielectric oxide layer. the dielectric oxide layer includes halogen to facilitate breakdown of the dielectric oxide layer upon application of an antifuse programming voltage.
Inventor(s): Raja Kumar Varma Manthena of Boise ID (US) for micron technology, inc., Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc.
IPC Code(s): H01L27/1157, H01L27/11531, H01L27/11529, G11C16/06
Abstract: methods, systems, and devices for lateral etch stops for access line formation in a memory die are described. a memory die may be formed with isolation regions that provide an etch stop to limit the extent of voids formed by removing a sacrificial material between layers of a dielectric region. for example, first trenches may be formed through a stack of alternating layers of a dielectric material and a sacrificial material, in which one or more materials may formed. second trenches may be formed between a first trench and an array portion of the memory die, or between pairs of the first trenches, which may support the removal of at least a portion of the sacrificial material to form voids for access line formation. however, the materials formed in the first trenches may provide a boundary, or a restriction zone, that limits an extent of the material removal operation.
20240040790.METAL GATE STACKS FOR CMOS SCALING_simplified_abstract_(micron technology, inc.)
Inventor(s): Pengyuan Zheng of Boise ID (US) for micron technology, inc., Yongjun Jeff Hu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/11573, H01L27/11556, H01L27/11526, H01L27/11582
Abstract: a variety of applications can include apparatus having a memory device structured with an array of memory cells and a complementary metal-oxide-semiconductor (cmos) device coupled to the array. the cmos device can include a gate electrode on and contacting the polysilicon gates of a p-channel metal-oxide-semiconductor (pmos) transistor and a n-channel metal-oxide-semiconductor (nmos) transistor of the cmos device, where the gate electrode is a multi-metal stack. the multi-metal stack of the gate electrode can be two levels of different metal compositions.
Micron Technology, Inc. patent applications on February 1st, 2024
- Micron Technology, Inc.
- F16L3/10
- Micron technology, inc.
- G05F1/575
- G11C5/14
- G06F1/14
- G06F1/3234
- G11C16/26
- G11C11/56
- G06F3/06
- G07C5/04
- G06N20/00
- G06F12/0802
- G06F11/10
- G06F11/14
- G06F1/24
- G06F9/4401
- G06F12/0804
- G06F12/1009
- G06F12/0882
- G06F12/0811
- G06F12/02
- G06V10/96
- G06V10/764
- G06T7/11
- G06V10/82
- G06V10/80
- G06V20/58
- G06V10/75
- G06F18/24
- G06V20/56
- G11C7/24
- G11C7/10
- G11C11/4076
- G11C11/408
- H03K5/135
- G11C11/4078
- G11C11/406
- G11C11/4096
- G11C13/00
- G11C16/34
- G11C16/08
- G11C16/10
- G11C16/16
- G11C16/32
- G11C29/12
- G11C29/46
- G11C29/42
- G11C29/50
- G01R19/165
- H01L21/762
- H01L27/11582
- H01L27/11556
- H01L21/311
- H01L21/768
- H01L27/108
- H01L23/522
- H01L23/538
- G11C5/06
- H10B12/00
- H01L23/00
- H01L25/065
- H01L25/18
- H01L25/00
- H01L27/02
- H01L21/8222
- G11C16/30
- H01R12/52
- H01R12/73
- H01R12/71
- H04L1/00
- H04L1/20
- H04L1/18
- H01L27/112
- H01L27/1157
- H01L27/11531
- H01L27/11529
- G11C16/06
- H01L27/11573
- H01L27/11526
- G06F3/0679
- G06F3/0604
