Micron Technology, Inc. patent applications on February 15th, 2024
Patent Applications by Micron Technology, Inc. on February 15th, 2024
Micron Technology, Inc.: 52 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (16), G06F3/0679 (12), G06F3/0659 (8), G11C16/10 (7), G11C16/26 (6)
With keywords such as: memory, data, device, based, semiconductor, systems, voltage, methods, include, and write in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Curtis W. Egan of Brighton CO (US) for micron technology, inc.
IPC Code(s): G06F1/30, G06F11/14
Abstract: a block storing corrupt data is detected. based on detecting the block storing corrupt data, threshold voltage (v) distribution data corresponding to the block is accessed. the vdistribution data comprises one or more vdistribution measurements corresponding to the block. the vdistribution data corresponding to the block is compared with reference vdistribution data. the reference vdistribution data comprises one or more reference vdistributions. based on a result of the comparison, it is determined whether to perform one or more heroic data recovery processes on the block.
Inventor(s): Jay Sarkar of San Jose CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Ipsita Ghosh of New Garia (IN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations including applying an ordered set of error-handling operations to be performed on data residing in a segment of the memory device as an input to a trained machine learning model, wherein the trained machine learning model is based on latency data for previously-performed error-handling operations; and obtaining an output of the trained machine learning model, the output comprising a reordered set of error-handling operations to be performed on the data residing in the segment of the memory device, and wherein the reordered set adjusts an order of one or more error-handling operations of the ordered set of error-handling operations.
20240053894.SUSPENDING OPERATIONS OF A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): David Aaron Palmer of Boise ID (US) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for suspending operations of a memory system are described. a memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.
20240053895.WRITE QUALITY IN MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc., David Aaron Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for improving write quality in memory systems are described. the memory system may receive, from a host system, a command to perform an operation. the memory system may determine an availability parameter that indicates processing resources of the memory system that are available to perform the operation based on receiving the command. in some cases, the memory system may transmit, to the host system, a message comprising the availability parameter, and the host system may delay transmission of one or more pending commands based on receiving the message comprising the availability parameter.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and apparatuses include receiving a command directed to a portion of memory. a cycle number for the portion of memory is determined. a group to which the portion of memory belongs is determined. a sensing time is determined using the cycle number and the group. the command is executed using the sensing time.
Inventor(s): Rakeshkumar Dayabhai Vaghasiya of Hyderabad (IN) for micron technology, inc., Anilkumar Rameshbhai Sindhi of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for sequential write operations using multiple memory dies are described. a memory system may be configured to support write operations that include writing respective subsets of a sequence of data to each first memory die of a set of multiple first memory dies, and then writing the sequence of data to a second memory die (e.g., based on reading the respective subsets of the sequence of data from the set of first memory dies). in some examples, such techniques may be implemented with memory dies having different memory cell storage densities. for example, the set of multiple first memory dies may be operated in accordance with relatively lower storage densities to leverage relatively faster access operations, whereas the second memory die may be operated in accordance with a relatively higher storage density to leverage relatively higher capacity.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and apparatuses include receiving a command directed to a portion of memory. a cycle number for the portion of memory is determined. a group to which the portion of memory belongs is determined. a bitline voltage is determined using the cycle number and the group. the command is executed using the bitline voltage.
Inventor(s): Christophe Vincent Antoine Laurent of Agrate Brianza (MB) (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (MB) (IT) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for balanced codewords for reducing a selected state in memory cells are described. a memory device may divide a sequence of data bits into sets of bits associated with different bit-positions in a coding scheme. the memory device may then balance a first codeword that includes the first set of the data bits in the binary domain to reach a target ratio of logic values for the codeword. using the first codeword and the other set(s) of data bits, the memory device may balance the remaining two states in the state domain to reach an overall target distribution of the three states. the memory device may then generate one or more codeword(s) for the other set(s) of data bits so that the memory device can write all of the codewords to ternary cells.
20240053905.COMPRESSION AND DECOMPRESSION OF TRIM DATA_simplified_abstract_(micron technology, inc.)
Inventor(s): Reshmi Basu of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc., Stephen Hanna of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for compression and decompression of trim data are described. a memory system may store one or more trim settings to a volatile memory in a compressed manner, and may expand (e.g., decompress) the data as part of a write operation to a non-volatile memory (e.g., during a start-up procedure). for example, compressed (e.g., non-expanded) data including trim settings may be stored to a volatile memory, and a portion of the array of volatile memory cells may be temporarily allocated to expand the data (e.g., copy the data, invert the data, copy the inverted data). once the data is expanded, it may be stored in the non-volatile memory, and the temporarily allocated portion of the array of volatile memory cells may be reallocated (e.g., allocated for another purpose). the expanded data may include multiple copies and inverted copies of the trim settings.
20240053908.TEMPERATURE-DEPENDENT REFRESH OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Martin Brox of Munich (DE) for micron technology, inc., Elena Cabrera Bernal of Munich (DE) for micron technology, inc., Milena Tsevetkova Ivanov of Munich (DE) for micron technology, inc., Manfred Hans Plan of Munich (DE) for micron technology, inc., Oleg Sakolski of Munich (DE) for micron technology, inc., Filippo Vitale of Dachau (DE) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for temperature-dependent refresh operations are described. a memory system may adjust refresh operations based on a temperature of the memory system to reduce a refresh current and improve reliability of the refresh operations. for example, the memory system may include a temperature sensor configured to provide temperature information associated with a memory device. based on the temperature information, the memory system may, in response to a refresh command, activate a set of access lines (e.g., word lines) to refresh memory cells coupled with the access lines, where a count of the set of access lines (e.g., how many access lines are included in the set) may be based on the temperature information. in some examples, the count of the set may be determined based on comparing the temperature information to one or more temperature thresholds.
20240053911.ASSIGNING BLOCKS OF MEMORY SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Caixia Yang of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for assigning blocks of memory systems are described. some memory systems may be configured to initiate an operation to characterize a plurality of blocks of a memory system; identify a first quantity of complete blocks of the plurality of blocks and a second quantity of reduced blocks of the plurality of blocks based at least in part on initiating the operation; determine, for a block of the second quantity of reduced blocks, whether a quantity of planes available for use to store the information in the block satisfies a threshold; and assign the block as a special function block configured to store data associated with a function of the memory system based at least in part on determining that the quantity of planes available for use to store the information in the block of the second quantity of reduced blocks satisfies the threshold.
20240053916.RESUMING WRITE OPERATIONS AFTER SUSPENSION_simplified_abstract_(micron technology, inc.)
Inventor(s): Amiya Banerjee of Bangalore (IN) for micron technology, inc., Kranthi Kumar Vaidyula of Bangalore (IN) for micron technology, inc., Shreesha Prabhu of Singapore (SG) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for resuming write operation after suspension are described. a memory system may be configured to determine an upper limit of a threshold voltage of a page of a block at which a performance of a write operation was suspended based at least in part on an indication to resume the performance of the write operation that was previously suspended at a memory system; determine a difference between a first quantity of a first logic state stored in the page and a second quantity of the first logic state associated with an unsuspended write operation based at least in part on determining the upper limit of the threshold voltage; and resume the performance of the write operation based at least in part on determining the difference between the first quantity of the first logic state and the second quantity of the first logic state.
Inventor(s): Olivier Duval of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for techniques for storing journaling information are described. a memory device may receive a first command to configure a circular buffer using memory cells of a nonvolatile memory device. the first command may include one or more labels associated with the circular buffer. the memory device may configure the circular buffer based at least in part on receiving the first command. the memory device may receive a second command to write journaling data to the nonvolatile memory device based at least in part on configuring the circular buffer. the second command may specify a label of the one or more labels. the memory device may generate an entry at a physical address indicated by a pointer of the circular buffer available to store the journaling data in the circular buffer based at least in part on the label specified by the second command.
Inventor(s): Deping He of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for commands to support adaptive memory systems are described. a memory system may be configured to receive a command to perform an operation on an address of a memory system, the command including an indication of a count of program/erase cycles associated with the address; determine whether the count of program/erase cycles associated with the address satisfies a threshold; adjust a trim parameter for operating the memory system based at least in part on determining that the indication of the count of program/erase cycles satisfies the threshold; and perform the operation associated with the command using the adjusted trim parameter.
20240053924.MEMORY SUB-SYSTEM TRANSFER QUEUE RETENTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Vinay Sandeep of Bangalore (IN) for micron technology, inc., Sanandan Sharma of Hyderabad (IN) for micron technology, inc., Amit Bhardwaj of Bangalore (IN) for micron technology, inc., Prashanth Reddy Enukonda of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a method includes issuing a program command to a logic unit (lun) of a memory device, writing a plurality of commands to a transfer queue within the memory device, detecting a program failure for the lun of the memory device, and maintaining a number of the plurality of commands in the transfer queue.
20240053925.CACHING FOR MULTIPLE-LEVEL MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Reshmi Basu of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Nitul Gohain of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02
Abstract: methods, systems, and devices for caching for a multiple-level memory device are described. first data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. later, second data writing to the memory device may be received. based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
20240054037.COMMON RAIN BUFFER FOR MULTIPLE CURSORS_simplified_abstract_(micron technology, inc.)
Inventor(s): Rakeshkumar Dayabhai Vaghasiya of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F11/00, G06F12/02
Abstract: methods, systems, and devices for a common error protection buffer for multiple cursors are described. a memory device may receive a command to write data to a memory system. the memory device may assign portions of the data to respective pages of a first cursor and generate error protection data for the assigned data. the memory device may assign the generated error protection data to an error protection buffer common to multiple cursors, for example, by performing an combination operation. the memory device may increment a counter associated with the error protection buffer. the memory device may write a summary of contents of the error protection buffer and a position of each cursor related to the error protection data based on the counter satisfying a threshold. the memory device may perform a readback operation to facilitate garbage collection without losing error protection data.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07, G06F21/60, G06F21/64
Abstract: in some aspects, the techniques described herein relate to a system including: a memory device including a secure storage area; a server configured to generate cryptographic data and compute a cyclical redundancy check (crc) value of the cryptographic data; and a manufacturer computing device configured to receive the cryptographic data and the crc value and issue a command including the cryptographic data and the crc value to the memory device, wherein the memory device is configured to compute a local crc value using the cryptographic data in the command, compare the local crc value to the crc value, and write the cryptographic data to the secure storage area when the local crc value matches the crc value.
Inventor(s): Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G11C29/08
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations comprising selecting a source set of memory cells of the memory device, performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; responsive to determining that a data integrity metric value satisfies the threshold criterion, performing a first error-handling operation on the data stored on the source set of memory cells; responsive to determining that the first error-handling operation fails to correct the data, performing a second error-handling operation on the data; and responsive to determining that the second error-handling operation corrected the data, causing the memory device to copy the corrected data to a destination set of memory cells of the memory device.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Huai-Yuan Tseng of San Ramon CA (US) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Jonathan Scott Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
Abstract: a system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. the user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. upon stress event completion, pages having user data with the extra error correction code data are scanned. if pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. the extra error correction code data is deleted from the second block and the second block is made available for user data.
20240054049.DYNAMIC PARITY SCHEME_simplified_abstract_(micron technology, inc.)
Inventor(s): Gennaro Schettino of Casamicciola Terme (NA) (IT) for micron technology, inc., Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
Abstract: methods, systems, and devices for a dynamic parity scheme are described. a memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. in some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. for example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.
Inventor(s): Prashant Parashari of Hyderabad (IN) for micron technology, inc., Gaurav Singh of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F11/10, H03M13/11, H03M13/00
Abstract: a sign bit of a low-density parity-check (ldpc) codeword associated with a translation unit (tu) can be generated by performing an xor operation on a rain drop corresponding to the tu and a raw read of the tu. the ldpc codeword can include a hard bit and three soft bits that include the sign bit. the ldpc codeword can be decoded using the hard bit and the three soft bits. a read recovery operation can be performed on the tu using the decoded ldpc codeword.
Inventor(s): Tony Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): G06F15/82, G06F9/4401
Abstract: disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. that is, the programmable atomic unit will send a response to the calling processor. the calling processor will recognize that the exception has been raised and will handle the exception. because the calling processor knows which process triggered the exception, the calling processor (e.g., the operating system) can take appropriate action, such as terminating the calling process. the calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): G06F21/57, G06F9/4401
Abstract: in some aspects, the techniques described herein relate to a system including: a storage array; a controller configured to detect a shutdown event; and an auto-measure circuit configured to: generate a plurality of measurements corresponding to a plurality of layers of a boot sequence, each layer including executable code used to generate a respective measurement; compare the plurality of measurements to a respective plurality of golden measurements; update flags associated with the plurality of layers based on the comparing; and instruct the controller to shut down the system after updating the flags.
Inventor(s): Gil Golov of Backnang (DE) for micron technology, inc.
IPC Code(s): G08G1/0967, G08G1/0969, G01W1/14, G01W1/10, G08G1/0968
Abstract: systems, methods, and apparatus related to determining ice hazards on roads based on crowdsourced data from vehicles. in one approach, a server receives weather data and location data from each of several vehicles. the weather data is timestamped when received. the server determines, using the location data, a geographic region in which each vehicle is located. the weather data is stored in a database associated with the respective geographic region for the vehicle that transmitted the weather data. the server periodically scans the database to select weather data received over a selected time period. the selected data is analyzed to determine whether an ice hazard exists for one or more regions. a communication is sent to vehicles in those regions having the determined ice hazard.
20240054971.CONFIGURABLE TYPES OF WRITE OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G09G5/08, G11C16/10
Abstract: methods, systems, and devices for configurable types of write operations are described. a memory device may receive a write command to write data in a zone of a memory system. the memory device may identify a physical address to store the data using a cursor associated with the zone based at least in part on receiving the write command. in some examples, the cursor may be associated with a type of a write operation based on a quantity of data associated with the cursor. as such, the memory device write, using a first type of the write operation or a second type of the write operation in accordance with the quantity of data, the data, and an indication of the type of the write operation used to write the data into the memory system.
Inventor(s): Tae H. Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/408
Abstract: a boost circuit is used to provide boosting voltage to a common boost node of a plurality of sub-word line drivers in memory systems and devices. the boost circuit includes a metal insulator metal capacitor. by using the boost circuit, the plurality of sub-word line drivers are configured to output a certain voltage to local word lines without using high dc generators to generate high voltages (4.2 volts or more). the area of the semiconductor substrate used for fabricating the sub-word line drivers is reduced, and thus reduce the cost or increasing the capacity of the memory devices.
Inventor(s): Ki-Jun Nam of Allen TX (US) for micron technology, inc.
IPC Code(s): G11C11/4091
Abstract: a memory device includes a memory cell that stores data. the memory device also includes a pair of digit lines that carry the data from the memory cell. the memory device further includes a sense amplifier that senses and amplifies voltages received at the pair of digit lines. the memory device also includes a replica sense amplifier that generates a replica common mode voltage associated with a common mode voltage of the pair of digit lines.
Inventor(s): Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Aswin Thiruvengadam of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/4076, G11C7/24
Abstract: methods, systems, and devices for a model for predicting memory system performance are described. a memory system may generate a set of read commands and perform a first set of read operations at a memory device according to the generated read commands. the memory system may generate information indicating a performance of the memory device based on the first set of read operations and may update one or more coefficients of a model that correlates the information with a change in a read window. in some cases, the memory system may model the change in a read window based on the information and update one or more parameters associated with read operations based on the modelled change in the read window. the memory system may perform a second set of read operations at the memory device using the one or more updated parameters.
Inventor(s): Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G11C16/08, G11C16/34, G11C16/10, G06F3/06
Abstract: embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Vivek Shivhare of Milpitas CA (US) for micron technology, inc., Vinh Diep of Hayward CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/32, G11C16/08, G11C29/52
Abstract: methods, systems, and apparatuses include determining an operation type for an operation. a sensing time is elected using the operation type. the operation is executed using the sensing time.
20240055054.INDEPENDENT SENSING TIMES_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/12, G11C16/10, G11C16/26
Abstract: a method includes determining that a program operation includes a first pass to apply a first voltage distribution to a plurality of memory cells and a second pass to apply a second voltage distribution to the plurality of memory cells, performing the first pass of the program operation using a first sensing time, and performing the second pass of the program operation using a second sensing time during the second pass of the program operation, where the first sensing time is shorter than the second sensing time.
20240055056.STORING BITS WITH CELLS IN A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Daniele Vimercati of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G11C16/26, G11C13/00, G11C16/12, G11C11/22
Abstract: methods, systems, and devices for storing bits, such as n−1 bits, with cells, such as n cells, in a memory device are described. a memory device may generate a first sensing voltage that is based on a first voltage of a first digit line and a second voltage of a second digit line. the memory device may also generate a second sensing voltage that is based on a third voltage of a third digit line and a fourth voltage of a fourth digit line. the memory device may then determine a bit value based at least in part on a difference between the first sensing voltage and the second sensing voltage.
Inventor(s): Jeremy Binfet of Boise ID (US) for micron technology, inc., Liang Yu of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/30, G11C5/06
Abstract: a memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (ppm) token during a current ppm cycle, in response to receiving the ppm token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current ppm cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a ppm cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current ppm cycle.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc., Tomer Tzvi ELIASH of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/32, G11C16/10, G11C16/24
Abstract: implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. in some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. the memory device may set a flag value based on comparing a transition time and a transition time threshold. the transition time may be a time to transition from a first voltage to a second voltage during the program operation. the memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.
Inventor(s): Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/08, G11C16/26
Abstract: embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a target read window budget (rwb) increase, wherein the target rwb increase corresponds to a maximum rwb increase associated with using a different pv voltage offset for each respective programming level of a memory cell. embodiments can also include segmenting the plurality of wordlines into one or more wordline groups, wherein each wordline group comprises one or more wordlines. embodiments can further include determining, for each wordline group, a target adjustment to a parameter of a memory access operation that is performed with respect to a memory cell associated with a wordline of the wordline group. embodiments can include determining an aggregate rwb increase for the block in view of the target adjustment to the parameter of the memory access operation. embodiments can further include determining that the aggregate rwb increase for the block satisfies a threshold range associated with the target rwb increase. embodiments can also include modifying the parameter of the memory access operation according to the target adjustment.
20240055190.PROGRAMMABLE CHALCOGENIDE CAPACITORS_simplified_abstract_(micron technology, inc.)
Inventor(s): Hongmei Wang of Boise ID (US) for micron technology, inc., Huiqi Gong of Redmond WA (US) for micron technology, inc., Peng Zhao of Boise ID (US) for micron technology, inc., Jingshan Wang of Eagan MN (US) for micron technology, inc., Giovanni Ferrari of Boise ID (US) for micron technology, inc.
IPC Code(s): H01G7/06
Abstract: methods, systems, and devices for programmable chalcogenide capacitors are described. a first programming pulse may be applied, for a first duration, to a capacitor comprising a chalcogenide material to adjust a capacitance of the capacitor from a first capacitance to a second capacitance. a pulse may be applied to the capacitor based on applying the first programming pulse to the capacitor. a first voltage may be stored in the capacitor based on adjusting the capacitance of the capacitor from the first capacitance to the second capacitance, and the first voltage may be stored based on the capacitor having the second capacitance.
Inventor(s): Ren Yuan Huang of Taichung (TW) for micron technology, inc., Kuan Wei Tseng of Taichung (TW) for micron technology, inc., Te Pao of Taichung (TW) for micron technology, inc., Koji Torii of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/48, H01L23/00, H01L21/768
Abstract: a semiconductor device assembly including a through-silicon via (tsv) having an end region protruding from a back side of the substrate, the end region being surrounded by a conductive annulus disposed over the back side of the substrate; a dielectric layer disposed over the back side of the substrate, the dielectric layer having an upper surface flush with an upper surface of the end region of the tsv and flush with an upper surface of the conductive annulus; and a bond pad disposed over and electrically coupled to the end region of the tsv and the conductive annulus.
Inventor(s): Mark S. Swenson of Meridian ID (US) for micron technology, inc., Surendranath C. Eruvuru of Boise ID (US) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L27/11565, H01L27/1157, H01L27/11582, H01L23/532, H01L21/768
Abstract: an electronic device comprises a stack comprising an alternating sequence of conductive structures and insulative structures arranged in tiers, and at least one dielectric-filled slot extending vertically through the stack and extending in a first horizontal direction. the at least one dielectric-filled slot is defined between two internal sidewalls of the stack. the electronic device comprises additional dielectric-filled slots extending vertically through the stack and extending in a second horizontal direction transverse to the first horizontal direction, and isolation structures laterally interposed between the at least one dielectric-filled slot and the additional dielectric-filled slots. the isolation structures are laterally adjacent to the conductive structures of the stack, and at least some of the isolation structures are vertically adjacent to the insulative structures of the stack. related systems and methods of forming the electronic devices are also disclosed.
Inventor(s): Brandon P. Wirz of Boise ID (US) for micron technology, inc., Andrew M. Bayless of Boise ID (US) for micron technology, inc., Owen R. Fay of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L23/552, H01L23/00, H01L25/065, H01L21/56
Abstract: a semiconductor device assembly, including a lower semiconductor die; a stack of upper semiconductor dies disposed over the lower semiconductor die; a conductive package perimeter material surrounding the stack of upper semiconductor dies; and an encapsulant material disposed between sidewalls of the stack of upper semiconductor dies and the conductive package perimeter material, and horizontally extending between the conductive package perimeter material and the lower semiconductor die. a method of forming a plurality of semiconductor assemblies, including stacking a plurality of semiconductor die stacks on a device wafer; disposing a pre-formed spacer assembly structure including a spacer material and a conductive package perimeter material around each of the plurality of semiconductor die stacks; disposing an encapsulant material between the conductive package perimeter material of the pre-formed spacer assembly structure and the corresponding semiconductor die stack; and singulating the device wafer to form the plurality of semiconductor device assemblies.
Inventor(s): Thiagarajan Raman of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/538, H01L23/495, H01L23/492, H01L23/66, H01L23/498
Abstract: this document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with through-substrate connections for recessed semiconductor dies. a semiconductor device assembly is described that includes a substrate having a first cavity and a second cavity. a first connective element is located at a side surface of the first cavity and a second connective element is located at a side surface of the second cavity. the semiconductor device assembly include a first semiconductor die and a second semiconductor die implemented at the first cavity and the second cavity, respectively. the first semiconductor die includes a third connective element at an edge surface of the die. the second semiconductor die includes a fourth connective element at an edge surface of the die. the dies are implemented at the cavities and connected through the connective elements to electrically couple the first die to the second die.
Inventor(s): Kunal R. Parekh of Boise ID (US) for micron technology, inc., Bret K. Street of Meridian ID (US) for micron technology, inc., Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Wei Zhou of Boise ID (US) for micron technology, inc., Thiagarajan Raman of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L25/00
Abstract: this document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. a semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. the substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. the semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. in doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.
Inventor(s): Travis M. Jensen of Boise ID (US) for micron technology, inc., David R. Hembree of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L25/00
Abstract: semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. in one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. the first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. in some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. the first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.
Inventor(s): Bingwu Liu of Meridian ID (US) for micron technology, inc., Shivani Srivastava of Boise ID (US) for micron technology, inc., Dan Mihai Mocuta of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/78, H01L27/108, H01L29/66, H01L29/08, H01L21/8234
Abstract: electronic devices and methods are disclosed, including transistors with thick gate dielectric layers. selected devices and methods shown include multiple layer gate dielectrics. selected devices and methods shown include a gate dielectric with a first layer having a first width, and a second layer over the first layer, wherein the second layer has a second width smaller than the first width.
20240055524.FINFETS WITH REDUCED PARASITICS_simplified_abstract_(micron technology, inc.)
Inventor(s): Wenjun Li of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L29/78, H01L29/08, H01L29/66, H01L27/108, H01L27/088, H01L21/8234
Abstract: a variety of applications can include apparatus having a fin field-effect transistor with a gate wrapping around fins to maintain good channel control and planar source and drain regions to reduce miller capacitance and contact resistance. the reduced parasitic capacitance and resistance can be translated into higher performance and lower power. a fin field-effect transistor can include a bulk semiconductor region having a planar source region structured as a first top portion of the bulk semiconductor region and a planar drain region structured as a second top portion of the bulk semiconductor region, with one or more semiconductor fins contacting the planar source region and the planar drain region with a gate wrapped around the one or more semiconductor fins.
Inventor(s): Alexander Tomlinson of Austin TX (US) for micron technology, inc., Gaurav Sanjay Ramdasi of Austin TX (US) for micron technology, inc., Greg Alan Becker of Austin TX (US) for micron technology, inc., Nabeel Meeramohideen Mohamed of Round Rock TX (US) for micron technology, inc., Steven Andrew Moyer of Round Rock TX (US) for micron technology, inc., Tristan Antonio Partin of Austin TX (US) for micron technology, inc.
IPC Code(s): H04L45/48, G06F16/22, H04L12/40
Abstract: methods, systems, and devices for techniques to balance log structured merge trees are described. a computing system may rebalance a tree structure having an ordered set of leaf nodes by splitting or joining leaf nodes of the tree structure. to split a leaf node, the computing system may select a key to evenly partition key and value data stored in the leaf. the computing system may place each key block of the leaf node having keys less than or equal to the selected key in a first new leaf node, and may place each key block of the leaf node having keys greater than the selected key in a second new leaf node. to join leaf nodes of the tree structure, the computing system may place each key block and each value block of the leaf node and the adjacent leaf node in a new leaf node.
Inventor(s): Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc., Ling Pan of Singapore (SG) for micron technology, inc.
IPC Code(s): H05K3/34, H05K1/02
Abstract: substrates having stress-releasing features, and associated systems and methods are disclosed herein. in some embodiments, the substrate includes a core layer, a metallization layer formed on an outer surface of the core layer, and a solder mask formed over the metallization layer and the outer surface. the metallization layer can include at least one bond pad and the solder mask can include a first opening exposing the bond pad. the first opening can be surrounded by a bonding region of the solder mask that thermally interfaces with the bond pad and/or any conductive structure bonded thereon. the solder mask can also include one or more second openings adjacent the first opening. each of the second openings provides space for the solder mask to expand into to release stress due to thermal expansions of the bond pad, the solder mask, and/or the conductive structure during manufacturing and/or operation.
20240057317.RECESSED CHANNEL FIN INTEGRATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Sangmin Hwang of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/108
Abstract: a variety of applications can include apparatus having a recessed channel finfet. the recessed channel finfet can include one or more fin structures between the source region and the drain region, where the one or more fin structures are recessed from a top level of the source region and from a top level of the drain region. the recessed channel finfet can include a gate recessed from the top level of a source region and a drain region, where the gate can be separated from tip regions of the fin structures by a gate dielectric defining a channel between the source region and the drain region. recessed channel finfets can be structured in a periphery to an array of a memory device and can be fabricated in a process merged with forming access lines to the array.
Inventor(s): Umberto Maria Meotto of Dietlikon (CH) for micron technology, inc., Anna Maria Conti of Milano (IT) for micron technology, inc., Paolo Tessariol of Arcore (IT) for micron technology, inc.
IPC Code(s): H01L27/11524, H01L27/11582, H01L27/11551
Abstract: a microelectronic device includes a stack structure including tiers each including insulative material and conductive material vertically adjacent the insulative material. the stack structure divided into at least two blocks separated from one another. the microelectronic device further includes at least one slot structure horizontally interposed between the at least two blocks of the stack structure. the at least one slot structure including additional insulative material and at least one contact structure extending through the additional insulative material to source tier underlying the stack structure.
Inventor(s): Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/40, H01L23/00, H01L23/532, H01L23/522, H10B41/27, H10B41/35, H10B41/41, H10B43/27, H10B43/35
Abstract: a method of forming a microelectronic device comprises forming a microelectronic device structure. the microelectronic device structure comprises a semiconductive base structure, and a memory array region vertically overlying the semiconductive base structure and comprising memory cells. the microelectronic device structure is attached to a base structure. a portion of the semiconductive base structure is removed after attaching the microelectronic device structure to a base structure. a control logic region is formed vertically over a remaining portion of the semiconductive base structure. the control logic region comprises control logic devices in electrical communication with the memory cells of the memory array region. microelectronic devices, memory devices, electronic systems, and additional methods are also described.
Inventor(s): Lorenzo Fratin of Buccinasco (IT) for micron technology, inc., Enrico Varesi of Milano (IT) for micron technology, inc., Paolo Fantini of Vimercate (IT) for micron technology, inc., Thomas M. Graettinger of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/24, H01L45/00
Abstract: methods, systems, and devices for pillar and word line plate architecture for a memory array are described to support a memory array that may include a word line plate at each vertical level of the memory array, where the word line plate may be coupled with each memory cell of a word line tile at the respective level. the memory array includes multiple pillars, where each pillar includes two or more electrodes that run the vertical length of the pillar and which are separated by an insulating dielectric material. each electrode of the pillar is coupled with a corresponding set of memory cells, with each memory cell located at a different level of the array. an electrode of the pillar mis addressed, along with a word line plate of the memory array, to access a memory cell associated with the electrode and word line plate.
Inventor(s): Innocenzo Tortorelli of Cernusco Sui Naviglio (IT) for micron technology, inc., Matteo Impalà of Milano (IT) for micron technology, inc., Cécile Colette Solange Nail of Meylan (FR) for micron technology, inc.
IPC Code(s): H01L45/00, G11C13/00
Abstract: methods, systems, and devices for random number generation based on threshold voltage randomness are described. for example, a memory device may apply a voltage to a chalcogenide element and increase the applied voltage at least until the applied voltage satisfies a threshold voltage associated with the chalcogenide element. the memory device may detect the state of an oscillating signal at a time at which the applied voltage satisfies the threshold voltage, and the memory device may output a logic value corresponding to the state of the oscillating signal. the threshold voltage of the chalcogenide element may vary in a statistically random manner across voltage applications, and hence the state of the oscillating signal at the time an applied voltage reaches the threshold voltage may likewise vary in a statistically random manner, and thus the corresponding logic value that is output may be a random value suitable for random number generation.
Micron Technology, Inc. patent applications on February 15th, 2024
- Micron Technology, Inc.
- G06F1/30
- G06F11/14
- Micron technology, inc.
- G06F3/06
- G06F12/02
- G06F11/00
- G06F11/10
- G06F11/07
- G06F21/60
- G06F21/64
- G11C29/08
- H03M13/11
- H03M13/00
- G06F15/82
- G06F9/4401
- G06F21/57
- G08G1/0967
- G08G1/0969
- G01W1/14
- G01W1/10
- G08G1/0968
- G09G5/08
- G11C16/10
- G11C11/408
- G11C11/4091
- G11C11/4096
- G11C11/4076
- G11C7/24
- G11C16/08
- G11C16/34
- G11C16/32
- G11C29/52
- G11C16/12
- G11C16/26
- G11C13/00
- G11C11/22
- G11C16/30
- G11C5/06
- G11C16/24
- H01G7/06
- H01L23/48
- H01L23/00
- H01L21/768
- H01L23/528
- H01L27/11565
- H01L27/1157
- H01L27/11582
- H01L23/532
- H01L23/552
- H01L25/065
- H01L21/56
- H01L23/538
- H01L23/495
- H01L23/492
- H01L23/66
- H01L23/498
- H01L25/00
- H01L29/78
- H01L27/108
- H01L29/66
- H01L29/08
- H01L21/8234
- H01L27/088
- H04L45/48
- G06F16/22
- H04L12/40
- H05K3/34
- H05K1/02
- H01L27/11524
- H01L27/11551
- H10B43/40
- H01L23/522
- H10B41/27
- H10B41/35
- H10B41/41
- H10B43/27
- H10B43/35
- H01L27/24
- H01L45/00
- G06F3/0679
- G06F3/0659
