Micron Technology, Inc. patent applications on February 13th, 2025
Patent Applications by Micron Technology, Inc. on February 13th, 2025
Micron Technology, Inc.: 31 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (8), H01L23/00 (4), G06F12/02 (3), H01L21/78 (2), H01L23/31 (2) G06F3/0659 (4), G06F1/20 (1), G11C7/1096 (1), H01L29/7835 (1), H10B43/27 (1)
With keywords such as: memory, device, data, semiconductor, controller, portion, material, storage, configured, and methods in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20250053209. THERMAL ISLANDING HEATSINK_simplified_abstract_(micron technology, inc.)
Inventor(s): Joseph L. Turmes of Nampa ID (US) for micron technology, inc., Dave Holmstrom of Los Gatos CA (US) for micron technology, inc.
IPC Code(s): G06F1/20
CPC Code(s): G06F1/20
Abstract: a thermal islanding heatsink (a monolithic heat sink that includes a thermal insulating barrier is provided within a memory sub-system. the memory sub-system can be a solid state drive that can include a memory device, such as a volatile memory device and/or a non-volatile memory device, a power regulation area, and/or a controller. the thermal insulating barrier is deployed between the memory device and the power regulation area or between the memory device and the controller.
Inventor(s): Hyungseok Kim of Santa Clara CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Sampath K. Ratnam of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C7/04, G11C16/08, G11C16/26
CPC Code(s): G06F3/0619
Abstract: an example method of performing read operation comprises: receiving a read request with respect to a set of memory cells of a memory device; determining a value of a media endurance metric of the set of memory cells; determining a programing temperature associated with the set of memory cells; determining a current operating temperature of the memory device; determining a voltage adjustment value based on the value of the media endurance metric, the programming temperature, and the current operating temperature; adjusting, by the voltage adjustment value, a bitline voltage applied to a bitline associated with the set of memory cells; and performing, using the adjusted bitline voltage, a read operation with respect to the set of memory cells.
20250053326. ADAPTIVE MEMORY PARTITION CLOSURE TIME_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhongguang Xu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0644
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. the controller determines a memory reliability value associated with an individual portion of the set of memory components and selects a partition closing time for the individual portion of the set of memory components based on the memory reliability value. the controller defines a partition of the individual portion of the set of memory components based on the partition closing time and associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.
20250053327. REPAIR OPERATION TECHNIQUES_simplified_abstract_(micron technology, inc.)
Inventor(s): Alan J. Wilson of Boise ID (US) for micron technology, inc., Donald M. Morgan of Meridan ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/10
CPC Code(s): G06F3/0647
Abstract: methods, systems, and devices for repair operation techniques are described. a memory device may detect a failure of a read operation associated with a physical row address of a memory die. the memory device may store information associated with the physical row address before performing a media management operation and after detecting the failure. additionally or alternatively, the memory device may initiate a counter based on detecting the failure and may increment a value of the counter for each media management operation performed after detecting the failure. the memory device may send a command or other information to perform a repair operation for the physical row address. the memory device may determine the physical row address for the repair operation (e.g., despite media management operations) based on the stored information or the value of the counter, and may perform the repair operation on the physical row address.
Inventor(s): Sampath Ratnam of San Jose CA (US) for micron technology, inc., Daniel J. Hubbard of Boise ID (US) for micron technology, inc., Kevin R. Brandt of Boise ID (US) for micron technology, inc., David Ebsen of Minnetonka MN (US) for micron technology, inc., Brent Carl Byron of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0652
Abstract: aspects of the present disclosure configure a memory sub-system controller to receive information from a host about invalidated memory addresses. the controller receives, from a host, data identifying a set of storage locations associated with invalidated data stored in a set of memory components and, in response to receiving the data, performs staging activity for the invalidated data stored in the set of storage locations. the controller receives, from the host, a trim command for one or more storage locations in the set of storage locations and performs trim operations for the one or more storage locations for which the staging activity has already been performed.
20250053341. SIGNAL LOCKING_simplified_abstract_(micron technology, inc.)
Inventor(s): Gyan Prakash of Bangalore (IN) for micron technology, inc., Jose Rey C. De Luna of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a method includes receiving, by a memory device interface, a first operation command targeted for receipt by a memory device coupled to the memory device interface causing, responsive to receiving the first operation command, a chip enable signal to be asserted in a first state to filter commands received by the memory device interface that are targeted for subsequent receipt by the memory device, receiving, by the memory device interface, a second operation command targeted for receipt by a memory device coupled to the memory device interface, and causing, responsive to receiving the second operation command, the chip enable signal to be asserted in a second state to allow commands received by the memory device interface that are targeted for subsequent receipt by the memory device to be received by the memory device.
Inventor(s): Shanyuan Gao of Bellevue WA (US) for micron technology, inc., Sen Ma of Bellevue WA (US) for micron technology, inc., Moon Mark Hur of Kirkland WA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and apparatuses related to computational storage are described. for example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. a computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. the host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. the accelerator logic can perform the computational task using the stored data on the storage.
20250053343. ROW HAMMER TELEMETRY_simplified_abstract_(micron technology, inc.)
Inventor(s): Amitava Majumdar of Boise ID (US) for micron technology, inc., Anandhavel Nagendrakumar of Boise ID (US) for micron technology, inc., Mohammed Ebrahim Hargan of Boise ID (US) for micron technology, inc., Scott Garner of Boise ID (US) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio (IT) for micron technology, inc., Chia Wei Chang of Boise ID (US) for micron technology, inc., Ankush Lal of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C11/406
CPC Code(s): G06F3/0659
Abstract: an apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. the memory controller can include a row hammer detector. the memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. the memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. the memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.
Inventor(s): Eldhose Peter of Bengaluru (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a system includes a memory device configured with a zoned namespace having a plurality of zones, and a processing device, operatively coupled with the memory device, to perform operations comprising storing, in a first queue of the memory device, a first identifier of a first memory access operation to be performed at a first zone of the memory device, identifying one of a plurality of plane sets of the memory device that is associated with the first zone of the memory device, identifying a second queue of the memory device, wherein the second queue corresponds to the identified plane set, responsive to determining that a number of identifiers of memory access operations stored in the second queue satisfies a threshold criterion, retrieving, from the second queue, a second identifier of a second memory access operation to be performed at a second zone of the memory device, storing the second identifier of the second memory access operation in a third queue of the memory device, and performing the second memory access operation at the second zone associated with a second plane set of the memory device.
20250053498. SECURELY MODIFYING ACCESS TO A DEBUG PORT_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): G06F11/36
CPC Code(s): G06F11/3656
Abstract: in some aspects, the techniques described herein relate to a device including: a debug port; a trusted execution environment (tee), the tee storing a public key; and a controller, the controller configured to: receive a command to access the debug port, the command including a signature generated using a private key corresponding to the public key; provide the command to the tee, wherein the tee validates the command by validating the signature using the public key to obtain a validation result; and modify access to the debug port based on the validation result.
Inventor(s): Emanuele CONFALONIERI of Segrate (IT) for micron technology, inc., Marco SFORZIN of Cernusco sul Naviglio (IT) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0223
Abstract: provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks including m (m>1) memory dice, the m memory dice stores stripes of data, and each stripe spanning over the m memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether the memory dice required to store the compressed data in each stripe is n memory dice or less; where n is an integer less than m; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is n memory dice or less.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: the disclosure configures a memory sub-system controller to perform redundant array of independent disks (raid) stripe deletion based on physical region size. the controller stores a set of data across a plurality of memory components, a first of the plurality of components being configured to store data in a first set of regions, a second of the plurality of components being configured to store data in a second set of regions. the controller generates a plurality of error correction parity information stripes for multiple collections of the set of data and computes a quantity of the plurality of error correction parity information stripes to delete based on sizes of each region in the first and second sets of regions. the controller deletes one or more of the plurality of error correction parity information stripes based on the computed quantity.
20250053512. BANK MAPPING FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Robert M. Walker of Raleigh NC (US) for micron technology, inc.
IPC Code(s): G06F12/06
CPC Code(s): G06F12/063
Abstract: mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. updated bank bits can be generated by removing the bank bit from the plurality of bank bits. the plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.
Inventor(s): Vanaja Urrinkala of Hyderabad (IN) for micron technology, inc., Niraimathi N S of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F12/0862
CPC Code(s): G06F12/0862
Abstract: methods, systems, and devices supporting techniques for pre-fetching information using pattern detection are described. some memory systems may support pre-fetching information, such as logical-to-physical (l2p) mapping tables, data, or both, if a sequential pattern of read commands is detected. in some examples, the memory system may store a list of logical addresses indicated by received read commands and may determine whether the list corresponds to a sequential pattern independent of intervening write-alike commands. the list may store previous logical addresses for read commands, allowing the memory system to determine whether subsequent read commands form a sequential pattern. additionally or alternatively, the memory system may track a ratio of hibernate commands to other commands (e.g., sequential read commands) and may refrain from pre-fetching l2p mapping tables for a detected sequence if the tracked ratio satisfies (e.g., exceeds) a threshold ratio.
20250053525. INPUT/OUTPUT EXPANDER REGISTER ADDRESSING_simplified_abstract_(micron technology, inc.)
Inventor(s): Gyan Prakash of Bangalore (IN) for micron technology, inc., Jose Rey C. De Luna of Boise ID (US) for micron technology, inc., Srinivasa Aditya Regulagadda of Vijayawada (IN) for micron technology, inc.
IPC Code(s): G06F13/20
CPC Code(s): G06F13/20
Abstract: a method includes receiving, via a decoder coupled to a feature register resident on a memory device interface that comprises a first feature register portion and a second feature portion, a bit string comprising at least one bit indicative of selection between the first feature register portion and the second feature register portion, and responsive to the at least one bit being indicative of selecting the first feature register portion, writing the bit string to at least one memory die among a plurality of memory dice addressed by the first feature register portion, or responsive to the at least one bit being indicative of selecting the second feature register portion, writing the bit string to at least one memory die among a plurality of memory dice addressed by the second feature register portion.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F13/42, G06F9/30, G06F9/38, G06F13/38, G06N3/08, G06V10/94, H04N19/43, H04N19/70
CPC Code(s): G06F13/4282
Abstract: systems, devices, and methods related to a deep learning accelerator and memory are described. for example, a data storage device may be configured to execute instructions with matrix operands and configured with: an interface to receive a video stream; and random access memory to buffer a portion of the video stream as an input to an artificial neural network and to store instructions executable by the deep learning accelerator and matrices of the artificial neural network. the deep learning accelerator can execute the instructions to generate an output of the artificial neural network, including analytics of the buffer portion. a video encoder in the data storage device may use the analytics to compress the portion of the video stream for storing in the device.
20250053630. DISPLAY VISIBILITY BLOCK_simplified_abstract_(micron technology, inc.)
Inventor(s): Bhumika Chhabra of Boise ID (US) for micron technology, inc., Carla L. Christensen of Boise ID (US) for micron technology, inc., Radhika Viswanathan of Boise ID (US) for micron technology, inc., Zahra Hosseinimakarem of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F21/32, G06F21/60, G06V40/12, G06V40/16, G06V40/18, G09G3/3208
CPC Code(s): G06F21/32
Abstract: methods, apparatuses, and non-transitory machine-readable media for displaying information and/or images on a display of a computing device based on received data. apparatuses can include a display screen, a memory resource, a recognition sensor, and a controller. an example controller can receive data and activate information and/or images on a display screen based in part on the received data. in another example, a method can include storing recognition data in a memory resource, receiving primary recognition data, comparing the primary recognition data to the stored recognition data, and activating the display screen for a viewing angle responsive to authentication of the primary recognition data through the comparison of the primary recognition data and the stored recognition data.
20250054391. DEFINING A PARKING AREA_simplified_abstract_(micron technology, inc.)
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc., Febin Sunny of Folsom CA (US) for micron technology, inc.
IPC Code(s): G08G1/14, G01C21/36, G08G1/16
CPC Code(s): G08G1/146
Abstract: apparatuses and methods related to defining a parking area are described. in an example, an apparatus can include a memory and a processor coupled to the memory, wherein the processor is configured to receive vehicle data, receive sensor data of a parking lot, and define a parking area within the parking lot for a vehicle to park based on the received vehicle data and the received sensor data.
Inventor(s): Cheng Cheng Ang of Singapore (SG) for micron technology, inc., Chun Lei Kong of Singapore (SG) for micron technology, inc., Ting Luo of Santa Clara CA (US) for micron technology, inc., Aik Boon Edmund Yap of Singapore (SG) for micron technology, inc.
IPC Code(s): G11C7/10, G06F12/02, G11C8/08, G11C29/12
CPC Code(s): G11C7/1096
Abstract: methods, systems, and devices for skipping pages for weak wordlines of a memory device during pre-programming are described. a memory device may be configured to operate in a first mode involving skipping one or more pages (e.g., a lower page (lp)) associated with a set of wordlines. in some examples, a testing system may determine the set of wordlines (e.g., weak wordlines) for which to skip pages according to performance degradation for the wordlines in response to applying a threshold temperature to a test memory device. in the first mode, the memory device may store (e.g., pre-program) data in a subset of pages distinct from the skipped pages. the memory device may switch to a second mode in response to a trigger condition. in the second mode, the memory device may use each page associated with the wordlines and may refrain from skipping the one or more pages.
Inventor(s): Tong Liu of Folsom CA (US) for micron technology, inc., Daniele Vimercati of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G11C11/22
CPC Code(s): G11C11/2273
Abstract: systems and methods are related to a memory device including a plate line. the memory device also includes a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line. the memory device further includes a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers. the memory device also includes a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the digit lines from the respective memory cells. the sense amplifier includes a threshold voltage compensated latch that includes multiple p-channel transistors and is configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the multiple p-channel transistors.
20250054543. MEMORY CELL READ OPERATION TECHNIQUES_simplified_abstract_(micron technology, inc.)
Inventor(s): Riccardo Muzzetto of Arcore (MB) (IT) for micron technology, inc., Francesco Mastroianni of Melzo (MI) (IT) for micron technology, inc., Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc., Nevil N. Gajera of Meridian ID (US) for micron technology, inc.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/004
Abstract: methods, systems, and devices for memory cell read operation techniques are described. a memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. for example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. in some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. as part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.
Inventor(s): Nagendra Prasad Ganesh Rao of Folsom CA (US) for micron technology, inc., Paing Htet of Union City CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/26
CPC Code(s): G11C16/102
Abstract: apparatuses and methods for programming partially programmed blocks with padding are provided. one example apparatus can include a controller configured to program a first number of word lines in a block of word lines in the array of memory cells, wherein the first number of word lines is less that a total number of word lines in the block, and program a second number of word lines of the array of memory cells, wherein the second number of word lines are programmed with padding and wherein the second number of word lines are different word lines that the first number of word lines and the total number of word lines in the block includes the first and second number of word lines.
20250054560. IMPRINT RECOVERY FOR MEMORY CELLS_simplified_abstract_(micron technology, inc.)
Inventor(s): Jonathan D. Harms of Meridian ID (US) for micron technology, inc., Jonathan J. Strand of Boise ID (US) for micron technology, inc., Sukneet Singh Basuta of Meridian ID (US) for micron technology, inc., Shashank Bangalore Lakshman of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/50, G11C11/22
CPC Code(s): G11C29/50004
Abstract: methods, systems, and devices for imprint recovery for memory cells are described. in some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. in some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
Inventor(s): Federico Pio of Brugherio (IT) for micron technology, inc.
IPC Code(s): H01L21/56, G06K19/06, H01L21/78, H01L23/00, H01L23/28
CPC Code(s): H01L21/561
Abstract: semiconductor device packages and associated methods are disclosed herein. in some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) a pattern positioned in a designated area of the first surface. the pattern includes multiple bit areas. each of the bit areas represents a first bit information or a second bit information. the pattern presents information for operating the semiconductor die. the pattern is configured to be read by a pattern scanner.
Inventor(s): Bong Woo Choi of Singapore (SG) for micron technology, inc., Ankur Harish Shah of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/60, H01L23/00
CPC Code(s): H01L23/60
Abstract: a semiconductor device assembly that includes an inductive coating is disclosed. the semiconductor device assembly includes a semiconductor substrate having circuitry disposed at a first side. a layer of inductive material is disposed at a second side of the semiconductor substrate opposite the first side. a die attach film (daf) is disposed at the second side of the semiconductor substrate at least partially over the layer of inductive material. the die attach film can be used to attach the semiconductor device assembly to an additional substrate. the layer of inductive material can be disposed at least partially between the semiconductor substrate and the die attach film, which can decrease the damage caused by electrostatic discharge (esd) events.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc., Bret K. Street of Meridian ID (US) for micron technology, inc., Akshay N. Singh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/31, H01L25/00, H01L25/065, H10B80/00
CPC Code(s): H01L24/32
Abstract: a semiconductor device, including a lower semiconductor die, one or more upper semiconductor dies disposed over the lower semiconductor die, a non-conductive fillet material disposed between adjacent semiconductor dies of the lower semiconductor die and the one or more upper semiconductor dies, the non-conductive fillet material having edge regions that squeeze out from space between adjacent semiconductor dies, a dielectric layer disposed on a backside of the lower semiconductor die and under the one or more upper semiconductor dies, a buffer layer disposed above the dielectric layer and in contact to at least one edge region of the non-conductive fillet material, and an encapsulant material disposed on sidewalls and top surface of the semiconductor device, the encapsulant material encapsulating the lower semiconductor die and the one or more upper semiconductor dies.
Inventor(s): Febin Sunny of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc., Saideep Tiku of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): H01S5/183
CPC Code(s): H01S5/18397
Abstract: a photonic probing system, including a communication bus for communicating a main photonic waveguide signal therethrough, a splitter that splits off a portion of the main photonic waveguide signal to create an off-shoot portion photonic signal, a photodetector that converts the off-shoot portion photonic signal to a converted electrical current, a current threshold detector that compares the converted electrical current to a threshold value to determine if the converted electrical current exceeds the threshold value, if the converted electrical current does not exceed the threshold value, then the current threshold detector generates a laser generating signal directed toward a vcsel, and wherein the laser generating signal drives the vcsel to generate a laser signal directed toward a central control system.
20250055497. TRANSCEIVER CAPACITANCE REDUCTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Robert Wimmer of Hastings MN (US) for micron technology, inc., Jeremy Kuehlwein of Woodbury MN (US) for micron technology, inc.
IPC Code(s): H04B1/40, H01L27/02
CPC Code(s): H04B1/40
Abstract: systems, methods and apparatus are provided for transceiver capacitance reduction. an example apparatus can comprise a first signal driver of a transceiver, a second signal driver of the transceiver, and an input/output (i/o) pad coupled to the first and second signal drivers. the apparatus can further comprise a resistor divider of a plurality of resistor dividers coupled to the first signal driver. the resistor divider, when enabled, can reduce capacitance of the first signal driver and maintain the reduced capacitance while the second signal driver is actively driving a signal.
Inventor(s): Shuangqiang Luo of Boise ID (US) for micron technology, inc., Dong Wang of Singapore (SG) for micron technology, inc., Rui Zhang of Boise ID (US) for micron technology, inc., Da Xing of Singapore (SG) for micron technology, inc., Xiao Li of Boise ID (US) for micron technology, inc., Pei Qiong Cheung of Singapore (SG) for micron technology, inc., Xiao Zeng of Singapore (SG) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/40, H10B43/40
CPC Code(s): H10B43/27
Abstract: some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. the conductive structures include a first stack over a metal-containing region. a semiconductor material is within the first stack. a second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. cell-material-pillars are within the memory array region. the cell-material-pillars include channel material. the semiconductor material directly contacts the channel material. conductive post structures are within the other region. some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. others of the conductive post structures are live posts electrically coupled with cmos circuitry. some embodiments include methods of forming assemblies.
Inventor(s): Si-Woo LEE of Boise ID (US) for micron technology, inc., Yuichi YOKOYAMA of Boise ID (US) for micron technology, inc., Scott E. SILLS of Boise ID (US) for micron technology, inc., Gautham MUTHUSAMY of Boise ID (US) for micron technology, inc., David HWANG of Boise ID (US) for micron technology, inc., Yoshitaka NAKAMURA of Boise ID (US) for micron technology, inc., Pavani Vamsi Krishna NITTALA of Meridian ID (US) for micron technology, inc., Yuanzhi MA of Meridian ID (US) for micron technology, inc., Glen H. WALTERS of Woodlawn MD (US) for micron technology, inc., Haitao LIU of Boise ID (US) for micron technology, inc., Kamal M. KARDA of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/78, H01L21/223, H01L21/8234, H01L29/06, H01L29/423, H01L29/775, H01L29/786, H10B12/00
CPC Code(s): H01L29/7835
Abstract: some implementations herein provide for a memory device and methods of formation. the memory device includes a plurality of storage cells arranged vertically and a plurality of corresponding gate all around transistors. methods of forming the memory device include using a single trench to remove a liner material and form recesses that define cell contact lightly-doped drain regions of the gate all around transistors. using the single trench to remove the liner material and form the recesses that define the cell contact lightly-doped drain region widths causes the cell contact lightly-doped drain regions to be formed having substantially similar widths.
Inventor(s): Vladimir Odnoblyudov of Eagle ID (US) for micron technology, inc., Scott D. Schellhammer of Meridian ID (US) for micron technology, inc., Jeremy S. Frei of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L33/52, H01L21/56, H01L21/683, H01L21/78, H01L23/00, H01L23/31, H01L33/00, H01L33/20, H01L33/44, H01L33/62, H01S5/02, H10K50/84, H10K50/844, H10K71/00
CPC Code(s): H01L33/52
Abstract: etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. a method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. in particular embodiments, the trenches extend into the carrier substrate. in further particular embodiments, the dies are at least partially encapsulated in a dielectric material.
Micron Technology, Inc. patent applications on February 13th, 2025
- Micron Technology, Inc.
- G06F1/20
- CPC G06F1/20
- Micron technology, inc.
- G06F3/06
- G11C7/04
- G11C16/08
- G11C16/26
- CPC G06F3/0619
- CPC G06F3/0644
- G06F12/10
- CPC G06F3/0647
- CPC G06F3/0652
- CPC G06F3/0659
- G11C11/406
- G06F11/36
- CPC G06F11/3656
- G06F12/02
- CPC G06F12/0223
- CPC G06F12/0246
- G06F12/06
- CPC G06F12/063
- G06F12/0862
- CPC G06F12/0862
- G06F13/20
- CPC G06F13/20
- G06F13/42
- G06F9/30
- G06F9/38
- G06F13/38
- G06N3/08
- G06V10/94
- H04N19/43
- H04N19/70
- CPC G06F13/4282
- G06F21/32
- G06F21/60
- G06V40/12
- G06V40/16
- G06V40/18
- G09G3/3208
- CPC G06F21/32
- G08G1/14
- G01C21/36
- G08G1/16
- CPC G08G1/146
- G11C7/10
- G11C8/08
- G11C29/12
- CPC G11C7/1096
- G11C11/22
- CPC G11C11/2273
- G11C13/00
- CPC G11C13/004
- G11C16/10
- CPC G11C16/102
- G11C29/50
- CPC G11C29/50004
- H01L21/56
- G06K19/06
- H01L21/78
- H01L23/00
- H01L23/28
- CPC H01L21/561
- H01L23/60
- CPC H01L23/60
- H01L23/31
- H01L25/00
- H01L25/065
- H10B80/00
- CPC H01L24/32
- H01S5/183
- CPC H01S5/18397
- H04B1/40
- H01L27/02
- CPC H04B1/40
- H10B43/27
- H10B41/27
- H10B41/40
- H10B43/40
- CPC H10B43/27
- H01L29/78
- H01L21/223
- H01L21/8234
- H01L29/06
- H01L29/423
- H01L29/775
- H01L29/786
- H10B12/00
- CPC H01L29/7835
- H01L33/52
- H01L21/683
- H01L33/00
- H01L33/20
- H01L33/44
- H01L33/62
- H01S5/02
- H10K50/84
- H10K50/844
- H10K71/00
- CPC H01L33/52
