Micron Technology, Inc. patent applications on December 26th, 2024
Patent Applications by Micron Technology, Inc. on December 26th, 2024
Micron Technology, Inc.: 38 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (8), G11C16/08 (6), G11C16/10 (4), G11C16/26 (4), G11C16/34 (4) G11C16/08 (2), G11C16/102 (2), H01L24/14 (2), C23C16/45527 (1), G11C16/3459 (1)
With keywords such as: memory, device, data, semiconductor, access, signal, coupled, cells, include, and threshold in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Jean-Sebastien Materne Lehn of Boise ID (US) for micron technology, inc., Francois H. Fabreguette of Boise ID (US) for micron technology, inc., Timothy A. Quick of Boise ID (US) for micron technology, inc.
IPC Code(s): C23C16/455, C23C16/24
CPC Code(s): C23C16/45527
Abstract: methods, systems, and devices for methods for depositing silicon films by atomic layer deposition are described. for instance, a device may expose a base material (e.g., multiple stacks of materials) to a first precursor to form a silicon compound on the base material, the first precursor including a silicon amidinate. the device may react a second precursor with the silicon compound and may form a layer of silicon on the base material based on exposing the base material to the first precursor and reacting the second precursor with the silicon compound.
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0617
Abstract: apparatuses and methods aggressor queue mitigation based threshold. a memory device detects aggressor rows by changing a count value associated with the row when it is accessed and comparing the count value to a mitigation threshold. identified aggressor rows are stored in an aggressor queue. the value of the mitigation threshold is set based on a number of addresses which are stored in the aggressor queue. for example the threshold may increase as the number of addresses in the queue increases.
Inventor(s): Nicola Ciocchini of Boise ID (US) for micron technology, inc., Thomas Lentz of Boise ID (US) for micron technology, inc., Ugo Russo of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C16/04, G11C16/08, G11C16/26
CPC Code(s): G06F3/0619
Abstract: a system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a set of memory cells of the memory device; identifying a wordline group coupled to the set of memory cells of the memory device; identifying a threshold voltage offset bin associated with the set of memory cells; determining a current temperature associated with the set of memory cells; determining, based on the threshold voltage offset bin and the current temperature, a read mask identifier associated with the set of memory cells; determining, based on the read mask identifier and the wordline group, a set of threshold voltage offsets associated with the set of memory cells; and performing the read operation using the set of threshold voltage offsets.
20240427507. POWER INTEGRITY MONITORING_simplified_abstract_(micron technology, inc.)
Inventor(s): Sriteja Yamparala of Boise ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc., Marco Domenico Tiburzi of Avezzano (IT) for micron technology, inc., Walter Di Francesco of Avezzano (IT) for micron technology, inc., Chiara Cerafogli of Boise ID (US) for micron technology, inc., Tawalin Opastrakoon of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F1/08, G06F1/28
CPC Code(s): G06F3/0625
Abstract: various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. a method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.
20240427511. VIRTUAL BINNING IN A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc., Brian Toronyi of Boulder CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0638
Abstract: a first memory resource is configured to store a data structure. the first memory resource is coupled to a second memory resource that is configured to store a plurality of data structures. a processing device is coupled to the first memory resource, the second memory resource, and a third memory resource. the processing device writes data entries to the data structure within the first memory resource, determine that the data structure within the first memory resource includes a threshold quantity of data entries, and write the contents of the data structure within the first memory resource to a data structure within the second memory resource. the processing resource is further configured to move the contents of the contents of the data structure in the second memory resource to the third memory resource by readdressing the entries written within the second memory resource to virtual addresses associated with the third memory resource.
20240427518. MEMORY SUB-SYSTEM SLOW PROGRAM DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Chia Wei Chang of Gukeng Township (TW) for micron technology, inc., Chia Yu Kuo of Hukou Town (TW) for micron technology, inc., Tzu Ting Tseng of Hsinchu City 300 (TW) for micron technology, inc., Pinhsueh Lai of New Taipei City 248 (TW) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: an example apparatus can include a program component. the program component can program each of a plurality of planes during different time periods subsequent to performing a multi-plane programming on a non-volatile memory array. the program component can monitor a program pulse count for each of the respective plurality of planes per super block. the program component can, in response to the program pulse count for a respective block within one of the plurality of planes being above a threshold pulse count, determine that the respective block is a bad block.
Inventor(s): Nicola Del Gatto of Cassina de’ Pecchi (IT) for micron technology, inc., Emanuele Confalonieri of Segrate (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Patrick Estep of Rowlett TX (US) for micron technology, inc., Stephen S. Pawlowski of Beaverton OR (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0864
CPC Code(s): G06F3/0659
Abstract: a memory controller can include a front end portion configured to interface with a host, a central controller portion configured to manage data, a back end portion configured to interface with memory devices. the memory controller can include interface management circuitry coupled to a cache and a memory device. the memory controller can receive, by the interface management controller, a first signal indicative of data associated with a memory access request from a host. the memory controller can transmit a second signal indicative of the data to cache the data in a first location in the cache. the memory controller can transmit a third signal indicative of the data to cache the data in a second location in the cache.
Inventor(s): Jianping Tian of Shanghai (CN) for micron technology, inc., Da Hong of SanYang (CN) for micron technology, inc.
IPC Code(s): G06F11/07, G06F9/4401
CPC Code(s): G06F11/0787
Abstract: various embodiments described herein provide for bootloader failure analysis of a memory system using information regarding a failure of the bootloader, where the information is stored on the memory sub-system in response to detection of (e.g., stored at the time of) the failure. in particular, the stored information can comprise data that would be lost or otherwise inaccessible for subsequent diagnostic (e.g., debug) purposes, such as by a manufacturer of the memory sub-system. according to some embodiments, a memory sub-system is configured to save information regarding a failure of a bootloader, to one or more designated memory devices of the memory sub-system, such that diagnostic firmware (e.g., debug firmware) subsequently loaded and executed on the memory sub-system (e.g., by a manufacturer) can make use of the stored information to perform one or more diagnostic functions (e.g., debug functions) on the memory sub-system.
20240427660. Read Data Path_simplified_abstract_(micron technology, inc.)
Inventor(s): Nicola Del Gatto of Cassina de Pecchi (IT) for micron technology, inc., Emanuele Confalonieri of Segrate (IT) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: described apparatuses and methods relate to a read data path for a memory system. the memory system may include logic that receives data and associated metadata from a memory. the logic may perform a reliability check on the data using the associated metadata to determine if the data has an error. if the data is determined not to include an error, the data may be transmitted to a requestor. if the data is determined to include an error, however, a data recovery process may be initiated to recover the data. this may reduce a likelihood the memory system returns corrupted data to a requestor. the memory system may process a different read request at least partially in parallel with the data recovery process to increase throughput or reduce latency. in some cases, the data recovery process may involve one or more techniques related to redundant array of disks (raid) technology.
Inventor(s): Steven R. NARUM of Meridian ID (US) for micron technology, inc., Huapeng GUAN of Redwood City CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F1/3225
CPC Code(s): G06F12/0246
Abstract: a memory device may detect a memory operation that updates a level two volatile (l2v) entry stored in an l2v table. each l2v entry in the l2v table may indicate a mapping between a respective logical block address (lba) and a respective user data physical address in non-volatile memory. the memory operation may cause a mapping between an lba indicated in the l2v entry and a user data physical address indicated in the l2v entry to become invalid. the memory device may store, in a volatile memory log, an indication of an lba region that includes the lba. the memory device may detect that an l2 transfer condition, associated with the volatile memory log, is satisfied. the memory device may copy, from volatile memory to non-volatile memory, every l2v entry that indicates an lba included in the lba region based on detecting that the l2 transfer condition is satisfied.
Inventor(s): Mattia Robustelli of Milano (IT) for micron technology, inc., Innocenzo Tortorelli of Naviglio (IT) for micron technology, inc., Alessandro Novati of Verano Brianza (IT) for micron technology, inc., Nicola Colella of Capodrise (IT) for micron technology, inc., Antonino Pollio of Vico Equense (IT) for micron technology, inc.
IPC Code(s): G06F12/02, G06F13/16
CPC Code(s): G06F12/0292
Abstract: the subject application related to referencing memory using portions of a split logical block address. a method includes receiving a memory operation including a logical block address (lba). the method also includes splitting the lba into a first portion and a second portion. the method further includes determining a physical block of a memory using a logical-to-physical (l2p) table to map the first portion of the lba to the physical block. the physical block includes a plurality of physical block addresses (pbas). the method further includes combining the second portion of the lba and the physical block to reference a physical block address (pba) of the physical block. the method further includes performing the memory operation at the pba of the physical block.
20240427701. TELEMETRY-CAPABLE MEMORY SUB-SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F12/0815
CPC Code(s): G06F12/0815
Abstract: an access counter associated with a segment of a memory device is maintained. the segment comprises a plurality of lines. a first count of the plurality of lines is identified. a subset of the plurality of lines of the segment is monitored. a second count of the subset of the plurality of lines is identified. an access notification for a first line of the subset of the plurality of lines is received. a first value of the access counter is changed by a second value. the second value is weighted based on the first count and the second count. based on the first value of the access counter, a memory management scheme is implemented.
Inventor(s): Samuel E. Bradshaw of Sacramento CA (US) for micron technology, inc., Shivam Swami of Folsom CA (US) for micron technology, inc., Sean Stephen Eilert of Penryn CA (US) for micron technology, inc., Justin M. Eno of El Dorado Hills CA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc.
IPC Code(s): G06F13/10, G06F3/06, G06F12/0802, G06F13/12
CPC Code(s): G06F13/102
Abstract: a memory chip having a first set of pins configured to allow the memory chip to be coupled to a first microchip or device via first wiring. the memory chip also having a second set of pins configured to allow the memory chip to be coupled to a second microchip or device via second wiring that is separate from the first wiring. the memory chip also having a data mover configured to facilitate access to the second microchip or device, via the second set of pins, to read data from the second microchip or device and write data to the second microchip or device. also, a system having the memory chip, the first microchip or device, and the second microchip or device.
20240427974. POWER EMULATION AND ESTIMATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc.
IPC Code(s): G06F30/3308, G06F30/333, G06F119/06
CPC Code(s): G06F30/3308
Abstract: an example method for power emulation and estimation includes estimating a functional power consumption value associated with a memory system by determining: a scan-based power estimation, scan-based power measurement, a calibration factor from correlating the scan-based power estimation to the scan-based power measurement and a correlated functional power using the calibration factor. the calibration factor can be applied to a functional power estimation in order to achieve better accuracy.
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Luca Barletta of Gallarate (IT) for micron technology, inc., Marco Pietro Ferrari of Milano (IT) for micron technology, inc., Antonino Favano of Brolo (IT) for micron technology, inc.
IPC Code(s): G11C7/10, G11C11/56
CPC Code(s): G11C7/1063
Abstract: systems, methods, and apparatuses are provided for drift compensation for codewords in memory. a memory device comprises memory cells and circuitry configured to sense a codeword stored in the memory cells. the circuitry is further configured to determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on a summation of a threshold voltage value of each of the memory cells, a mean of the threshold voltage values of the memory cells, and a value proportional to the mean of the threshold voltage values of the memory cells. the circuitry is further configured to determine which cell metric of each of the memory cells has a lowest value, input that cell metric into a pearson detector, and determine the originally programmed data of the codeword using the pearson detector.
Inventor(s): Angelo VISCONTI of Appiano Gentile (IT) for micron technology, inc., Giorgio SERVALLI of Fara Gera d’Adda (IT) for micron technology, inc.
IPC Code(s): G11C11/22
CPC Code(s): G11C11/2255
Abstract: at least one portion of a memory array may be arranged to provide high density non-volatile random access memory (high density non-volatile ram) while at least one other portion of the memory array may be arranged to provide dynamic random access memory (dram)-like memory. in some examples, the memory array may be arranged by programming one or more configuration devices. in some examples, the configuration device may include one or more switches to couple one or more memory cells to a sense amplifier. in some examples, the configuration device may include fuses and/or antifuses to couple one or more memory cells to a sense amplifier. in some examples, the portions of the memory array may be reconfigurable from one arrangement to another arrangement.
Inventor(s): YUKIMI MORIMOTO of Sagamihara (JP) for micron technology, inc., YOSHIO MIZUKANE of Sagamihara (JP) for micron technology, inc., HIDEKAZU NOGUCHI of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C11/406, G11C7/22
CPC Code(s): G11C11/40615
Abstract: apparatuses, systems, and methods for partial array self refresh masking. a memory bank may be divided into a number of segments, each of which is associated with partial-array self-refresh (pasr) logic which provides a mask signal. the mask signal may be deactivated responsive to an access operation performed on the associated segment. while the mask signal is deactivated, self-refresh operations are performed on the segment. a period of time after deactivating the mask signal, the mask signal may be reactivated.
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Randall J. Rooney of Boise ID (US) for micron technology, inc., David R. Brown of Boise ID (US) for micron technology, inc., Michael A. Shore of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/4076
CPC Code(s): G11C11/40622
Abstract: apparatuses, systems, and methods for multiple types of alert along an alert bus. a memory device may detect multiple types of alert and use an alert signal along an alert bus to signal a controller of these alerts. different pulse widths of the alert signal may be used to indicate the type of alert. for example if the alert signal is at an active level between a first duration and a second duration, it may indicate a first type of alert, if the alert signal is active between a third duration and a fourth duration, it may indicate a second type of alert. if the alert signal remains active for longer than a threshold amount of time, it may indicate a third type of alert.
Inventor(s): BAOKANG WANG of Sagamihara (JP) for micron technology, inc., TAKUYA MIYAGI of Sagamihara (JP) for micron technology, inc.
IPC Code(s): G11C11/4076
CPC Code(s): G11C11/4076
Abstract: apparatuses, systems, and methods for data timing alignment with fast alignment mode. a stacked memory device includes an interface die and a number of core die. the interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. the delay codes are adjusted based on a measured phase difference along a replica path. in a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. if one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. this may allow for correction of systemic errors such as voltage drift.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4078, G11C11/406
CPC Code(s): G11C11/4078
Abstract: methods, apparatuses, and systems related to detecting and mitigating waterfall attacks are described. a memory device may include a waterfall attack mitigation circuit that is configured to detect, based on the ratio of read commands to write command received by the memory device, whether the memory device is the target of a waterfall attack. upon detecting that the memory device is the target of a waterfall attack, the waterfall attack mitigation circuit can initiate certain mitigation actions, such as adjusting a threshold used to perform row hammer-related refreshes.
Inventor(s): Aliasger Tayeb Zaidy of Seattle WA (US) for micron technology, inc., Patrick Alan Estep of Rowlett TX (US) for micron technology, inc., David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G11C11/54, G06F12/0862, G06F12/0897, G06N3/063, G06N3/08
CPC Code(s): G11C11/54
Abstract: systems, devices, and methods related to a deep learning accelerator and memory are described. for example, the accelerator can have processing units to perform at least matrix computations of an artificial neural network via execution of instructions. the processing units have a local memory store operands of the instructions. the accelerator can access a random access memory via a system buffer, or without going through the system buffer. a fetch instruction can request an item, available at a memory address in the random access memory, to be loaded into the local memory at a local address. the fetch instruction can include a hint for the caching of the item in the system buffer. during execution of the instruction, the hint can be used to determine whether to load the item through the system buffer or to bypass the system buffer in loading the item.
Inventor(s): Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Patrick R. Khayat of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G11C16/08, G06F3/06, G11C16/04, G11C16/10, G11C16/34
CPC Code(s): G11C16/08
Abstract: embodiments disclosed can include determining, for a wordline of the plurality of wordlines, a respective value of a sensitivity metric that reflects a sensitivity of a threshold voltage of a memory cell associated with the wordline to a change in a threshold voltage of an adjacent memory cell. embodiments can also include determining, for the wordline, that the respective value of the sensitivity metric satisfies a threshold criterion. embodiments can further include responsive to determining that the respective value of the sensitivity metric satisfies the threshold criterion, associating the wordline with a first wordline group, wherein the first wordline group comprises one or more wordlines, and wherein each wordline of the one or more wordlines is associated with a respective value of the sensitivity metric that satisfies the threshold criterion. embodiments can include performing, on a specified memory cell connected to the wordline associated with the first wordline group, a compensatory operation.
Inventor(s): Michael A. Smith of Boise ID (US) for micron technology, inc., Martin W. Popp of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/08, G11C16/04, H01L29/10, H01L29/78
CPC Code(s): G11C16/08
Abstract: a memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. the first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. for a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.
Inventor(s): Taehyun Kim of San Jose CA (US) for micron technology, inc., Brian Kwon of San Jose CA (US) for micron technology, inc., Dong Kyo Shim of Milpitas CA (US) for micron technology, inc., Kwang Ho Kim of Pleasanton CA (US) for micron technology, inc., Erwin E. Yu of San Jose CA (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/34
CPC Code(s): G11C16/102
Abstract: control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. during the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. during the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.
20240428863. BALANCING DATA IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08, G11C16/26
CPC Code(s): G11C16/102
Abstract: the present disclosure includes apparatuses, methods, and systems for balancing data in memory. an embodiment includes a memory having a group of memory cells, wherein each respective memory cell is programmable to one of three possible data states, and circuitry to balance data programmed to the group between the three possible data states by determining whether the data programmed to the group is balanced for any one of the three possible data states, and upon determining the data programmed to the group is not balanced for any one of the three possible data states apply a rotational mapping algorithm to the data programmed to the group until the data is balanced for any one of the three possible data states and apply a knuth algorithm to the data of the group programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.
Inventor(s): Hanping Chen of Campbell CA (US) for micron technology, inc., Zhongguang Xu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/08, G11C16/24
CPC Code(s): G11C16/26
Abstract: apparatuses and methods for determining performing read operations on a partially programmed block are provided. one example apparatus can include a controller configured to apply a read voltage to a first word line in the array of memory cells during a read operation on the first word line, and apply a bit line bias to a number of bit lines coupled to the first word line during the read operation on the first word line, wherein the bit line bias includes a bit line bias offset associated with performing the read operation on a partially programmed block.
Inventor(s): Manuel Mencarelli of München (DE) for micron technology, inc.
IPC Code(s): G11C16/34, H01L23/498
CPC Code(s): G11C16/3418
Abstract: methods, systems, and devices for probe pad disconnection for high-speed memory system interfaces are described. for example, a probe pad may be electrically connected with an operative signal path of a memory system interface via a conductor portion, and the conductor portion may be configured to deteriorate (e.g., melt, disconnect) after applying an electrical current through or a laser to the conductor portion (e.g., after performing evaluation operations via the probe pad). such a deterioration may electrically disconnect the probe pad from the signal path, thereby reducing an effective capacitance of the signal path. in some examples, cross-sectional dimensions of the conductor portion, or material properties of the conductor portion, or both may support the probe pad being electrically disconnected from the signal path as a result of applying a current or a laser to the conductor portion.
20240428872. CONTINUOUS MEMORY PROGRAMMING OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Violante Moschiano of Avezzano (IT) for micron technology, inc., Ali Mohammadzadeh of Mountain View CA (US) for micron technology, inc., Walter Di Francesco of Avezzano (IT) for micron technology, inc., Dheeraj Srinivasan of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C7/10, G11C16/10, G11C16/26
CPC Code(s): G11C16/3459
Abstract: described are systems and methods for implementing continuous memory programming operations. an example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of conductive lines; and a controller coupled to the memory array. the controller performs operations comprising: performing a memory programming operation with respect to a set of memory cells of the memory array, wherein the memory programming operation comprises a sequence of programming pulses applied to one or more conductive lines electrically coupled to the set of memory cells; responsive to receiving a command to perform a memory access operation, suspending the memory programming operation after performing a current programming pulse of the sequence of programming pulses, wherein the current programming pulse is performed at a first voltage level; initiating the memory access operation; and resuming the memory programming operation by performing a next programming pulse at a second voltage level that exceeds the first voltage level.
Inventor(s): Kevin J. Torek of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/308, H01L21/822, H01L21/84, H01L27/06, H01L27/088, H01L29/08, H01L29/10, H01L29/423, H01L29/66, H01L29/786, H10B12/00
CPC Code(s): H01L21/823885
Abstract: a method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. related methods of forming semiconductor structures and an array of memory cells are also disclosed.
Inventor(s): Ruei Ying Sheng of Taichung (TW) for micron technology, inc., Andrew M. Bayless of Boise ID (US) for micron technology, inc., Brandon P. Wirz of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/538, H01L21/48, H01L21/50, H01L21/768, H01L25/065
CPC Code(s): H01L23/5384
Abstract: semiconductor devices having electrical interconnections through vertically stacked semiconductor dies, and associated systems and methods, are disclosed herein. in some embodiments, a semiconductor assembly includes a die stack having a plurality of semiconductor dies. each semiconductor die can include surfaces having an insulating material, a recess formed in at least one surface, and a conductive pad within the recess. the semiconductor dies can be directly coupled to each other via the insulating material. the semiconductor assembly can further include an interconnect structure electrically coupled to each of the semiconductor dies. the interconnect structure can include a monolithic via extending continuously through each of the semiconductor dies in the die stack. the interconnect structure can also include a plurality of protrusions extending from the monolithic via. each protrusion can be positioned within the recess of a respective semiconductor die and can be electrically coupled to the conductive pad within the recess.
Inventor(s): Aibin Yu of Singapore (SG) for micron technology, inc., Wei Zhou of Boise ID (US) for micron technology, inc., Zhaohui Ma of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/768, H01L23/48, H01L25/065
CPC Code(s): H01L24/14
Abstract: a bond pad with micro-protrusions for direct metallic bonding. in one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (tsv) extending through the semiconductor substrate, and a copper pad electrically connected to the tsv and having a coupling side. the semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. in another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first tsv and a first copper pad electrically coupled to the first tsv, wherein the first copper pad has a first coupling side. the bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. a plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.
Inventor(s): Brandon P. Wirz of Boise ID (US) for micron technology, inc., Benjamin L. McClain of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065, H01L25/16, H01L25/18
CPC Code(s): H01L24/14
Abstract: a semiconductor device assembly is provided. the assembly includes a first package element and a second package element disposed over the first package element. the assembly further includes a plurality of die support structures between the first and second package elements, wherein each of the plurality of die support structures has a first height, a lower portion surface-mounted to the first package element and an upper portion in contact with the second package element. the assembly further includes a plurality of interconnects between the first and second package elements, wherein each of the plurality of interconnects includes a conductive pillar having a second height, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad. the first height is about equal to a sum of the solder joint thickness and the second height.
20240429904. ASYNCRONOUS RESETTING INTEGRATED CIRCUITS_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc., Leonid Minz of Beer Sheva (IL) for micron technology, inc., Yoav Weinberg of Thornhill (CA) for micron technology, inc.
IPC Code(s): H03K3/037, G11C19/28
CPC Code(s): H03K3/037
Abstract: a plurality of flip-flops of an integrated circuit (ic) (e.g., an asic) are electrically connected in a predefined series. the scan input gate of any give flip-flop in the predefined series is electrically connected to one of a q output gate or a q-bar output gate of an adjacent flip-flop in the predefined series. a reset operation for the ic occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the ic.
Inventor(s): Timothy M. Hollis of Meridian ID (US) for micron technology, inc., Chulkyu Lee of Meridian ID (US) for micron technology, inc.
IPC Code(s): H03K3/356, H03K19/0185, H03K19/0944
CPC Code(s): H03K3/356121
Abstract: a device includes a signal path including a plurality of inverters connected in series, which comprises a first inverter having a first input and a having first output, a second inverter having a second input coupled to the first output of the first inverter and having a second output, and a third inverter having a third input coupled to the second output of the second inverter and having a third output. the device also includes a first feedback path connecting the second output of the second inverter to the first input of the first inverter, the first feedback path including a fourth inverter and a second feedback path connecting the third output of the third inverter to the second input of the second inverter, the second feedback path including a fifth inverter.
20240429944. ERROR CORRECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Yang Lu of Boise ID (US) for micron technology, inc.
IPC Code(s): H03M13/15, G06F13/42, H03M13/09
CPC Code(s): H03M13/152
Abstract: methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (mtb) to a plurality of linked (lk) die input/output (ldio) lines coupling a lk die to an interface (if) die. the plurality of pairs of bits of the mtb can be communicated from the lk die to the if die via the plurality of ldio lines. responsive to a failure of one of the plurality of ldio lines, a bose-chaudhuri-hocquenghem (bch) error correction can be performed on the pairs of bits mapped to the failed ldio line. each of the plurality of pairs of bits is a respective symbol for the bch error correction.
Inventor(s): Jeffrey Charles Shiner of Richardson TX (US) for micron technology, inc., Lance W. Dover of Fair Oaks CA (US) for micron technology, inc.
IPC Code(s): H04L9/40, H04L9/14
CPC Code(s): H04L63/083
Abstract: a security server to validate identity data of computing devices having secure memory devices and track activities of components in the computing devices. the server system is configured to store data representative of a unique device secret sealed in the memory device. the server system can generate a first cryptographic key independently from the memory device generating a second cryptographic key. the memory device uses the second cryptographic key to generate identity data including a message and a verification code generated via cryptographic operations combining the message and the second cryptographic key. the server system can use the first cryptographic key to determine whether the verification code is valid for the message. if so, the security server can generate an activity record associating the activity of the computing device with identifications of respective components of the computing device confirmed via validation of the identity data.
Inventor(s): Scott J. Derner of Boise ID (US) for micron technology, inc., Charles L. Ingalls of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C11/4091, G11C11/4094, H01L29/78
CPC Code(s): H10B12/00
Abstract: some embodiments include an integrated assembly having a primary access transistor. the primary access transistor has a first source/drain region and a second source/drain region. the first and second source/drain regions are coupled to one another when the primary access transistor is in an on mode, and are not coupled to one another when the primary access transistor is in an off mode. a charge-storage device is coupled with the first source/drain region. a digit line is coupled with the second source/drain region through a secondary access device. the secondary access device has an on mode and an off mode. the digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective on modes.
Inventor(s): Yoshitaka Nakamura of Boise ID (US) for micron technology, inc., Ashwin Panday of Boise ID (US) for micron technology, inc., Iche Huang of Boise ID (US) for micron technology, inc., Richard Beeler of Boise ID (US) for micron technology, inc., Dojun Kim of Boise ID (US) for micron technology, inc., Lane T. Cunningham of Meridian ID (US) for micron technology, inc., Adriel Jebin Jacob Jebaraj of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: methods, apparatuses, and systems related to a three-dimensional semiconductor device having a doped liner at least disposed between a capacitor and an access device. the doped liner may be configured to provide dopants that diffuse into a semiconductor path of the access device and improve an electrical connection between the access device and the capacitor.
Micron Technology, Inc. patent applications on December 26th, 2024
- Micron Technology, Inc.
- C23C16/455
- C23C16/24
- CPC C23C16/45527
- Micron technology, inc.
- G06F3/06
- CPC G06F3/0617
- G11C16/04
- G11C16/08
- G11C16/26
- CPC G06F3/0619
- G06F1/08
- G06F1/28
- CPC G06F3/0625
- CPC G06F3/0638
- CPC G06F3/0653
- G06F12/0864
- CPC G06F3/0659
- G06F11/07
- G06F9/4401
- CPC G06F11/0787
- G06F11/10
- CPC G06F11/1004
- G06F12/02
- G06F1/3225
- CPC G06F12/0246
- G06F13/16
- CPC G06F12/0292
- G06F12/0815
- CPC G06F12/0815
- G06F13/10
- G06F12/0802
- G06F13/12
- CPC G06F13/102
- G06F30/3308
- G06F30/333
- G06F119/06
- CPC G06F30/3308
- G11C7/10
- G11C11/56
- CPC G11C7/1063
- G11C11/22
- CPC G11C11/2255
- G11C11/406
- G11C7/22
- CPC G11C11/40615
- G11C11/4076
- CPC G11C11/40622
- CPC G11C11/4076
- G11C11/4078
- CPC G11C11/4078
- G11C11/54
- G06F12/0862
- G06F12/0897
- G06N3/063
- G06N3/08
- CPC G11C11/54
- G11C16/10
- G11C16/34
- CPC G11C16/08
- H01L29/10
- H01L29/78
- CPC G11C16/102
- G11C16/24
- CPC G11C16/26
- H01L23/498
- CPC G11C16/3418
- CPC G11C16/3459
- H01L21/8238
- H01L21/02
- H01L21/308
- H01L21/822
- H01L21/84
- H01L27/06
- H01L27/088
- H01L29/08
- H01L29/423
- H01L29/66
- H01L29/786
- H10B12/00
- CPC H01L21/823885
- H01L23/538
- H01L21/48
- H01L21/50
- H01L21/768
- H01L25/065
- CPC H01L23/5384
- H01L23/00
- H01L23/48
- CPC H01L24/14
- H01L25/00
- H01L25/16
- H01L25/18
- H03K3/037
- G11C19/28
- CPC H03K3/037
- H03K3/356
- H03K19/0185
- H03K19/0944
- CPC H03K3/356121
- H03M13/15
- G06F13/42
- H03M13/09
- CPC H03M13/152
- H04L9/40
- H04L9/14
- CPC H04L63/083
- G11C11/4091
- G11C11/4094
- CPC H10B12/00
- CPC H10B12/30
