Micron Technology, Inc. patent applications on December 19th, 2024
Patent Applications by Micron Technology, Inc. on December 19th, 2024
Micron Technology, Inc.: 37 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (7), G06F11/10 (5), H10B43/27 (4), G11C7/10 (3), H10B43/35 (3) G06F11/1068 (3), H01L23/481 (1), G11C16/3459 (1), G11C16/3495 (1), G11C27/005 (1)
With keywords such as: memory, data, device, region, cells, die, based, parity, host, and write in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Tomer Eliash of Sunnyvale CA (US) for micron technology, inc., Jianmin Huang of San Carlos CA (US) for micron technology, inc., Zhengang Chen of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: aspects of the present disclosure configure a memory sub-system controller to read data from a first portion of a memory based on read levels previously established while reading a second portion of the memory. the controller receives a request to read data from a first portion of a set of memory components. the controller identifies a second portion of the set of memory components that has been programmed with data within a threshold period of time of programming the data in the first portion. the controller retrieves a set of read threshold levels that have been previously computed in association with reading the data from the second portion. the controller reads the data from the first portion using the set of read threshold levels that have been previously computed in association with reading the data from the second portion.
20240419336. APPARATUS WITH SIGNAL QUALITY FEEDBACK_simplified_abstract_(micron technology, inc.)
Inventor(s): Jackson Callaghan of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, H04L7/00, H04L25/06
CPC Code(s): G06F3/0619
Abstract: methods, apparatuses, and systems related to operations for measuring the quality of a signal received by a memory device and providing feedback. the memory device can sample signal data using a predetermined sequence of timing offsets relative to a reference signal. additionally or alternatively, the memory device can sample the signal data using a predetermined sequence of reference voltages. the memory device can provide feedback results to a controller regarding the quality of the sampled signal data.
20240419338. DATA MASKING FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Angelo Visconti of Appiano Gentile (CO) (IT) for micron technology, inc., Jahanshir Javanifard of Carmichael CA (US) for micron technology, inc., Daniele Vimercati of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0623
Abstract: methods, systems, and devices for data masking for memory are described. a memory device may set multiple data masking flags for associated memory array(s) at power-up. each data masking flag may be associated with a respective page of memory cells and may indicate whether the data stored in the respective page is masked data, or whether the data is new, unmasked data. data existing at a previous power-down may be masked until an initial write or activate command has been performed on the page after power-up, where the initial write or activate command may result in writing masked data, write data, or a combination thereof to the page. after previously stored data is overwritten to a page, the flag associated with the page may be reset, which may indicate that data stored at the page is available to be read.
Inventor(s): Luca Bert of Bologna (BO) (IT) for micron technology, inc., Joseph Harold Steinmetz of Loomis CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0631
Abstract: an apparatus with a solid state drive (ssd) configured to manage storage resources for proof of space activities. the ssd has a host interface configured to receive at least read commands and write commands from an external host system. the ssd has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands and the write commands. in response to an indication of a storage space request for the host system, the apparatus identifies a portion of storage resources used to store the data of the proof of space plot, and reallocates the portion to service the host system. subsequently, the ssd can continue proof of space activities based on the proof of space plot using the data stored in a remaining portion of the storage resources initially allocated to the proof of space plot.
Inventor(s): Francesco Basso of Portici (NA), (IT) for micron technology, inc., Antonino Pollio of Vico Equense (NA) (IT) for micron technology, inc., Francesco Falanga of Quarto (NA) (IT) for micron technology, inc., Massimo Iaculo of San Marco Evangelista (CE) (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0653
Abstract: methods, systems, and devices for idle mode temperature control for memory systems are described. a memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. for example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. the memory system may measure the temperature of the memory device during the idle mode. if the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.
Inventor(s): Rakeshkumar Dayabhai Vaghasiya of Hyderabad (IN) for micron technology, inc., Nicola Colella of Capodrise (CE) (IT) for micron technology, inc., Mani Raghavendra Aravapalli of Hyderabad (IN) for micron technology, inc., Anilkumar Rameshbhai Sindhi of Hyderabad (IN) for micron technology, inc., Dhruv Chauhan of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for data relocation scheme selection for a memory system are described. a system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. a relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. a relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.
Inventor(s): Shakeel Isamohiuddin BUKHARI of San Jose CA (US) for micron technology, inc., Mark ISH of Manassas VA (US) for micron technology, inc.
IPC Code(s): G06F11/00, G06F12/02, G06F12/12
CPC Code(s): G06F11/004
Abstract: in some implementations, a memory device may cache a subset of one or more block family error avoidance (bfea) lookup tables associated with a block family associated with host data in a first memory location. the block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. the memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more bfea tables, a threshold voltage offset associated with the host data. the memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. the memory device may read, using the modified threshold voltage, the host data from the first memory location.
Inventor(s): Christopher Baronne of Allen TX (US) for micron technology, inc.
IPC Code(s): G06F11/07, G06F9/38
CPC Code(s): G06F11/0793
Abstract: devices and techniques for parking threads in a barrel processor for managing hazard clearing are described herein. a barrel processor includes hazard management circuitry that is used to receive an indication of an instruction executing in a compute pipeline of the barrel processor, the instruction having encountered a hazard and unable to progress through the compute pipeline; store the indication of the instruction in a hazard memory; receive a signal indicating that the hazard has cleared; and cause the instruction to be rescheduled at the beginning of the compute pipeline in response to the signal.
20240419542. COMMAND ADDRESS FAULT DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Melissa I. URIBE of El Dorado Hills CA (US) for micron technology, inc., Steffen BUCH of Muenchen (DE) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: implementations described herein relate to command address fault detection. a memory device may receive, from a host device via a command address (ca) bus, a plurality of ca bits associated with a command signal or an address signal. the memory device may receive, from the host device via the ca bus, a first set of parity bits that is based on the plurality of ca bits and a select parity generation process. the memory device may generate a second set of parity bits, based on the plurality of ca bits, using the select parity generation process. the memory device may compare the first set of parity bits and the second set of parity bits. the memory device may selectively transmit an alert signal to the host device based on comparing the first set of parity bits and the second set of parity bits.
20240419543. PROXIMITY BASED PARITY DATA MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Wei Wang of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/14, G06F11/34
CPC Code(s): G06F11/1068
Abstract: a method includes generating parity data corresponding to a plurality of word lines coupled to blocks of a memory device and generating additional parity data for a block based on a physical location of the block. the method can further include performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.
Inventor(s): Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, H03M13/11
CPC Code(s): G06F11/1068
Abstract: a memory device to use added known data as part of data written to memory cells with redundant data generated according to an error correction code (ecc). the code rate of the ecc may limit its capability to recover from excessive errors in the stored data. to reduce the errors, the added data retrieved from the memory cells can be corrected without using the ecc. subsequently, remaining errors can be corrected via the ecc. optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.
Inventor(s): Christophe Laurent of Agrate Brianza (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1076
Abstract: the present disclosure relates to defining a minimum number of parity cells for storing parity data, the minimum number of parity cells corresponding to a minimum error correction code (ecc) correction capability, defining a maximum number of parity cells for storing the parity data, the maximum number of parity cells corresponding to a maximum ecc correction capability, storing payload content in a plurality of memory cells of a memory array, and, based on a current status of the memory cells storing the payload, selecting a number of parity cells to be used for storing the parity data between the minimum number and the maximum number. the payload is stored in at least part of the parity cells which are not selected to store parity data. related memory devices and systems are also herein disclosed.
Inventor(s): Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Helena Caminal of Ithaca NY (US) for micron technology, inc., Sean S. Eilert of Penryn CA (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/108
Abstract: methods, systems, and devices for parity-based error management are described. a processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. the processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.
20240419588. SEQUENTIAL GARBAGE COLLECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): David A. Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0253
Abstract: an example apparatus for sequential garbage collection can include a memory device including a plurality of memory blocks associated with a plurality of logical block addresses (lbas). the example apparatus can include a controller coupled to the memory device. the controller can be configured to monitor a quantity of read operations and a quantity of write operations associated with a plurality of command sizes performed on a portion of the plurality of memory blocks. the controller can be configured to monitor a quantity of read operations and a quantity of write operations associated with a particular lba. the controller can be configured to determine a type of garbage collection operation to perform based on the monitoring.
Inventor(s): Olivier Duval of Pacifica CA (US) for micron technology, inc.
IPC Code(s): G06F16/17, G06F11/14, G06F12/02, G06F16/16, G06F16/18
CPC Code(s): G06F16/1734
Abstract: a processing device writes file system data to a first area of a memory zone of a zoned block memory device based on a current position of a write pointer within the memory zone. the file system data comprises data files contained within a file system and file structure metadata describing a file structure of the file system. the processing device detects a write event based on the write pointer advancing past a predetermined memory address within the memory zone that corresponds to a checkpoint. the checkpoint is a second area within the memory zone that is designated for storing write event data. based on detecting the write event, the processing device writes write event data to the checkpoint, the first write event data indicating a most recent memory address of a root node of the file structure within the memory zone.
Inventor(s): Saideep TIKU of Folsom CA (US) for micron technology, inc., Poorna KALE of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06T19/00, G06Q30/0601, G06V20/68
CPC Code(s): G06T19/006
Abstract: in some implementations, an extended reality (xr) device may receive, via an interface of the xr device, an input associated with meals of a user associated with the xr device. the xr device may determine, based on the input, a meal plan for the user of the xr device, wherein the meal plan is associated with target meals. the xr device may determine, based on recipes for the target meals, a list of food items for preparing the target meals associated with the meal plan. the xr device may provide, via the interface, the list of food items and the target meals. the xr device may provide, via the interface, an in-store navigation path to direct the user of the xr device via overlayed audio-visual cues to locations within a physical retail store to pick up the food items.
Inventor(s): Alyssa N. Scarbrough of Boise ID (US) for micron technology, inc.
IPC Code(s): G06V20/20, G06F40/35, G06V20/40, G06V40/16, G08B21/02, G08B25/00
CPC Code(s): G06V20/20
Abstract: disclosed in some examples are methods, systems, and machine-readable mediums which utilize augmented reality devices to detect and warn vulnerable individuals about real-life situations that could pose a hazard to their safety. one or more signals identified from data captured by sensors of one or more devices of the user may be analyzed to determine whether elements such as persons, objects, or the like pose a danger to the user. the system, upon detection of an unsafe event, situation, or person may then warn the user through the augmented reality glasses of the unsafe events, situations, or persons. in addition, a caregiver or other individual and/or the police may also be notified.
Inventor(s): Gil Golov of Backnang (DE) for micron technology, inc.
IPC Code(s): G11C7/06, G06F21/60, G06F21/78, G11C7/10
CPC Code(s): G11C7/065
Abstract: systems, methods, and apparatus related to validating data stored in a memory system. in one approach, a dram stores data for a host device. a controller that manages the dram receives a command from the host device to generate a signature. the controller also receives data from the host device that indicates a region of the dram. in response to receiving the command, the controller reads data from the indicated region. a signature is generated by the controller based on the data read from the indicated region. the generated signature is sent to the host device in response to the command.
Inventor(s): Brian W. Huber of Allen TX (US) for micron technology, inc., Scott E. Smith of Plano TX (US) for micron technology, inc., Gary L. Howe of Allen TX (US) for micron technology, inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1084
Abstract: a memory device includes a command interface configured to receive write commands from a host device. additionally, the memory device includes an input buffer configured to buffer a strobe signal from the host device. furthermore, the memory device includes a first ripple counter and a second ripple counter. the memory device includes command handling circuitry configured to alternatingly start the first ripple counter and the second ripple counter in response to consecutive write commands. the command handling circuitry and/or the first and second ripple counters are configured to suppress a reset of the input buffer if either the first ripple counter or the second ripple counter has not reached a threshold and is still counting.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Alessandro Calderoni of Boise ID (US) for micron technology, inc., Richard E. Fackenthal of Carmichael CA (US) for micron technology, inc., Duane R. Mills of Shingle Springs CA (US) for micron technology, inc.
IPC Code(s): G11C11/404
CPC Code(s): G11C11/404
Abstract: some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.
Inventor(s): Glen E. Hush of Boise ID (US) for micron technology, inc., Sean S. Eilert of Penryn CA (US) for micron technology, inc., Aliasger T. Zaidy of Seattle WA (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4093, G06F3/06, G06F13/16, G06F13/28, G11C7/08, G11C7/10, G11C11/408, G11C11/4091, G11C11/4096, G16B30/00, G16B50/10, H01L21/66, H01L21/78, H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): G11C11/4093
Abstract: a memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. each of a plurality of subsets of the sense lines is coupled to a respective local input/output (i/o) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local i/o line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.
Inventor(s): Jun Fujiki of Tokyo (JP) for micron technology, inc., Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc., Akira Goda of Setagaya (JP) for micron technology, inc.
IPC Code(s): G11C16/08, G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): G11C16/08
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.
Inventor(s): Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc., Jun Fujiki of Tokyo (JP) for micron technology, inc., Shuji Tanaka of Kanagawa (JP) for micron technology, inc., Masanobu Saito of Chiba City (JP) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): G11C16/10
Abstract: apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells, a data line, a first field-effect transistor between the data line and a first string of series-connected memory cells, and a second field-effect transistor between the data line and a second string of series-connected memory cells, wherein a control gate of the first field-effect transistor is connected to a control gate of the second field-effect transistor, and wherein a channel of the first field-effect transistor was fabricated to have a first threshold voltage and a channel of the second field-effect transistor was fabricated to have a second threshold voltage, different than the first threshold voltage.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc., Tomer Tzvi ELIASH of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/24, G11C16/32
CPC Code(s): G11C16/3459
Abstract: implementations described herein relate to detecting a memory write reliability risk without using a write verify operation. in some implementations, a memory device may perform a program operation that includes a single program pulse and that does not include a program verify operation immediately after the single program pulse. the memory device may set a flag value based on comparing a transition time and a transition time threshold. the transition time may be a time to transition from a first voltage to a second voltage during the program operation. the memory device may selectively perform a mitigation operation based on whether the flag value is set to a first value or a second value.
Inventor(s): Murong Lang of San Jose CA (US) for micron technology, inc., Peng Zhang of Los Altos CA (US) for micron technology, inc., Lei Lin of Fremont CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Jun Wan of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10
CPC Code(s): G11C16/3495
Abstract: aspects of the present disclosure configure a memory sub-system controller to selectively adjust a program pulse for different word line groups of a memory sub-system. the controller receives a request to program data to an individual memory component of a set of memory components. the controller determines that a program erase count (pec) associated with the individual memory component transgresses a threshold value. the controller, in response to determining that the pec associated with the individual memory component transgresses the threshold value, selectively adjusts a predetermined program voltage (vpgm) associated with a subset of word lines (wls) of the individual memory component based on whether the subset of wls is associated with an individual wl group (wlg). the controller programs the data to the individual memory component according to the selectively adjusted predetermined vpgm.
20240420786. ANALOG STORAGE USING MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Mattia Boniardi of Cormano (MI) (IT) for micron technology, inc., Innocenzo Tortorelli of Cernusco sul Naviglio (MI) (IT) for micron technology, inc.
IPC Code(s): G11C27/00, G06N3/065, G06N3/08
CPC Code(s): G11C27/005
Abstract: methods, systems, and devices for analog storing information are described herein. such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. a memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. memory cells may be provided on different decks of a multi-deck memory array. a storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. the memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.
20240420789. SELF-CALIBRATION IN A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Jennifer E. Taylor of Boise ID (US) for micron technology, inc., Eric J. Stave of Meridian ID (US) for micron technology, inc., Timothy M. Hollis of Meridian ID (US) for micron technology, inc., Chulkyu Lee of Meridian ID (US) for micron technology, inc., Chris Gregory Holub of Bath PA (US) for micron technology, inc.
IPC Code(s): G11C29/12, G11C29/20
CPC Code(s): G11C29/12015
Abstract: systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. the semiconductor device receives an indication of a condition for re-training of the equalizer. the semiconductor device operates the equalizer based on trained values derived during the self-training. the semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.
20240420790. SELF-CALIBRATION IN A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Jennifer E. Taylor of Boise ID (US) for micron technology, inc., Eric J. Stave of Meridian ID (US) for micron technology, inc., Timothy M. Hollis of Meridian ID (US) for micron technology, inc., Chulkyu Lee of Meridian ID (US) for micron technology, inc., Chris Gregory Holub of Bath PA (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C29/12
CPC Code(s): G11C29/42
Abstract: systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. the received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. a first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. the first received bit is also latched in error evaluation circuitry as a second latched bit. the second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. the self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.
Inventor(s): Bharat Bhushan of Taichung (TW) for micron technology, inc., Amy R. Griffin of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Akshay N. Singh of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L23/373, H01L23/00, H01L23/29, H01L23/31, H01L25/00, H01L25/065, H10B80/00
CPC Code(s): H01L23/373
Abstract: a semiconductor device is provided. the semiconductor device includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die at a first location above a back side surface of the logic die, a second plurality of stacked memory dies electrically coupled with the logic die at a second location above the back side surface of logic die, a first dielectric material disposed above the back side surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies, and a dummy die disposed above the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to back side surfaces of the first plurality and second plurality of stacked memory dies through a second dielectric layer having dielectric-dielectric fusion bonding.
20240421040. APPARATUS INCLUDING TSV STRUCTURE_simplified_abstract_(micron technology, inc.)
Inventor(s): SEIJI NARUI of Sagamihara (JP) for micron technology, inc., SHIRO UCHIYAMA of Tokyo (JP) for micron technology, inc., BANG NING HSU of West Central (TW) for micron technology, inc., KAYOKO SHIBATA of Tokyo (JP) for micron technology, inc., FUMIYUKI OSANAI of Sagamihara (JP) for micron technology, inc.
IPC Code(s): H01L23/48, H01L23/00, H01L23/528, H10B80/00
CPC Code(s): H01L23/481
Abstract: according to one or more embodiments of the disclosure, an apparatus comprises a logic die including a plurality of first through-silicon vias (tsvs), and a core die on the logic die including a plurality of tsvs. the number of the first tsvs in the logic die is different from the number of the second tsvs in the core die.
Inventor(s): Hung-Wei Liu of Meridian ID (US) for micron technology, inc., Sameer Chhajed of Boise ID (US) for micron technology, inc., Jeffery B. Hull of Boise ID (US) for micron technology, inc., Anish A. Khandekar of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/78, H01L21/02, H01L29/04, H01L29/66, H10B12/00
CPC Code(s): H01L29/7841
Abstract: a transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. at least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. all crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 �mof one another. other embodiments, including methods, are disclosed.
Inventor(s): Tony M. Brewer of Plano TX (US) for micron technology, inc.
IPC Code(s): H03K19/17756, G11C16/04, H01L27/06, H03K17/687, H03K19/0948, H03K19/17704, H03K19/17764, H10B41/40, H10B63/00
CPC Code(s): H03K19/17756
Abstract: a three-dimensional stacked integrated circuit (3d sic) having a non-volatile memory die, a volatile memory die, and a logic die. the non-volatile memory die, the volatile memory die, and the logic die are stacked. the 3d sic is partitioned into a plurality of columns that are perpendicular to each of the stacked dies. each column of the plurality of columns is configurable to be bypassed via configurable routes. when the configurable routes are used, functionality of a failing part of the column is re-routed to a corresponding effective part of a neighboring column.
Inventor(s): Jonathan D. Harms of Boise ID (US) for micron technology, inc.
IPC Code(s): H04L9/32, G06Q20/06, G06Q20/38, H04L9/00
CPC Code(s): H04L9/3218
Abstract: computerized apparatus using characterized devices such as memories for intensive computational applications such as blockchain processing. in one embodiment, the computerized apparatus comprises a computational appliance (e.g., stand-alone box, server blade, plug-in card, or mobile device) that includes characterized memory devices. these memory devices are associated with a range of performances over a range of operational parameters, and can be used in conjunction with a solution density function to optimize memory searching. in one embodiment, the ledger appliance can communicate with other ledger appliances to create and/or use a blockchain ledger so as to facilitate decentralized exchanges between untrusted parties. in some variants, the ledger appliance may additionally use an application programming interface (api) to dynamically generate blockchains on the fly. various other applications are also described (e.g., social media, machine learning, probabilistic applications and other error-tolerant applications).
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc., Te-Chang Lin of New Taipei City (TW) for micron technology, inc.
IPC Code(s): H04N21/2343, G06F9/30, G06F13/38, G06N3/02, G06N3/049, G06N3/08, G06V10/764, G06V10/82, G06V20/52, H04N19/46, H04N19/50, H04N19/70
CPC Code(s): H04N21/2343
Abstract: systems, devices, and methods related to a deep learning accelerator and memory are described. for example, a removable media (e.g., a memory card, or a usb drive) may be configured to execute instructions with matrix operands and configured with: an interface to receive a video stream; and random access memory to buffer a portion of the video stream as an input to an artificial neural network and to store instructions executable by the deep learning accelerator and matrices of the artificial neural network. such a removable media can be used to replace an existing removable media used in a surveillance camera to record video or images. the deep learning accelerator can execute the instructions to generate analytics of the buffer portion using the artificial neural network, enabling the surveillance camera that is upgraded via the use of the removable media to provide intelligent services based on the analytics.
Inventor(s): Jeffrey Charles Shiner of Richardson TX (US) for micron technology, inc., Lance W. Dover of Fair Oaks CA (US) for micron technology, inc., Olivier Duval of Pacifica CA (US) for micron technology, inc.
IPC Code(s): H04W12/42, H04L9/32, H04W8/18, H04W12/069
CPC Code(s): H04W12/42
Abstract: a system, method and apparatus to authenticate an endpoint having a secure memory device. for example, a card profile can be selected, configured, and/or stored into the secure memory device based on endpoint identity data representative of a component configuration of the endpoint, including the device identity representative of the memory device and other components. the card profile can be used by the endpoint to emulate a physical smart card and can be viewed a virtual smart card, such as a virtual subscriber identification module (sim) card for accessing a cellular connection.
Inventor(s): Yoshiaki Fukuzumi of Tokyo (JP) for micron technology, inc.
IPC Code(s): H10B43/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: a method of forming a microelectronic device includes forming a preliminary stack structure, forming a cell slit extending through the preliminary stack structure, forming oxide separator structures, forming a sacrificial backfill, removing the oxide separator structures to form separator recesses, forming preliminary separator structures in the separator recesses, forming vertical memory string structures within the cell slit, and replacing the sacrificial backfill with conductive material. the preliminary stack structure includes tiers, each tier including a sacrificial material and an insulative material. the oxide separator structures are horizontally adjacent to the cell slit and may vertically extend through the preliminary stack structure. the memory cell material are formed within the cell slit over the preliminary separator structures. the vertical memory string structures vertically extend through the preliminary stack structure and are horizontally separated from one another by separator structures formed from the preliminary separator structures.
Inventor(s): Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B63/00, G11C5/06, H01L25/16, H01L25/18, H10B41/27, H10B41/35, H10B41/41, H10B43/27, H10B43/35, H10B43/40, H10N70/00
CPC Code(s): H10B63/84
Abstract: a method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. an additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. a portion of the semiconductive material is removed. a second control logic region is formed over the first memory array region. the second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. a second memory array region is formed over the second control logic region. the second memory array region comprises an array of resistance variable memory cells. microelectronic devices, memory devices, and electronic systems are also described.
Micron Technology, Inc. patent applications on December 19th, 2024
- Micron Technology, Inc.
- G06F3/06
- CPC G06F3/0613
- Micron technology, inc.
- H04L7/00
- H04L25/06
- CPC G06F3/0619
- CPC G06F3/0623
- CPC G06F3/0631
- CPC G06F3/0653
- CPC G06F3/0659
- G06F11/00
- G06F12/02
- G06F12/12
- CPC G06F11/004
- G06F11/07
- G06F9/38
- CPC G06F11/0793
- G06F11/10
- CPC G06F11/1068
- G06F11/14
- G06F11/34
- H03M13/11
- CPC G06F11/1076
- CPC G06F11/108
- CPC G06F12/0253
- G06F16/17
- G06F16/16
- G06F16/18
- CPC G06F16/1734
- G06T19/00
- G06Q30/0601
- G06V20/68
- CPC G06T19/006
- G06V20/20
- G06F40/35
- G06V20/40
- G06V40/16
- G08B21/02
- G08B25/00
- CPC G06V20/20
- G11C7/06
- G06F21/60
- G06F21/78
- G11C7/10
- CPC G11C7/065
- CPC G11C7/1084
- G11C11/404
- CPC G11C11/404
- G11C11/4093
- G06F13/16
- G06F13/28
- G11C7/08
- G11C11/408
- G11C11/4091
- G11C11/4096
- G16B30/00
- G16B50/10
- H01L21/66
- H01L21/78
- H01L23/00
- H01L25/00
- H01L25/065
- H01L25/18
- CPC G11C11/4093
- G11C16/08
- G11C16/04
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- CPC G11C16/08
- G11C16/10
- CPC G11C16/10
- G11C16/34
- G11C16/24
- G11C16/32
- CPC G11C16/3459
- CPC G11C16/3495
- G11C27/00
- G06N3/065
- G06N3/08
- CPC G11C27/005
- G11C29/12
- G11C29/20
- CPC G11C29/12015
- G11C29/42
- CPC G11C29/42
- H01L23/373
- H01L23/29
- H01L23/31
- H10B80/00
- CPC H01L23/373
- H01L23/48
- H01L23/528
- CPC H01L23/481
- H01L29/78
- H01L21/02
- H01L29/04
- H01L29/66
- H10B12/00
- CPC H01L29/7841
- H03K19/17756
- H01L27/06
- H03K17/687
- H03K19/0948
- H03K19/17704
- H03K19/17764
- H10B41/40
- H10B63/00
- CPC H03K19/17756
- H04L9/32
- G06Q20/06
- G06Q20/38
- H04L9/00
- CPC H04L9/3218
- H04N21/2343
- G06F9/30
- G06F13/38
- G06N3/02
- G06N3/049
- G06V10/764
- G06V10/82
- G06V20/52
- H04N19/46
- H04N19/50
- H04N19/70
- CPC H04N21/2343
- H04W12/42
- H04W8/18
- H04W12/069
- CPC H04W12/42
- CPC H10B43/27
- G11C5/06
- H01L25/16
- H10B41/41
- H10B43/40
- H10N70/00
- CPC H10B63/84
