Micron Technology, Inc. patent applications on December 12th, 2024
Patent Applications by Micron Technology, Inc. on December 12th, 2024
Micron Technology, Inc.: 44 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (12), H01L25/065 (4), G11C29/12 (4), G11C7/10 (3), H01L25/18 (3) H01L25/0657 (3), G06F3/0659 (3), H01L22/12 (1), G11C16/3404 (1), G11C29/12005 (1)
With keywords such as: memory, data, device, circuit, command, configured, translation, unit, cells, and control in patent application abstracts.
Patent Applications by Micron Technology, Inc.
20240411090. METHOD OF FORMING PHOTONICS STRUCTURES_simplified_abstract_(micron technology, inc.)
Inventor(s): Gurtej Sandhu of Boise ID (US) for micron technology, inc.
IPC Code(s): G02B6/42, G02B6/12, G02B6/122, H01L21/324, H01L27/06, H01L31/0232, H01L31/18
CPC Code(s): G02B6/42
Abstract: the disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a cmos semiconductor structure containing electronic devices. doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.
Inventor(s): Yu-Chung Lien of San Jose CA (US) for micron technology, inc., Tomer Tzvi Eliash of Sunnyvale CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0604
Abstract: a processing device, operatively coupled with a memory device, performs a first sequence of programming operations on a first set of cells addressable by a first wordline of the memory device. the processing device identifies a second wordline of the memory device, wherein a second physical location of the second wordline is in a predefined relationship with a first physical location of the first wordline. the processing device performs a second sequence of programming operations on a second set of cells addressable by the second wordline of the first die, wherein a first order of the first sequence of programming operations is different from a second order of the second sequence of programming operations.
20240411451. DATA STRIPE PROTECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Daniele Balluchi of Cernusco Sul Naviglio (IT) for micron technology, inc.
IPC Code(s): G06F3/06, G06F11/07, G06F11/10
CPC Code(s): G06F3/061
Abstract: systems, apparatuses, and methods related to data stripe protection are described. an error management component can process multiple read/write/recovery requests concurrently. when read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.
Inventor(s): Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a method includes determining a logical saturation of a memory device in a memory sub-system and adjusting a code rate of the memory device based on the logical saturation, wherein the code rate represents a ratio of user data to a combination of the user data and error correction data.
20240411465. SELECTIVE DATA MAP UNIT ACCESS_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco REDAELLI of Munich (DE) for micron technology, inc., Gaurav SINHA of Unterschleißheim (DE) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0631
Abstract: implementations described herein relate to selective data map unit access. a memory device may receive a request from a host device to access a resource associated with a data map unit. the memory device may identify whether the data map unit is in a locked state or an unlocked state. the data map unit may be in the locked state when another host device currently has exclusive access to the resource or may be in the unlocked state when no other host device currently has exclusive access to the resource. the memory device may selectively grant the host device exclusive access to the resource based on identifying whether the data map unit is in the locked state or the unlocked state.
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Edmund J. Gieske of Cedar Park TX (US) for micron technology, inc., Cagdas Dirik of Indianola WA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Elliott C. Cooper-Balis of San Jose CA (US) for micron technology, inc., Amitava Majumdar of Boise ID (US) for micron technology, inc., Robert M. Walker of Raleigh NC (US) for micron technology, inc., Danilo Caraccio of Milano (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: systems, methods, and apparatus for memory device security and row hammer mitigation are described. a control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. a row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (cam) of the memory sub-system may be received. control circuitry may determine whether the first count is greater than a row hammer threshold (rht) minus a second count of a cam decrease counter (cdc); the second count may be incremented each time the cam is full. a refresh command to the row address may be issued when a determination is made that the first count is greater than the rht minus the second count.
Inventor(s): Shiva Pahwa of Bangalore (IN) for micron technology, inc., Abhilash Ramamurthy Nag of Bangalore (IN) for micron technology, inc., Sathyashankara Bhat Muguli of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0644
Abstract: respective temperature values for a plurality of dies of a memory device is obtained. each respective temperature value is indicative of a temperature at a corresponding die of the plurality of dies of the memory device. the plurality of dies based on the respective temperature values, each die of the plurality of dies is ordered. a zone creation command directed to the memory device is received from a host. the zone creation command on the memory device on a die of the ordered plurality of dies is performed based on a temperature threshold.
20240411471. THE USE OF MIMO IN MEMORY CONTROLLERS_simplified_abstract_(micron technology, inc.)
Inventor(s): Fa-Long Luo of San Jose CA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0647
Abstract: the present invention relates to a memory controller and a memory device that are configured to communicate with each other using multiple input multiple output (mimo) technology. the memory controller includes a precoder that precodes data for transmission. the precoding is based on channel state information, a neural network, or both. the memory device receives the precoded data and decodes them to retrieve the original data. in some cases, the precoder uses the channel state information to optimize the precoding matrix for the given channel conditions. in some cases, a neural network is trained to predict the optimal precoding matrix for the current channel state. the precoding matrix is then used to encode the data, which is then transmitted to the memory device. the use of mimo and precoding improves the reliability and efficiency of the communication between the memory controller and memory device.
Inventor(s): Jianmin Huang of San Carlos CA (US) for micron technology, inc., Xiangang Luo of Fremont CA (US) for micron technology, inc., Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Kulachet Tanpairoj of San Mateo CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0652
Abstract: an apparatus can include a block program erase count (pec) component. the block pec component can monitor a quantity of program erase counts (pecs) for each particular type of block of a non-volatile memory array. the block pec component can further determine which block of the superblock to write host data to next based on the quantity of pecs. the block pec component can further write host data to the determined block.
20240411483. UNMAP BACKLOG IN A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Huachen Li of Shanghai (CN) for micron technology, inc., Xu Zhang of Shanghai (CN) for micron technology, inc., Xing Wang of Shanghai (CN) for micron technology, inc., Guan Zhong Wang of Shanghai (CN) for micron technology, inc., Tian Liang of Shanghai (CN) for micron technology, inc., Junjun Wang of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for unmap backlog in a memory system are described. a memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). in response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. for example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). in some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.
Inventor(s): Juane Li of San Jose CA (US) for micron technology, inc., Jason Duong of Milpitas CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc., Chih-Kuo Kao of Fremont CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a die command from a requestor is received. the die command into a die command queue is stored. the die command from the die command queue into a plurality of partition commands is partitioned. the plurality of partition commands into one of a first plurality of partition command queues or a second plurality of partition command queues is mapped. the partition command of the first plurality of partition command queues or the second plurality of partition command queues is issued to a command processor to be applied to the one or more memory devices.
Inventor(s): Alex Frolikov of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C29/08
CPC Code(s): G06F3/0659
Abstract: a memory system having a mode indicator, a set of hardware resources, a set of media, and a controller. when the mode indicator identifies a factory mode, a first portion of the hardware resources is reserved for performance of factory functions by the controller and a second portion of the hardware resources is allocated for performance of normal functions. when the mode indicator identifies a user mode, both the first portion and the second portion are allocated for the performance of the normal function. the normal functions are performed by the controller to at least store data in and retrieve data from the set of media in response to requests from a host system.
Inventor(s): Christophe Vincent Antoine Laurent of Agrate Brianza (IT) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1048
Abstract: the present disclosure relates to a memory device comprising an array including a plurality of memory cells and an operating unit, the operating unit comprising an encoding unit configured to store user data in a plurality of memory cells of the memory array and to store parity data associated with the user data in a number of parity cells of the memory array, the operating unit further comprising a decoding unit in turn comprising a syndrome generating unit configured to calculate an ecc syndrome from the stored user data and parity data, wherein the syndrome generating unit comprises a plurality of circuit portions, each circuit portion being configured to calculate a respective syndrome portion of the ecc syndrome. the operating unit is configured to activate a first circuit portion of the syndrome generating unit for calculating a first syndrome portion, and, based on the calculated first syndrome portion, decide whether to activate or not to activate a second circuit portion for the calculation of a second syndrome portion. related methods and systems are also herein disclosed.
20240411644. DATA PROTECTION AND RECOVERY_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco Sforzin of Cernusco Sul Naviglio (IT) for micron technology, inc., Paolo Amato of Treviglio (IT) for micron technology, inc., Joseph M. McCrate of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1096
Abstract: a redundant array of independent disks (raid) protection can be provided along with other types of error correction code (ecc) schemes that correct either errors in data prior to the data being input to the raid process or residual errors from the raid process. the ecc schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
20240411655. USING MEMORY DEVICE SENSORS_simplified_abstract_(micron technology, inc.)
Inventor(s): Cheryl M. O'Donnell of Boise ID (US) for micron technology, inc., Erica M. Gove of Boise ID (US) for micron technology, inc., Zahra Hosseinimakarem of Boise ID (US) for micron technology, inc., Debra M. Bell of Boise ID (US) for micron technology, inc., Roya Baghi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/30, B60H1/00, G06F11/32, G06F13/16
CPC Code(s): G06F11/3089
Abstract: systems, apparatuses, and methods related to using memory device sensors are described. some memory system or device types include sensors embedded in their circuitry. for instance, another device can be coupled to a memory device with an embedded sensor. the memory device can transmit a signal representing sensor data generated by the embedded sensor using a sensor output coupled to the other device. a controller coupled to a memory device may determine one or more threshold values of a sensor or sensors embedded in a memory device. the memory device may transmit an indication responsive to one or more sensors detecting a value greater or less than a threshold and may transmit the indication to another device.
Inventor(s): Raja V.S. Halaharivi of Gilroy CA (US) for micron technology, inc., Prateek Sharma of San Jose CA (US) for micron technology, inc., Sumangal Chakrabarty of Campbell CA (US) for micron technology, inc., Venkat R. Gaddam of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F12/10, G06F12/0802
CPC Code(s): G06F12/10
Abstract: a method includes buffering, in a descriptor queue, descriptors associated with translation units of an lba-based, direct memory access (dma) read command of a host system, each descriptor to be linked with a pointer including a physical destination for data associated with a respective translation unit. the method includes sending address translation requests to an address translation circuit for the pointers of respective translation units and detecting an address translation request miss at a cache of the address translation circuit for a first pointer of a first translation unit linked to a first descriptor of the plurality of descriptors. the method includes causing a translation miss message to be sent to a page request interface (pri) handler, the translation miss message containing a virtual address of the first pointer and to trigger the pri handler to send a page miss request to a translation agent of the host system.
20240411701. ADDRESS TRANSLATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Chung Kuang Chin of Saratoga CA (US) for micron technology, inc., Di Hsien Ngu of Zhubei City (TW) for micron technology, inc., Horia C. Simionescu of Foster City CA (US) for micron technology, inc.
IPC Code(s): G06F12/1009
CPC Code(s): G06F12/1009
Abstract: translated addresses of a memory device can be stored in a first lut maintained by control circuitry. untranslated addresses can be stored in a second lut maintained by the control circuitry. in response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second lut associated with the target untranslated address can be determined, the index of the second lut can be mapped to an index of the first lut, and the particular translated address corresponding to the target untranslated address can be retrieved from the first lut.
Inventor(s): Raja V.S. Halaharivi of Gilroy CA (US) for micron technology, inc., Prateek Sharma of San Jose CA (US) for micron technology, inc., Sumangal Chakrabarty of Campbell CA (US) for micron technology, inc., Venkat R. Gaddam of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F12/1045
CPC Code(s): G06F12/1063
Abstract: a method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. the method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. the method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. the method includes sending a translation miss message to a page request interface (pri) handler. the translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the pri handler to send a page miss request to a translation agent of the host system.
Inventor(s): Fa-Long Luo of San Jose CA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): G06F13/16, G06F13/42
CPC Code(s): G06F13/1642
Abstract: an example of compute express link (cxl) system includes a memory, and a tensor access circuit having a memory mapper configured to configure a memory map based on a compute express link (cxl) command associated with an access operation of the memory. the memory map includes a specific sequence of cxl instructions to access to the memory via a cxl bus.
20240412050. NONLINEAR DRAM DIGITAL EQUALIZATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Fa-Long Luo of San Jose CA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): G06N3/048, G06N3/049
CPC Code(s): G06N3/048
Abstract: the present disclosure relates to signal processing systems that employ various techniques to enhance data transfer quality. in some cases, a memory controller uses a neural network (e.g., time delay neural network (tdnn) to enable nonlinear processing to improve equalization. in some other cases, the memory controller uses an activation function to enable nonlinear processing to improve equalization. the systems may incorporate a finite impulse response (fir) filter with the activation function applied to its output. a memory controller including a cache may store precomputed values of the activation function. various types of activation functions or neural network configurations may be employed to introduce nonlinearity and adapt to different application requirements. the present disclosure is applicable in communication systems, control systems, and other digital signal processing systems requiring efficient processing of complex data transmission patterns.
20240412765. MULTI-DRIVER SIGNALING_simplified_abstract_(micron technology, inc.)
Inventor(s): Peter Mayer of Neubiberg (DE) for micron technology, inc., Rethin Raj of Augsburg (DE) for micron technology, inc., Nobuyuki Umeda of Tokyo (JP) for micron technology, inc., Andreas Schneider of Gernlinden (DE) for micron technology, inc., Casto Salobrena Garcia of Munich (DE) for micron technology, inc.
IPC Code(s): G11C7/10
CPC Code(s): G11C7/1084
Abstract: methods, systems, and devices for multi-driver signaling are described. an apparatus may include a first voltage source configured to supply a positive voltage and a second voltage source configured to supply a negative voltage. the apparatus may also include a first driver configured to couple a transmission line of a bus with the first voltage source and a second driver configured to couple the transmission line of the bus with the second voltage source. the first driver may be configured to transfer current to the transmission line based on a configurable resistance of the first driver. and the second driver configured to transfer current from the transmission line of the bus based on a configurable resistance of the second driver.
Inventor(s): Christophe Laurent of Agrate Brianza (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc.
IPC Code(s): G11C11/22, G11C7/10, G11C16/34
CPC Code(s): G11C11/2275
Abstract: the present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. an embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.
20240412770. SEQUENCED ACTIVATION OF MEMORY COMPONENTS_simplified_abstract_(micron technology, inc.)
Inventor(s): Shawn Storm of Boise ID (US) for micron technology, inc., Brittany A. Boyd of Boise ID (US) for micron technology, inc., Christopher Kuhn of Boise ID (US) for micron technology, inc., Eric S. Nelson of Boise ID (US) for micron technology, inc., Craig A. Farrer of Boise ID (US) for micron technology, inc., Kazuo Shibata of Sagamihara City (JP) for micron technology, inc.
IPC Code(s): G11C11/4072, G11C5/14, G11C11/4076
CPC Code(s): G11C11/4072
Abstract: a method includes providing, in accordance with a memory component activation sequence, a first activation power to a first memory component of a plurality of memory components for a first time period, where the first activation power is provided in the absence of providing an activation power to at least one other memory component of the plurality of memory components during the first time period. the method includes providing, in accordance with the memory component activation sequence, a second activation power to a second memory component for a second time period.
Inventor(s): Edric Goh of Singapore (SG) for micron technology, inc., Dheeraj Srinivasan of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G11C16/102
Abstract: a memory device can include a memory array including a plurality of memory cells coupled to a control logic. the control logic is to initiate a program operation on one or more memory cells of a first segment of the memory array, wherein the program operation comprises a first calibration phase. the control logic can also read a first stored value corresponding to a first voltage applied during a second calibration phase for a second segment of the memory array, the second calibration phase before the first calibration phase. the control logic can further read a second stored value corresponding to an offset value associated with the first voltage. additionally, the control logic can determine a second voltage for application during the calibration phase responsive to reading the first stored value and the second stored value.
Inventor(s): Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc., Jun Fujiki of Tokyo (JP) for micron technology, inc., Shuji Tanaka of Kanagawa (JP) for micron technology, inc., Masashi Yoshida of Yokohama (JP) for micron technology, inc., Masanobu Saito of Chiba City (JP) for micron technology, inc., Yoshihiko Kamata of Yokohama (JP) for micron technology, inc.
IPC Code(s): G11C16/26, G11C16/04
CPC Code(s): G11C16/26
Abstract: apparatus might include a plurality of series-connected first field-effect transistors selectively connected in series with a plurality of series-connected second field-effect transistors, wherein the plurality of series-connected first field-effect transistors are configured to store user data, and wherein a channel of the plurality of series-connected second transistors is capacitively coupled to a channel of a third transistor.
Inventor(s): Phong Sy Nguyen of Livermore CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C7/10, G11C16/10, G11C16/26, G11C16/30
CPC Code(s): G11C16/3404
Abstract: a memory system to store multiple bits of data in a memory cell. after receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. the threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. a group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. the memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.
Inventor(s): Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Patrick Robert Khayat of San Diego CA (US) for micron technology, inc., AbdelHakim S. Alhussien of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/12, G06F18/214, G06N20/00, G11C7/02, G11C29/14, G11C29/44
CPC Code(s): G11C29/12005
Abstract: a memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. for example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. the memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. the memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.
Inventor(s): Fa-Long Luo of San Jose CA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): G11C29/12, G11C11/54, G11C29/36
CPC Code(s): G11C29/1201
Abstract: a memory includes a receiver circuit configured to receive write data via a data terminal, and a neural network based preconditioning circuit configured to receive a write data signal according to the write data. a neural network of the preconditioning circuit is configured to precondition the write data signal based on a characteristic of a write data path to provide a modified write data signal. the memory further includes a memory array configured to store the write data based on the modified write data signal.
20240412801. TECHNIQUES FOR DETECTING A STATE OF A BUS_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Aaron P. Boehm of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C8/18, G11C29/12, G11C29/14
CPC Code(s): G11C29/42
Abstract: methods, systems, and devices for techniques for detecting a state of a bus are described. a memory device may fail to receive or decode (e.g., successfully receive or successfully decode) an access command transmitted to the memory device via a bus. the bus may enter or remain in an idle state which may cause indeterminate signals to develop on the idle bus. a host device may obtain the indeterminate signals from the idle bus and determine that the indeterminate signals include an error based on a signal that develops on a control line of the idle bus. the signal may be associated with a control signal that indicates errors in a data signal when the control signal has a first voltage, and the control line may be configured to have the first voltage when the bus is idle.
Inventor(s): Qun Su of Boise ID (US) for micron technology, inc., Pitamber Shukla of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/46, G11C29/12
CPC Code(s): G11C29/46
Abstract: exemplary methods, apparatuses, and systems write data to a first wordline of a partially programmed block of memory. a second wordline of the block is determined to fail to satisfy a first margin threshold by comparing a first voltage threshold of the second wordline to a reference voltage. in response to the second wordline failing to satisfy the first margin threshold, a second margin test is applied to the block. in response to determining the block passed the second margin test, data is written in a subsequent write operation to the block using an adjusted trim setting.
20240412805. GLITCH DETECTION REDUNDANCY_simplified_abstract_(micron technology, inc.)
Inventor(s): Angelo Alberto Rovelli of Agrate Brianza (IT) for micron technology, inc., Craig A. Jones of Plano TX (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/02
CPC Code(s): G11C29/52
Abstract: a method can include detecting, by a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. the method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. the method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/3205, H01L23/00, H01L23/528, H01L23/532
CPC Code(s): H01L21/32051
Abstract: a semiconductor device assembly is provided. the semiconductor device assembly includes a first semiconductor die and a second semiconductor die. the first semiconductor die has a first layer of dielectric material and a first conductive pad disposed in a first opening of the first layer of dielectric material. the second semiconductor die has a second layer of dielectric material facing the first layer of dielectric material and a second conductive pad disposed in a second opening of the second layer of dielectric material and corresponding to the first conductive pad. a spacer extends between the first layer of dielectric material and the second layer of dielectric material. a conductive material is disposed between the first conductive pad and the second conductive pad (e.g., through atomic layer deposition (ald)) to implement an interconnect electrically coupling the first semiconductor die and the second semiconductor die.
Inventor(s): Wei Zhou of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/66, H01L21/67, H01L21/78, H01L25/18
CPC Code(s): H01L22/12
Abstract: methods, apparatuses, and systems related to a semiconductor apparatus having one or more dielectric structures used to detect bonding voids during manufacturing. in some embodiments, a semiconductor wafer includes the dielectric structures. after the wafer is bonded to another structure, capacitances may be measured across the dielectric structures and the other wafer. the measured capacitance can be used to detect or characterize any bonding voids that may have been introduced during the wafer bonding process.
Inventor(s): WATARU NOBEHARA of Sagamihara (JP) for micron technology, inc., HARUNOBU KONDO of Sagamihara (JP) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/498, H01L23/528, H01L25/18, H10B80/00
CPC Code(s): H01L25/0657
Abstract: according to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (tsvs). the core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. the first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. the first function circuit and the second function circuit provide the same functions.
Inventor(s): WATARU NOBEHARA of Sagamihara (JP) for micron technology, inc., CHIKARA KONDO of Tokyo (JP) for micron technology, inc.
IPC Code(s): H01L25/065, H10B80/00
CPC Code(s): H01L25/0657
Abstract: according to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (tsvs). the core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. the first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. the first function circuit and the second function circuit provide a logic circuit and a power supply circuit, respectively. the logic circuit receives power from the power supply circuit.
Inventor(s): WATARU NOBEHARA of Sagamihara (JP) for micron technology, inc., CHIKARA KONDO of Tokyo (JP) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/48, H10B80/00
CPC Code(s): H01L25/0657
Abstract: according to one or more embodiments of the disclosure, an apparatus comprises a plurality of core chips that includes a plurality of spiral through-substrate vias (tsvs). the core chips are stacked with one another in a face-to-face manner to define a common channel in first and second core chips, which face each other, of the plurality of core chips. the first core chip and the second core chips include a first function circuit and a second function circuit coupled to the first function circuit, respectively. the first function circuit and the second function circuit provide a first clock divider circuit and a second clock divider circuit, respectively. the first and second clock divider circuits are activated to jointly provide a clock division function.
Inventor(s): Aaron S. Yip of Los Gatos CA (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): H01L25/18, H01L23/00, H01L25/00, H01L25/065
CPC Code(s): H01L25/18
Abstract: a microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. the first die further comprises a first control logic region comprising a first control logic device including at least a word line driver. the microelectronic device further comprises a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. related microelectronic devices, electronic systems, and methods are also described.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Yi Fang Lee of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Ramanathan Gandhi of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc., Sameer Chhajed of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/092, H01L27/12, H01L29/24, H01L29/267, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L27/092
Abstract: some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. the second semiconductor material is a different composition than the first semiconductor material. hydrogen is diffused within the first and second semiconductor materials. the conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. a transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. some embodiments include methods of forming integrated assemblies.
Inventor(s): Takashi Ishihara of Tokyo (JP) for micron technology, inc.
IPC Code(s): H01L29/06, H01L21/762, H01L23/522, H01L29/417, H10B10/00, H10B12/00
CPC Code(s): H01L29/0607
Abstract: a semiconductor device including a substrate; a first active region disposed in the substrate, the first active region having one or more first type channels and a first plurality of doped regions; a second active region disposed in the substrate, the second active region having one or more second type channels and a second plurality of doped regions, the second active region being physically separated from the first active region by a sti region; an intermediate wiring layer disposed above the substrate, the intermediate wiring layer having a plurality of fingers connected to the first plurality of doped regions and the second plurality of doped regions, respectively; and a metal wiring layer having a source finger and a drain finger, wherein the source finger is connected to a first group of the plurality of fingers, and the drain finger is connected to a second group of the plurality of fingers.
Inventor(s): Marco SFORZIN of Boise ID (US) for micron technology, inc., DI HSIEN NGU of Boise ID (US) for micron technology, inc.
IPC Code(s): H03M13/09, H03K19/173, H03M13/11
CPC Code(s): H03M13/098
Abstract: a system and method for memory error detection and recovery in a decoding system in cxl components is presented. the method includes receiving, into a first decoder within the decoding system, a memory transfer block (mtb) having data and parity information, and having a vertical portion and a horizontal portion, performing error detection and correction on the vertical portion of the mtb using binary hamming code logic within the first decoder; and upon performing error detection and correction in the first decoder, then forwarding mtb to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the mtb using a non-binary hamming code logic within the second decoder such that the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the mtb in a serial manner.
Inventor(s): Jiyun Li of Boise ID (US) for micron technology, inc., Toby D. Robbs of Boise ID (US) for micron technology, inc.
IPC Code(s): H03M13/11, H03M13/00
CPC Code(s): H03M13/1105
Abstract: apparatuses and methods for on-device error correction implemented in a memory. a memory may have a first column plane comprising a first number of bit lines and a parity column plane that has a second number of parity bit lines in which the first number is different than the second number. in an access operation, a column select signal may activate the first number of bit lines in the first column plane and the second number of parity bit lines in the second column plane.
Inventor(s): Joseph M. McCrate of Boise ID (US) for micron technology, inc., Nevil Gajera of Boise ID (US) for micron technology, inc., Mohammed Ebrahim Hargan of Boise ID (US) for micron technology, inc.
IPC Code(s): H03M13/15, H03M13/37
CPC Code(s): H03M13/154
Abstract: provided is a memory system comprising a plurality of memory components; and a controller in communication with the plurality of memory components and configured to perform error correction code (ecc) decoding on a received word read from the plurality of memory components. the ecc decoding is configured to (i) detect one or more random errors in a portion of the received word, the portion corresponding to one of the components within the plurality, and (ii) correct the detected random errors; and when the correcting of the detected random errors fails, iteratively marking symbols in the remaining portions of the received word as erasures.
20240414008. MEMORY WRITE ACCESS CONTROL_simplified_abstract_(micron technology, inc.)
Inventor(s): Zhan Liu of San Jose CA (US) for micron technology, inc.
IPC Code(s): H04L9/32, G06F3/06, G06F21/60, H04L9/30
CPC Code(s): H04L9/3247
Abstract: methods, systems, and devices for memory write access control are described. in some examples, memory systems may include storage that is access-protected (e.g., write access protected). to enable access to the protected storage, a server node may communicate a command to the memory system that is signed with a private key that is inaccessible to the memory system. they memory system may verify the command using a public key and may enable access to the protected storage. access commands associated with the protected storage may be processed until access to the protected storage is disabled.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Karthik Sarpatwari of Boise ID (US) for micron technology, inc., Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/50
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. the memory cell includes a first transistor and a second transistor. the first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. the second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. the first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. the first level is between the substrate and the third level. the third data line is electrically coupled to the second channel region and electrically separated from the first channel region.
Micron Technology, Inc. patent applications on December 12th, 2024
- Micron Technology, Inc.
- G02B6/42
- G02B6/12
- G02B6/122
- H01L21/324
- H01L27/06
- H01L31/0232
- H01L31/18
- CPC G02B6/42
- Micron technology, inc.
- G06F3/06
- CPC G06F3/0604
- G06F11/07
- G06F11/10
- CPC G06F3/061
- CPC G06F3/0619
- CPC G06F3/0631
- CPC G06F3/0632
- CPC G06F3/0644
- CPC G06F3/0647
- CPC G06F3/0652
- CPC G06F3/0659
- G11C29/08
- CPC G06F11/1048
- CPC G06F11/1096
- G06F11/30
- B60H1/00
- G06F11/32
- G06F13/16
- CPC G06F11/3089
- G06F12/10
- G06F12/0802
- CPC G06F12/10
- G06F12/1009
- CPC G06F12/1009
- G06F12/1045
- CPC G06F12/1063
- G06F13/42
- CPC G06F13/1642
- G06N3/048
- G06N3/049
- CPC G06N3/048
- G11C7/10
- CPC G11C7/1084
- G11C11/22
- G11C16/34
- CPC G11C11/2275
- G11C11/4072
- G11C5/14
- G11C11/4076
- CPC G11C11/4072
- G11C16/10
- G11C16/26
- CPC G11C16/102
- G11C16/04
- CPC G11C16/26
- G11C16/30
- CPC G11C16/3404
- G11C29/12
- G06F18/214
- G06N20/00
- G11C7/02
- G11C29/14
- G11C29/44
- CPC G11C29/12005
- G11C11/54
- G11C29/36
- CPC G11C29/1201
- G11C29/42
- G11C8/18
- CPC G11C29/42
- G11C29/46
- CPC G11C29/46
- G11C29/52
- G11C29/02
- CPC G11C29/52
- H01L21/3205
- H01L23/00
- H01L23/528
- H01L23/532
- CPC H01L21/32051
- H01L21/66
- H01L21/67
- H01L21/78
- H01L25/18
- CPC H01L22/12
- H01L25/065
- H01L23/498
- H10B80/00
- CPC H01L25/0657
- H01L23/48
- H01L25/00
- CPC H01L25/18
- H01L27/092
- H01L27/12
- H01L29/24
- H01L29/267
- H01L29/423
- H01L29/66
- H01L29/786
- CPC H01L27/092
- H01L29/06
- H01L21/762
- H01L23/522
- H01L29/417
- H10B10/00
- H10B12/00
- CPC H01L29/0607
- H03M13/09
- H03K19/173
- H03M13/11
- CPC H03M13/098
- H03M13/00
- CPC H03M13/1105
- H03M13/15
- H03M13/37
- CPC H03M13/154
- H04L9/32
- G06F21/60
- H04L9/30
- CPC H04L9/3247
- CPC H10B12/50
