Micron Technology, Inc. patent applications on August 8th, 2024
Patent Applications by Micron Technology, Inc. on August 8th, 2024
Micron Technology, Inc.: 38 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (8), G11C29/44 (4), G11C16/26 (4), H10B12/00 (3), H04L9/08 (3) H10B80/00 (2), H10B43/27 (2), G06F3/0659 (2), G06F3/0611 (2), G06F3/0608 (1)
With keywords such as: memory, device, data, material, access, configured, portion, address, cells, and read in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Brian Toronyi of Boulder CO (US) for micron technology, inc., Scheheresade Virani of Frisco TX (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/02, G06F12/1009
CPC Code(s): G06F3/0608
Abstract: an example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. the processing device is configured to receive a memory access request specifying a logical address of a data item and a memory access operation to be performed with respect to the data item; produce a truncated logical address by applying a predefined mathematical transformation to the specified logical address; identifying, in an address translation table, an address translation table entry identified by the truncated logical address; and perform the memory access operation using a physical address specified by the address translation table entry.
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: methods, systems, and devices for improved efficiency for consecutive read operations are described. for example, a memory system may receive a first command indicating a first read operation in a block of memory cells that are each configured to store more than one bit. in response to receiving the first command, the memory system may initiate the performance of the first read operation by applying a voltage to a set of access lines associated with the block of memory cells. the memory system may additionally receive a second read command indicating a second, consecutive read operation in the block of memory cells, where the second command includes an indication to refrain from discharging the set of access lines. here, the memory system may initiate the performance of the second read operation without first discharging the set of access lines after the performance of the first read operation.
20240264746. THERMAL DUPLICATION OF DATA_simplified_abstract_(micron technology, inc.)
Inventor(s): David Aaron PALMER of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: in some implementations, a memory device may detect that data is to be written for a set of temperature profiles. the memory device may write, at respective temperatures corresponding to the set of temperature profiles, multiple copies of the data. the memory device may receive, from a host device, a read request associated with the data. the memory device may detect, based on receiving the read request, a current temperature of the memory device. the memory device may read a copy, from the multiple copies, that is associated with a temperature profile, from the set of temperature profiles, that corresponds to the current temperature of the memory device. the memory device may provide, to the host device, the copy of the data.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/0815
CPC Code(s): G06F3/0619
Abstract: a computing device having a computer express link (cxl) connection between a memory sub-system and a host system and a flag configured to indicate an atomic operation being in progress in the memory sub-system. over the connection, the memory sub-system can attach a portion of its fast, random access memory as a memory device, and a non-volatile memory as a storage device. the flag is set in the memory device accessible to the host system via a cache-coherent memory access protocol, before execution of commands of the atomic operation. after the completion of the atomic operation, the flag is cleared off the memory device. during a recovery from an interruption, the host system can check the flag to decide whether to restart or start the atomic operation again, or undo the partially executed the atomic operation.
Inventor(s): Gianluca COPPOLA of Saviano (IT) for micron technology, inc., Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: in some implementations, a memory device may receive, from a host device, a host configuration that includes an indication of a set of thermal throttling threshold values, wherein the set of thermal throttling threshold values are from a list of sets of valid thermal throttling threshold values. the memory device may send, to the host device, an indication of a set of maximum current consumption values for the memory device, wherein the set of maximum current consumption values is based on the host configuration. the memory device may apply a thermal throttling based on the host configuration.
20240264767. TECHNIQUES FOR DETECTING A STATE OF A BUS_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: methods, systems, and devices for techniques for detecting a state of a bus are described. a memory device may receive an access command transmitted to the memory device via a bus. the memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. the control signal may be transmitted during a first unit interval of a read operation. the control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. the control line may be configured to have or trend toward the first voltage when the bus is in the idle state.
Inventor(s): Yanhua Bi of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for techniques for tagging data based on chunk size are described. generally, the described techniques provide for a device tagging data according to a chunk size of the data. the device may receive a command to write data. the command may include a first indication of a first type of the data (e.g., hot data, cold data). the device may determine whether a size of the data satisfies a threshold based on the command. the device may generate a second indication of a second type of the data based on whether the size of the data satisfies the threshold. the device may write the data to a buffer including a first set of blocks for storing the data in a first type of memory cells based on the second indication of the second type of the data (e.g., hot data, cold data).
Inventor(s): Tao Liu of San Jose CA (US) for micron technology, inc., Zhengang Chen of San Jose CA (US) for micron technology, inc., Ting Luo of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C16/04, G11C16/10, G11C16/26
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for a corrective read of a memory device with reduced latency are described. a memory system may identify a read error based on accessing a memory device, and may select a trim setting for a performing a corrective read operation based on a data retention condition associated with the accessed memory device. such a data retention condition may be associated with a data retention duration, or a cross-temperature condition, among other criteria or combinations thereof. in some implementations, the memory system may select from a subset of possible trim settings, which may be associated with relevant process corners. for example, the memory system may select between a first trim setting that is associated with a relatively large cross-temperature and a relatively short data retention duration and a second trim setting that is associated with a relatively small cross-temperature and a relatively long data retention duration.
Inventor(s): Steven Jeffrey Wallach of Dallas TX (US) for micron technology, inc.
IPC Code(s): G06F9/38, G06F12/0811, G06F12/0831, G06F12/0891, G06F13/20
CPC Code(s): G06F9/3842
Abstract: a cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. the cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. the first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.
20240264904. LOGICAL COUNTERS FOR A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Sai Krishna Mylavarapu of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07, G06F11/14
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for logical counters for a memory system are described. a controller within a memory system may generate one or more logical counters that each correspond to a management counter of a memory die. the controller may store the logical counters at a logical address space associated with the memory system. the logical address space may correspond to a physical location within a memory array of the memory die. the controller may periodically read a value of a management counter and store the value to the logical counter. in some examples, if the memory system detects an error condition for the management counter, the memory system may perform a recovery operation for the data stored at the memory die.
Inventor(s): Amiya Banerjee of Bangalore (IN) for micron technology, inc., Sriraman Sridharan of Hosur (IN) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for read performance improvement using memory device latches are described. a memory system may determine whether a portion of an address mapping table is absent from a cache of one or more controllers and may read the portion of the address mapping table from memory cells of the memory device based on the portion of the address mapping table being absent from the cache. the memory system may communicate, to a memory device, a write command to store the portion of the address mapping table in a set of latches of the memory device based on the address mapping table being associated with an access command that is part of a non-sequential read procedure. the memory system may update a tracking table in the cache to indicate that the portion of the address mapping table is stored in the set of latches.
20240264938. ADDRESS MAP CACHING FOR A MEMORY SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Alex Frolikov of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0802
Abstract: a system having non-volatile media, a volatile memory, and a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media. the non-volatile media has a quantity of memory units and stores an address map that defines logical addresses used in the requests in terms of physical addresses of the memory units in the non-volatile media. the host system has a memory connected to the system via a communication channel. the system has a cache manager that stores a first portion of the address map in the volatile memory of the system and a second portion of the address map in the memory of the host system. in response to an operation that uses a logical address defined in the second portion, the cache manager retrieves the second portion of the address map from the memory.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/0877, G06F12/0815, G06F12/123
CPC Code(s): G06F12/0877
Abstract: a computing device having a computer express link (cxl) connection between a memory sub-system and a host system and having storage access queues configured at least in part in the memory sub-system. the memory sub-system can attach, as a memory device, a portion of its fast random access memory over the connection to the host system. one or more storage access queues can be configured in the memory device. the host system can use a cache-coherent memory access protocol to communicate storage access messages over the connection to the random access memory of the memory sub-system. optionally, the host system can have a memory with second storage access queues usable to access the storage services of the memory sub-system over the connection using a storage access protocol.
Inventor(s): Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Wayne Kinney of Emmett ID (US) for micron technology, inc.
IPC Code(s): G11C11/22, H01L21/28, H01L29/78, H01L29/788, H10B51/30, H10B53/30
CPC Code(s): G11C11/2275
Abstract: some embodiments include a ferroelectric transistor. the transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. metal-containing material is configured as a second container nested within said first container. the second container has a second inner surface with an area less than the first inner surface. ferroelectric material is configured as a third container nested within the second container. the third container has a third inner surface with an area less than the second inner surface. gate material is within the third container. some embodiments include memory arrays having ferroelectric transistors as memory cells. some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (mfmis) transistors.
Inventor(s): Ferdinando Bedeschi of Biassono (MB) (IT) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/404
CPC Code(s): G11C11/4096
Abstract: the present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a p-type transistor and a n-type transistor connected to the p-type transistor, the two-transistor driver being configured to drive a first one of the access lines to a read/program voltage through the two-transistor driver, during a pulse phase and drive a second one of the access lines physically adjacent to the first one of the access lines to a shielding voltage through the two-transistor driver, during the pulse phase.
20240265965. PRE-DECODER CIRCUITRY_simplified_abstract_(micron technology, inc.)
Inventor(s): Vijayakrishna J. Vankayala of Allen TX (US) for micron technology, inc., Hari Giduturi of Folsom CA (US) for micron technology, inc., Jeffrey E. Koelling of Fairview TX (US) for micron technology, inc., Mingdong Cui of Folsom CA (US) for micron technology, inc., Ramachandra Rao Jogu of McKinney TX (US) for micron technology, inc.
IPC Code(s): G11C13/00, H03K19/20
CPC Code(s): G11C13/0023
Abstract: the present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. an embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.
20240265973. ALGORITHM QUALIFIER COMMANDS_simplified_abstract_(micron technology, inc.)
Inventor(s): Anna Chiara Siviero of Albignasego (IT) for micron technology, inc., Umberto Siciliani of Rubano (IT) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/14, G11C16/26, G11C16/34
CPC Code(s): G11C16/102
Abstract: apparatuses, systems, and methods for algorithm qualifier commands are described according to embodiments of the present disclosure. one example method can include executing an algorithm qualifier command on a memory device and performing an operation on the memory device for a command sequence that follows the algorithm qualifier command using a number of settings indicated by the algorithm qualifier command. the algorithm qualifier command can indicate a number of settings to use while performing the operation on the memory device.
Inventor(s): James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Phong Sy Nguyen of Livermore CA (US) for micron technology, inc., Dung Viet Nguyen of San Jose CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, A63B24/00, G11C16/26
CPC Code(s): G11C16/3404
Abstract: a memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. for example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. if the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
Inventor(s): Michael Sheperek of Longmont CO (US) for micron technology, inc., Bruce A. Liikanen of Berthoud CO (US) for micron technology, inc., Steven Michael Kientz of Westminster CO (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C16/16, G11C16/26, G11C29/12, G11C29/44
CPC Code(s): G11C29/42
Abstract: disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. the operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. the operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.
20240265990. APPARATUS WITH CIRCUIT-LOCATING MECHANISM_simplified_abstract_(micron technology, inc.)
Inventor(s): Itamar Lavy of Rockville MD (US) for micron technology, inc., Chunhao Wang of Chantilly VA (US) for micron technology, inc., Wesley B. Butler of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/44, G11C29/04, H01L21/67, H01L23/544
CPC Code(s): G11C29/44
Abstract: an apparatus includes a substrate; circuit components disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer includes one or more section labels for representing physical locations of the circuit components within the apparatus.
20240265991. BIT RETIRING TO MITIGATE BIT ERRORS_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/44, G11C29/12, G11C29/18, G11C29/42
CPC Code(s): G11C29/4401
Abstract: methods, systems, and devices for bit retiring to mitigate bit errors are described. a memory device may retrieve a set of bits from a first row of an address space and may determine that the set of bits includes one or more errors. the memory device may remap at least a portion of the first row from a first row index to a second row index, where the second row index, before the remapping, corresponds to a second row within the address space addressable by the host device. additionally or alternatively, the memory device may receive a first command to access a first logical address of a memory array that is associated with a first row index. the memory device may determine that the first row includes one or more errors and may transmit a signal indicating that the first row includes the one or more errors.
20240265992. SEMICONDUCTOR DEVICE HAVING FUSE ARRAY_simplified_abstract_(micron technology, inc.)
Inventor(s): YASUSHI MATSUBARA of Isehara (JP) for micron technology, inc., MINORU SOMEYA of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C29/00, G11C17/18, G11C29/44
CPC Code(s): G11C29/787
Abstract: an apparatus includes a memory chip including a plurality of fuse units, and a controller chip. each fuse unit includes a fuse array having a plurality of fuse cells, a first register, and a second register. the controller is configured to set the fuse address in the second register included in selected one or more of the plurality of fuse units, set the match signal in the first register included in the selected one or more of the plurality of fuse units, and send a blow signal to the memory chip. each of the selected one or more of the plurality of fuse units is configured to blow one of the plurality of fuse cells selected by the fuse address stored in the second register responsive to the blow signal.
Inventor(s): Brandon P. Wirz of Boise ID (US) for micron technology, inc., Liang Chun Chen of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L21/56, H01L21/48
CPC Code(s): H01L21/56
Abstract: encapsulation warpage reduction for semiconductor die assemblies, and associated methods and systems are disclosed. in one embodiment, a semiconductor die assembly includes an interface die, a stack of semiconductor dies attached to a surface of the interface die, where the stack of semiconductor dies has a first height from the surface. the semiconductor die assembly also includes an encapsulant over the surface and surrounding the stack of semiconductor dies, where the encapsulant includes a sidewall with a first portion extending from the surface to a second height less than the first height and a second portion extending from the second height to the first height. further, the first portion has a first texture and the second portion has a second texture different from the first texture.
Inventor(s): YASUHIRO MAMETSUKA of Hiroshima (JP) for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/528, H01L23/532, H10B12/00
CPC Code(s): H01L21/7682
Abstract: an apparatus includes: first and second conductive pillars in a first layer, each of the first and second conductive pillars including a conductive plug of which a first side surface is covered with a barrier material and a second side surface opposed to the first side surface is coupled to an air-gap free from the barrier material; a wiring in the first layer, the wiring arranged between the first conductive pillar and the second conductive pillar such that a first side surface of the wiring faces to the barrier metal of the first conductive pillar and a second side surface opposed to the first side surface of the wiring faces to the air-gap of the second conductive pillar.
Inventor(s): Zahra Hosseinimakarem of Boise ID (US) for micron technology, inc., Ariela E. Gruszka of Boise ID (US) for micron technology, inc., Mandy W. Fortunati of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/075, G02F1/13357, H01L33/62
CPC Code(s): H01L25/0753
Abstract: embodiments of the present disclosure include apparatuses and method for a stacked light emitting diode (led) hologram display. a stacked led hologram display can include a first array of leds that are configured to emit red light received by a meta-optics panel configured to display a first portion of a holographic image, a second array of leds that are configured to emit green light received by a meta-optics panel configured to display a second portion of a holographic image, and a third array of leds that are configured to emit blue light received by a meta-optics panel configured to display a third portion of a holographic image. the stacked led hologram display can include a number of actuators configured to adjust a position of a first array of leds in first direction and a second direction, adjust a position of a second array of leds in the first direction and the second direction, and adjust a position of a third array of leds in the first direction and the second direction.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc., Lance W. Dover of Fair Oaks CA (US) for micron technology, inc.
IPC Code(s): H04L9/08, H04L61/5007, H04L101/622
CPC Code(s): H04L9/0841
Abstract: disclosed are methods for encrypting communications with a remote endpoint via a memory device. in one embodiment, a memory device is configured to receive, from the application, a request to establish a communications session with a remote computing device, establish a shared symmetric key, the shared symmetric key shared between the memory device and the remote computing device, receive a message from the application, the message including an identifier of the remote computing device and a payload, generate a ciphertext using the symmetric key and the payload, and return the ciphertext to the application.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): H04L9/30, H04L9/08, H04L9/32
CPC Code(s): H04L9/30
Abstract: in some aspects, the techniques described herein relate to a system including: a device identity composition engine (dice) configured to generate asymmetric key pairs for software layers of a computing system; and a secure element (se), the secure element configured to receive requests for accessing the software layers and validating a request for a given software layer by: generating a nonce, providing the nonce and an identifier of the given software layer to the dice, receiving a response from the dice, and validating the response using a public key corresponding to the given software layer to allow access to the given software layer.
Inventor(s): Zhan Liu of Cupertino CA (US) for micron technology, inc.
IPC Code(s): H04L9/32, H04L9/08
CPC Code(s): H04L9/3263
Abstract: in some aspects, the techniques described herein relate to a system including: a remote key management server (rkms); and a computer network communicatively coupled to the rkms, the computer network including: a first computing device a second computing device, and a local key management server (lkms) communicatively coupled to the rkms, the first computing device, and the second computing device, wherein the lkms is configured to: writes a lkms public key to the first computing device using a command signed by the rkms, write a public key of the second computing device to the first computing device using a second command signed using a private key corresponding to the lkms public key.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04N25/60, H04N23/617, H04N23/80, H04N25/78, H04N25/79
CPC Code(s): H04N25/60
Abstract: a method to enhance images, including: receiving, in an image processing logic circuit in an integrated circuit device, first data representative of an input image; generating, by the image processing logic circuit, input data for an inference logic circuit in the integrated circuit device; generating, by the inference logic circuit, a column of bits from the input data; performing, by the inference logic circuit using memory cells in the integrated circuit device having threshold voltages programmed to represent at least one weight matrix, operations of multiplication and accumulation, via reading concurrently rows of the memory cells selected according to the column of bits; generating, by the inference logic circuit, output data based on results of the operations multiplication and accumulation; and generating, by the image processing logic circuit using the output data, second data representative of an output image enhanced from the input image.
20240268077. MEMORY SUB-SYSTEM ENCLOSURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Suresh Reddy Yarragunta of Bangalore (IN) for micron technology, inc., Deepu Narasimiah Subhash of Yeshwanthpu (IN) for micron technology, inc., Ravi Kumar Kollipara of Puppalaguda (IN) for micron technology, inc.
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20409
Abstract: aspects of the present disclosure are directed to a memory sub-system with isothermal cooling of components. a pcb assembly may be secured between a heat spreader and a heat sink that are thermally coupled. the heat sink radiates heat absorbed from both sides of the pcb assembly. by connecting the heat spreader to the heat sink, heat is more effectively transferred from the side of the pcb assembly not directly connected to the heat sink. the pcb assembly may be secured between a top enclosure and a bottom enclosure. the top enclosure and the bottom enclosure may be thermally coupled using a vapor chamber. the vapor chamber pumps heat from a higher-temperature side of the pcb assembly to a lower-temperature side of the pcb assembly. by using the vapor chamber to thermally couple the top and bottom enclosures, creation of hot spots is avoided.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Pankaj Sharma of Boise ID (US) for micron technology, inc., Manuj Nahar of Boise ID (US) for micron technology, inc., Nicholas R. Tapias of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/00
Abstract: some embodiments include apparatuses and methods of forming the apparatuses. one of the apparatuses includes a first conductive region; a second conductive region; a memory cell between the first and second conductive regions and including a first transistor including a first region coupled to the first and second conductive regions, and a charge storage structure separated from the first conduction region, and a second transistor including a second region coupled to the charge storage structure and the second conductive region; and a structure separated from the first region, the charge storage structure, and the second region by a dielectric structure, the structure forming part of a gate of the first transistor and the second transistor, and the structure including a first portion adjacent the dielectric structure, and a second portion adjacent the first portion, wherein the first portion includes a semiconductor material and the second portion includes a conductive material.
Inventor(s): Jordan D. Greenlee of Nampa ID (US) for micron technology, inc., Jieun Lee of Garden City ID (US) for micron technology, inc., Andrea Gotti of Boise ID (US) for micron technology, inc., Kai Yen Lo of Taichung City (TW) for micron technology, inc., David McShannon of Meridian ID (US) for micron technology, inc., Daniel Rave of Boise ID (US) for micron technology, inc., Silvia Borsari of Boise ID (US) for micron technology, inc., Hsiao Wei Liu of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/033
Abstract: a method used in forming an array of capacitors comprises forming a stack comprising sacrificial material and insulative material that is between a top and a bottom of the sacrificial material. the insulative material at least predominately comprises at least one of a silicon nitride, a silicon boronitride, and a silicon carbonitride. horizontally-spaced openings are formed partially through the sacrificial material. a lining is deposited within the horizontally-spaced openings and directly above the sacrificial material. after depositing the lining, the horizontally-spaced openings are extended through remaining of the sacrificial material. the extended horizontally-spaced openings extend through the insulative material. the insulative material with extended horizontally-spaced openings there-through comprises an insulative horizontal lattice. first capacitor electrodes are formed that are individually within individual of the extended horizontally-spaced openings laterally over the lining that is in the extended horizontally-spaced openings. the sacrificial material is removed and forms a capacitor insulator over the first capacitor electrodes and the insulative horizontal lattice. second-capacitor-electrode material is formed over the capacitor insulator. structure independent of method is disclosed
Inventor(s): Amiya Banerjee of Bangalore (IN) for micron technology, inc., Kranthi Kumar Vaidyula of Bangalore (IN) for micron technology, inc., Davide Resnati of Vimercate (IT) for micron technology, inc., Byeung Chul Kim of Boise ID (US) for micron technology, inc., Kyubong Jung of Boise ID (US) for micron technology, inc., Jameer Babasaheb Mulani of Bangalore (IN) for micron technology, inc., Jae Kyu Choi of Boise ID (US) for micron technology, inc., Gianpietro Carnevale of Bottanuco (IT) for micron technology, inc.
IPC Code(s): H10B43/27, H10B43/35
CPC Code(s): H10B43/27
Abstract: a method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. the first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. channel openings are formed through the first and second tiers. charge-storage material is formed in the channel openings through the first and second tiers. the charge-storage material comprises a first charge-trap density. the first charge-trap density of the charge-storage material that is in the first tiers is increased as compared to the charge-storage material that is in the second tiers to a second charge-trap density. channel material is formed in the channel openings through the first and second tiers and that is laterally-inward of the charge-storage material. other embodiment, including structure, are disclosed.
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc., Patrick White of Kuna ID (US) for micron technology, inc., Kevin Y. Titus of Meridian ID (US) for micron technology, inc., Steven P. Turini of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H01L21/02, H01L21/67, H10B43/35, H10B43/40
CPC Code(s): H10B43/27
Abstract: a method used in forming memory circuitry comprises forming a stack where strings of memory cells will be formed and a select-gate region directly above the stack. the stack comprises vertically-alternating different-composition first tiers and second tiers having lower channel openings extending there-through. the select-gate region comprises upper channel openings extending there-through and that are individually directly above and extend to individual of the lower channel openings. storage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. then, insulative charge-passage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. then, channel material is formed simultaneously in the upper and lower channel openings. the storage material is removed from the upper channel openings. after the removing, a select gate is formed in the select-gate region operatively aside the channel material in the select-gate region. other embodiments, including structure, are disclosed.
Inventor(s): Agostino Pirovano of Milano (IT) for micron technology, inc., Lorenzo Fratin of Buccinasco (IT) for micron technology, inc.
IPC Code(s): H10B63/00, G11C13/00
CPC Code(s): H10B63/84
Abstract: methods, systems, and devices for cross point array architecture for multiple decks are described. a memory array may include multiple decks, such as six or eight decks. the memory array may also include sockets for coupling access lines with associated decoders. the sockets may be included in sub-blocks of the array. a sub-block may be configured to include sockets for multiple access lines. a socket may intersect an access line in the middle of the access line, or at an end of the access line. sub-blocks containing sockets for an access line may be separated by a period based on the access line.
Inventor(s): Timothy M. Hollis of Meridian ID (US) for micron technology, inc., Eric J. Stave of Meridian ID (US) for micron technology, inc.
IPC Code(s): H10B80/00, H01L25/065
CPC Code(s): H10B80/00
Abstract: methods, systems, and devices for near memory photonics are described. a memory device may include an optical interface, which may include an array of optical emitters and optical receivers, to convert between electrical signaling and optical signaling. for example, a vertical stack of memory dies may be coupled with an interface component which includes the optical interface. optical signaling may be carried over one or more optical channels to a host device, and the host device may include an optical interface to convert the optical signaling back to electrical signaling. in some examples, the interface component may be positioned above the vertical stack of memory dies. alternatively, the interface component may be positioned below the stack of memory dies, and may extend horizontally beyond the stack of memory dies, forming a porch section. in such cases, the optical interface may be distributed across the porch section.
Inventor(s): See Hiong LEOW of Singapore (SG) for micron technology, inc., Hong Wan NG of Singapore (SG) for micron technology, inc., Chin Hui CHONG of Singapore (SG) for micron technology, inc., Ling PAN of Singapore (SG) for micron technology, inc., Kelvin Aik Boo TAN of Singapore (SG) for micron technology, inc., Seng Kim YE of Singapore (SG) for micron technology, inc.
IPC Code(s): H10B80/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: some implementations described herein are directed to a semiconductor die package including a stacked die arrangement. the semiconductor die package includes one or more legged support structures between respective overhang portions of the stacked die arrangement and a substrate of the semiconductor die package. the one or more legged support structures may reduce a likelihood of the respective overhang portions deflecting during manufacturing of the semiconductor die package. by reducing the likelihood of the overhang portions deflecting, a quality and reliability of the semiconductor die package may be improved.
Inventor(s): Farrell M. Good of Meridian ID (US) for micron technology, inc., Robert K. Grubbs of Boise ID (US) for micron technology, inc., Gurpreet S. Lugani of Boise ID (US) for micron technology, inc.
IPC Code(s): H10N70/00
CPC Code(s): H10N70/063
Abstract: techniques are described to form a liner to protect a material, such as a storage element material, from damage during subsequent operations or phases of a manufacturing process. the liner may be bonded to the material (e.g., a chalcogenide material) using a strong bond or a weak bond. in some cases, a sealant material may be deposited during an etching phase of the manufacturing process to prevent subsequent etching operations from damaging a material that has just been etched.
Micron Technology, Inc. patent applications on August 8th, 2024
- Micron Technology, Inc.
- G06F3/06
- G06F12/02
- G06F12/1009
- CPC G06F3/0608
- Micron technology, inc.
- CPC G06F3/0611
- G06F12/0815
- CPC G06F3/0619
- CPC G06F3/0625
- CPC G06F3/0655
- CPC G06F3/0659
- G11C16/04
- G11C16/10
- G11C16/26
- G06F9/38
- G06F12/0811
- G06F12/0831
- G06F12/0891
- G06F13/20
- CPC G06F9/3842
- G06F11/10
- G06F11/07
- G06F11/14
- CPC G06F11/1068
- CPC G06F12/0246
- G06F12/0802
- CPC G06F12/0802
- G06F12/0877
- G06F12/123
- CPC G06F12/0877
- G11C11/22
- H01L21/28
- H01L29/78
- H01L29/788
- H10B51/30
- H10B53/30
- CPC G11C11/2275
- G11C11/4096
- G11C11/404
- CPC G11C11/4096
- G11C13/00
- H03K19/20
- CPC G11C13/0023
- G11C16/14
- G11C16/34
- CPC G11C16/102
- A63B24/00
- CPC G11C16/3404
- G11C29/42
- G11C16/16
- G11C29/12
- G11C29/44
- CPC G11C29/42
- G11C29/04
- H01L21/67
- H01L23/544
- CPC G11C29/44
- G11C29/18
- CPC G11C29/4401
- G11C29/00
- G11C17/18
- CPC G11C29/787
- H01L21/56
- H01L21/48
- CPC H01L21/56
- H01L21/768
- H01L23/528
- H01L23/532
- H10B12/00
- CPC H01L21/7682
- H01L25/075
- G02F1/13357
- H01L33/62
- CPC H01L25/0753
- H04L9/08
- H04L61/5007
- H04L101/622
- CPC H04L9/0841
- H04L9/30
- H04L9/32
- CPC H04L9/30
- CPC H04L9/3263
- H04N25/60
- H04N23/617
- H04N23/80
- H04N25/78
- H04N25/79
- CPC H04N25/60
- H05K7/20
- CPC H05K7/20409
- CPC H10B12/00
- CPC H10B12/033
- H10B43/27
- H10B43/35
- CPC H10B43/27
- H01L21/02
- H10B43/40
- H10B63/00
- CPC H10B63/84
- H10B80/00
- H01L25/065
- CPC H10B80/00
- H01L25/00
- H01L25/18
- H10N70/00
- CPC H10N70/063
