Micron Technology, Inc. patent applications on August 22nd, 2024
Patent Applications by Micron Technology, Inc. on August 22nd, 2024
Micron Technology, Inc.: 69 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (14), G06F12/02 (8), H10B12/00 (5), H01L23/498 (5), H01L23/00 (5) G06F12/0246 (4), H10B43/27 (2), G06F3/0659 (2), H10B12/485 (2), G06F3/0613 (2)
With keywords such as: memory, data, device, include, read, devices, based, systems, methods, and array in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G02B27/01, G06T19/00, G06V10/82
CPC Code(s): G02B27/017
Abstract: an augmented reality device having a pair of glasses and an artificial neural network partially implemented via a passive neural network and partially implemented via digital circuits. the passive neural network can process image lights representative of a scene in a view of the pair of glasses to generate a light pattern. an array of light sensing pixels can convert the light pattern into data representative of outputs of a first set of artificial neurons of the artificial neural network. a processor can execute instructions to perform computations of a second set of artificial neurons of the artificial neural network responsive to the outputs of the first set of artificial neurons. a digital accelerator can accelerate multiplication and accumulation operations applied on weight matrices of the second set of artificial neurons.
Inventor(s): Agostino Macerola of San Benedetto dei Marsi (IT) for micron technology, inc.
IPC Code(s): G05F1/575, G05F1/56, G05F1/563, G11C5/14
CPC Code(s): G05F1/575
Abstract: an apparatus includes a first switch coupled between a first voltage source and input/output (i/o) circuitry of a memory device, wherein the first voltage source is to supply power to core memory circuitry of the memory device. a second switch is coupled between a second voltage source and the i/o circuitry. control logic is coupled with the first and second switches and to cause the second switch to be activated to permit current to flow from the second voltage source to the i/o circuitry. the control logic, in response to detecting a current draw from the i/o circuitry that satisfies a first threshold criterion, causes the first switch to be activated.
20240281042. THERMAL CONTROL SYSTEM ON CHIP_simplified_abstract_(micron technology, inc.)
Inventor(s): Leon Zlotnik of Camino CA (US) for micron technology, inc.
IPC Code(s): G06F1/20
CPC Code(s): G06F1/206
Abstract: a method includes measuring, by a plurality of thermal sensors coupled to a plurality of circuit portion areas of a memory sub-system, temperature information associated with the plurality of circuit portion areas. the method further includes generating a thermal map based on the measured temperature information associated with the plurality of circuit portion areas and determining, based on the thermal map, that at least one of the circuit portion areas has greater than a threshold probability of experiencing a thermal event. the method further includes operating processing circuitry coupled to the plurality of circuit portion areas to mitigate a thermal load associated with the at least one of the circuit portion areas that has greater than the threshold probability of experiencing the thermal event.
Inventor(s): Patrick A. La Fratta of McKinney TX (US) for micron technology, inc., Robert Walker of Raleigh NC (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: better command scheduling in a memory controller can help improve memory device bandwidth utilization. a method for command scheduling in a memory controller can include processing commands of exclusively a first command type from a command queue including transmitting data in a first direction using a data bus for a first duration. responsive to determining the first duration meets or exceeds a specified time or cycle limit, the bus can be turned around to accommodate transactions or commands of a second type. following the bus turnaround, the method can include processing commands of exclusively a second command type from the command queue including transmitting data in a second direction using the data bus. the time or cycle limit can be statically or dynamically adjusted, for example, based on a read/write mix of commands in the command queue.
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc., Amiya Banerjee of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: methods, systems, and devices for techniques for improving host write performance during data transferring (e.g., folding) are described. a memory system may determine to transfer first data from one or more source data blocks of the memory system to one or more destination data blocks, where the source data blocks and the destination data blocks are associated with one or more memory dies of a set of memory dies of the memory system. the memory system may also receive, from a host system, a command to write second data to a first memory die of the one or more memory dies, and write, concurrent with transferring the first data, the second data to a second memory die of the set of memory dies different than the one or more memory dies based on the transfer of the first data being associated with the first memory die.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: methods, systems, and apparatuses include determining an erase policy for a memory device. an erase operation is selected based on the determined erase policy, where the erase operations include an alternating erase operation and a uniform erase operation. the erase operation is executed on a portion of memory.
20240281148. DYNAMIC ERASE VOLTAGE STEP_simplified_abstract_(micron technology, inc.)
Inventor(s): Jiun-Horng Lai of Kanagawa-ken (JP) for micron technology, inc., Pitamber Shukla of Boise ID (US) for micron technology, inc., Ching-Huang Lu of Fremont CA (US) for micron technology, inc., Chengkuan Yin of Tokyo (JP) for micron technology, inc., Ronit Roneel Prakash of Hiratsuka City (JP) for micron technology, inc., Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: apparatuses, systems, and methods for determining a dynamic erase voltage step. one example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a first erase voltage to a first wordline and a second wordline in the array of memory cells to perform an erase operation, apply a first verify voltage to the first wordline to verify the erase operation, apply a second verify voltage greater than the first verify voltage to the second wordline in response to failing to verify the erase operation by applying the first verify voltage to the first wordline, and apply a second erase voltage to the first wordline and the second wordline in response to verifying the erase operation by applying the second verify voltage to the second wordline.
Inventor(s): William C. Filipiak of Northville MI (US) for micron technology, inc., Elancheren Durai of Boise ID (US) for micron technology, inc., Quincy R. Holton of Kuna ID (US) for micron technology, inc., Adam Satar of Northville MI (US) for micron technology, inc., Brett Hunter of White Lake MI (US) for micron technology, inc., David R. Silwanowicz of Macomb MI (US) for micron technology, inc.
IPC Code(s): G06F3/06, G11C7/04, G11C11/406, G11C16/34
CPC Code(s): G06F3/0619
Abstract: methods, apparatuses and systems related to managing deck-specific read levels are described. the apparatus may include a memory array having the memory cells organized into two or more decks. the apparatus can determine a delay between programming the decks. the apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.
Inventor(s): Angelo della Monica of Aversa (CE) (IT) for micron technology, inc., Luca Dorato of Volla (IT) for micron technology, inc., Claudio Giaccio of Torre del Greco (IT) for micron technology, inc., Massimo Iaculo of San Marco Evangelista (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: a set of simulations of a function to be performed by a computing system is performed. each of the set of simulations are performed according to a distinct hardware/software partition configuration for the computing system. one or more outputs of each simulation of the set of simulations are obtained. the one or more outputs of a respective simulation indicate resources consumed by the computing system based on the respective simulation. an optimal hardware/software partition configuration for the computing system is determined based on the obtained one or more outputs of each simulation of the set of simulations. an indication of the determined optimal hardware/software partition configuration is provided to a processing device to cause the processing device to execute one or more operations associated with the function at the computing system in accordance with the optimal hardware/software partition configuration.
Inventor(s): Christian M. Gyllenskog of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0629
Abstract: methods, systems, and devices for techniques to configure zonal architectures of memory systems are described. in some cases, a host system may control characteristics of zones of a memory system. for example, the host system may transmit a command to the memory system to configure a zone according to a parameter. the parameter may indicate the quantity of bits per cell in memory cells within a zone. in some examples, the parameter may include one or more bits indicating the quantity. upon receiving the command, the memory system may configure the zone in accordance with the parameter. in some examples, the memory system may provide a mapping to the host system indicating the quantity of addresses that a zone may store for each memory cell type.
20240281157. MEMORY SUB-SYSTEM DYNAMIC QOS POOL_simplified_abstract_(micron technology, inc.)
Inventor(s): Abhijit Krishnamoorthy Rao of Bangalore (IN) for micron technology, inc., Ashok Kumar Yadav of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0631
Abstract: a method includes receiving a request for an allocation of memory resources based on quality of service (qos) parameters. the method further includes provisioning, via a qos manager component, a plurality of physical functions to provide the requested allocation of resources. at least two of the plurality of physical functions can be provided to meet a qos criteria.
Inventor(s): Junam Kim of Seoul (KR) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0634
Abstract: methods, systems, and devices for memory system standby mode control are described. a system may be configured to support a memory system transmitting an indication of a duration to a host system in response to receiving a standby indication from the host system. for example, a memory system may determine a set of background operations to be performed at the memory system and, in response to a standby indication, may determine a duration associated with performing at least a subset of the set of background operations. in response to receiving the indication of the duration, the host system may delay an isolation of the memory system from one or more voltage sources, which may include the host system signaling an approval or a different duration to the memory system, during which the memory system may proceed with at least some of the determined set of background operations.
Inventor(s): Amiya Banerjee of Bangalore (IN) for micron technology, inc., Thibash Rajamani Balakrishnan of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: methods, systems, and devices for synchronizing operations between decks of a memory system are described. in some examples, a memory system may determine a pec difference between sister decks of physical blocks of the memory system. a memory system controller may associate the sister decks with respective virtual blocks. the controller may scan each virtual block of the memory system to determine which blocks are to be recycled, and may generate a list of virtual blocks having a vpc that satisfies a first threshold. in some cases, the controller may perform one or more threshold comparisons to determine whether to perform the maintenance operation on the first sister deck or both the first sister deck and the second sister deck.
Inventor(s): Sean S. Eilert of Penryn CA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Justin Eno of El Dorado Hills CA (US) for micron technology, inc., Brian Hirano of Longmont CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: methods, systems, and devices for in-memory associative processing for vectors are described. a device may perform a computational operation on a first set of contiguous bits of a first vector and a first set of contiguous bits of a second vector. the first sets of contiguous bits may be stored in a first plane of a memory die and the computational operation may be based on a truth table for the computational operation. the device may perform a second computational operation on a second set of contiguous bits of the first vector and a second set of contiguous bits of the second vector. the second sets of contiguous bits may be stored in a second plane of the memory die and the computational operation based on the truth table for the computational operation.
Inventor(s): Luca Porzio of Casalnuovo (IT) for micron technology, inc., Rakeshkumar Dayabhai Vaghasiya of Hyderabad (IN) for micron technology, inc., Roberto Izzi of Caserta (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for reliable and efficient boot logical unit access are described. for instance, a memory device may receive a request to write data to a boot logical unit of the memory device. the memory device may update a parameter from a first value to a second value based on receiving the request, the second value indicating a first stage of a procedure for updating the boot logical unit. the memory device may write, to a block of memory in the memory device, the data based on the parameter indicating the first stage of the procedure. additionally or alternatively, the memory device may read a value of the parameter as part of a power up procedure and may perform a boot procedure using either first data at the boot logical unit or second data at the block of memory based on reading the value of the parameter.
Inventor(s): Dmitri A. Yudanov of Rancho Cordova CA (US) for micron technology, inc., Shanky Kumar Jain of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F9/54, G06F12/02, G06F12/0802, G06F12/0873, G06F12/0875, G06F12/0893, G06F12/1045, G11C7/08, G11C7/10, G11C8/08, G11C11/22, G11C11/406, G11C11/4074, G11C11/408, G11C11/4091, G11C11/4096
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices related to write broadcast operations associated with a memory device are described. in one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). the memory device may enable read broadcast operations. a read broadcast may occur from the memory array to multiple locations of the signal development cache, for example via one or more multiplexers.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F7/544, G06F17/16
CPC Code(s): G06F7/5443
Abstract: an apparatus to compute an attention matrix implementing an attention mechanism in artificial neural networks, having: a plurality of memory regions; and a controller configured to receive key value pairs of an attention model, identify a plurality of subsets of the key value pairs to store the plurality of subsets in the plurality of memory regions respectively, and refresh the plurality of memory regions at a plurality of refreshing rates according to representative zero-to-one bit ratios of keys and values stored in the plurality of subsets.
20240281254. OVERLAY CODE RETRIEVAL FROM A HOST SYSTEM_simplified_abstract_(micron technology, inc.)
Inventor(s): Sridhar Prudviraj Gunda of Bangalore (IN) for micron technology, inc., Mani Raghavendra Aravapalli of Hyderabad (IN) for micron technology, inc., Ritesh Tiwari of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30185
Abstract: methods, systems, and devices for overlay code retrieval from a host system are described. a memory system may determine that a set of code for execution by a processor of the memory system is absent from an executable memory of the processor. the memory system may prevent the processor from retrieving the set of code from a non-volatile memory of the memory system based on the set of code being designated for retrieval from a host system. the memory system may retrieve the set of code from a memory of a host system, instead of retrieving the set of code from the non-volatile memory, based on the set of code being designated for retrieval from the host system.
Inventor(s): Binbin HUO of Sauerlach (DE) for micron technology, inc.
IPC Code(s): G06F9/4401
CPC Code(s): G06F9/4408
Abstract: a method includes receiving a first read request during a first boot time. the first read request includes a logical block address and a length. the method also includes tracing the first read request. the method further includes creating a table using the traced first read request. the table includes a sequential record of each traced read request received during the first boot time. the method further includes transmitting the table to a host system during a second boot time. the method further includes receiving a second read request during the second boot time. the second read request includes a logical to physical representation obtained using the table and the logical block address.
Inventor(s): Satheesh Babu MUTHUPANDI of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F9/455, G06F13/40
CPC Code(s): G06F9/45558
Abstract: a system comprises a chassis; a compute express link (cxl) back plane interface mounted within the chassis; a first printed circuit board housed within the chassis and connected to the cxl back plane interface, the first printed circuit board including processing circuitry, switching circuitry and a memory; and a blade server comprising a second printed circuit board housed within the chassis and connected to the cxl back plane interface. the processing circuitry is configured to control the switching circuitry to allocate at least a portion of the memory to the blade server such that a virtual machine provided by the blade server can access the allocated memory through the cxl back plane interface in addition to its own dedicated memory provided by the blade server.
Inventor(s): Pavana Prakash of Houston TX (US) for micron technology, inc., Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Febin Sunny of Folsom CA (US) for micron technology, inc., Saideep Tiku of Fort Collins CO (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5027
Abstract: decomposing an operation can include dividing the operation into a plurality of portions of the operation. a different portion can be provided from the plurality of portions to each group from the plurality of groups of edge devices. the input values can be provided to each of the plurality of groups of edge devices. a plurality of outputs can be received from the plurality of groups of edge devices generated using the input values and the plurality of portions. the plurality of outputs can be recomposed into a single output for the operation.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Febin Sunny of Folsom CA (US) for micron technology, inc., Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F9/50, G06F9/48, G06F15/80
CPC Code(s): G06F9/5033
Abstract: an apparatus having a plurality of accelerators of different types for operations of multiplication and accumulation. in response to a request to perform a task of multiplication and accumulation on input data, the apparatus can analyze the input data to determine characteristics of the input data. the characteristics are indicative of energy efficiency levels of the accelerators in performing the task. the apparatus can assign the task to one of the accelerators based on the characteristics for improved energy efficiency, in addition to balancing workloads for the accelerators. for example, the different types of accelerators can include accelerators configured to perform multiplication and accumulation using microring resonators, synapse memory cells, logical multiply-accumulate units, memristors, etc.
20240281322. VOTING SCHEME IN A MEMORY PAGE_simplified_abstract_(micron technology, inc.)
Inventor(s): Makoto Kitagawa of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: a system for providing a voting scheme in a memory page is disclosed. the system receives a request from a host device for data. the system identifies a memory page of a memory array of a memory device storing data bits corresponding to the requested data. the data bits are transferred from memory cells of the memory page to sense amplifiers to sense the values of the data bits. inversion bits for the row address(es) of the memory page are transferred to a voting circuit to conduct a vote using the inversion bits. if the vote indicates that the data bits are inverted, the system flips the data bits prior to providing the data bits to the host device. if the vote indicates that the data bits are not inverted, the system provide the data bits to the host device without flipping the data bits.
Inventor(s): Deping He of Boise ID (US) for micron technology, inc., Caixia Yang of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1064
Abstract: methods, systems, and devices for critical data management within a memory system are described. a memory system may avoid writing critical data to weak word lines. for example, as part of a media management operation or a host write operation (among other examples), the memory system may determine which data is critical data and may determine which word lines are weak word lines, which may refer to word lines having bit error rates that satisfy a threshold. the memory system may refrain from writing critical data to memory cells coupled with weak word lines, and may instead write non-critical or dummy data to the weak word lines. the memory system may reserve the writing of critical data to memory cells coupled with non-weak word lines, which may refer to word lines having bit error rates that fail to satisfy the threshold.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Scott E. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/14, G06F13/16
CPC Code(s): G06F11/1068
Abstract: a bank of a memory device may be divided into column planes. each column plane may be associated with column selects. in some examples, a portion of a column plane associated with one column select may be used to store metadata associated with data of the remaining column selects. in some examples, both the metadata and the data may be provided to an error correction code circuit as a combined code word that provides error correction for both the data and the metadata.
20240281331. FAST FAILURE RECOVERY OF APPLICATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): David Andrew Roberts of Wellesley MA (US) for micron technology, inc.
IPC Code(s): G06F11/14, G06F9/455, G06F9/50
CPC Code(s): G06F11/1407
Abstract: disclosed in some examples, are methods, systems, and machine-readable mediums in which application state is saved using in-memory versioning in a shared memory pool of disaggregated memory. by utilizing a disaggregated memory pool, the processing resources may be on separate devices than the memory those resources are using. as a result of this architecture, a failure of hardware of processing resources or an application does not necessarily also cause the hardware resources of the memory devices to fail. this allows a standby application executing on standby processing resources to quickly resume execution when a primary application fails by utilizing the memory pool assigned to the primary application in the memory pool.
Inventor(s): Jotiba Koparde of Bangalore (IN) for micron technology, inc., Nicola Colella of Capodrise (IT) for micron technology, inc., Sridhar Prudviraj Gunda of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F11/16, G06F11/07, G06F11/10
CPC Code(s): G06F11/1658
Abstract: methods, systems, and devices for programming failure handling during data folding are described. a memory system may support a non-blocking exception handling process for handling program failures that occur during folding. for example, if a program failure occurs at a given page, the memory system may mark the failed page as storing uncorrectable data (e.g., associated with an uncorrectable error correction code (uecc) error) rather than as being associated with the program failure. based on the marking, the memory system may continue the folding operation, allowing the data to be moved to another page of a physical destination block. after the folding operation is complete, the memory system may replace a failed physical destination block that includes the failed page with a spare block and retire the failed physical destination block.
Inventor(s): Stephen Hanna of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F11/263
CPC Code(s): G06F11/263
Abstract: methods, systems, and devices for improved testing for memory devices using dedicated command and address (ca) channels are described. a memory system associated with the memory devices may include a buffer configured to store a channel select indicator that indicates which ca channel to be utilized for various access commands associated with the memory devices. the memory system may utilize headers to facilitate the data transfers between the associated memory devices and testing system via the indicated ca channel using the buffer. the memory system may detect a select chip enable command on the ca channel and may subsequently store the channel select indicator in the buffer. the memory system may then detect data on the dedicated ca channel and subsequently read the stored channel select indicator from the buffer. the memory system may then erase the channel select indicator from the buffer, after receiving a select chip terminate command.
Inventor(s): Makoto Kitagawa of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F11/273
CPC Code(s): G06F11/2733
Abstract: a memory device can include an array of memory cells comprising groups of memory cells, the groups including at least one redundant group for repairing a defective group. the memory device can include a controller coupled to the array. responsive to receiving a memory access command, the controller can detect whether a defective group is present. if a defect is present, sensing operations are not performed for the defective group. if no defect is present, sensing operations are not performed for the redundant group.
20240281367. ATOMIC WRITE OPERATIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0238
Abstract: methods, systems, and devices for atomic write operations are described. a host system may receive a sequence of data that includes a first set of data and a second set of data. the host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. the host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. the first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses.
Inventor(s): Bryan D. Kerstetter of Kuna ID (US) for micron technology, inc., Donald M. Morgan of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: systems, methods, and apparatuses are provided for periodic and activity-based memory management. a memory management bank can be coupled to a memory management block, wherein the memory management bank includes a plurality of memory banks. each memory bank of the plurality of memory banks includes an activate counter to increment responsive to the memory bank receiving an activate command and circuitry to determine whether a value of the activate counter is equal to or greater than a wear leveling threshold and perform a wear leveling operation on data stored in the memory bank responsive to determining the value of the activate counter is equal to or greater than the wear leveling threshold.
Inventor(s): David Aaron Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F13/16
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for a partitioned cache for random read operations are described. implementations may determine a target compression factor that is used during read operations. larger compression factors may be associated with more frequent penalties, but may allow for a larger high-performance benchmark on a large address range. as described herein, a compression factor may indicate certain mappings that are stored to a volatile memory. the compression factor may be chosen at product design time or may be chosen dynamically at run time based on statistics such as extended cache hit or miss rate. if a read command associated with a logical block address not stored by the volatile memory is received, the memory system may “guess” the physical address by assuming that data was written to the memory system sequentially. if the data is correct, the data may be read out to the host system.
Inventor(s): Luca Porzio of Casalnuovo (IT) for micron technology, inc., Roberto Izzi of Caserta (IT) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F3/06, G06F12/126, G06F13/16
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for usage level identification for memory device addresses are described. systems, techniques, and devices are described herein in which a memory device may determine where to store data according to a level of usage of the data. the memory device may receive a write command indicating data to be written, a type of the data, and a logical address of a memory array for writing the data. the memory device may identify an entry associated with the logical address in a table that maps the logical address to a physical address of the memory array. the entry may include a field configured to maintain a level of usage for the logical address. the memory device may update the level of usage value according to a process and write the data to a physical address of the memory array based on the level of usage value.
Inventor(s): Antonio David Bianco of Boise ID (US) for micron technology, inc., John Paul Traver of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F9/54, G06F12/0891
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for separate cores for media management of a memory sub-system are described. a controller of a memory sub-system can include a first processing core and a second processing core for a garbage collection procedure. the first processing core can perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory sub-system. the second processing core can perform a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure, where the second set of one or more operations are concurrent with the first set of one or more operations.
20240281373. MEMORY SYSTEM HOST DATA RESET FUNCTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Yanhua Bi of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/123
CPC Code(s): G06F12/0253
Abstract: methods, systems, and devices for a memory system host data reset function are described. a reset operation may be performed to reset data in a memory system without erasing host data from the memory system. the memory system and a host system may perform the reset operation to sequentially reorder the data across pages and blocks of the memory system, mitigating holes in the data. the reset operation may enable sequentially reordering the data by performing refresh operations on the blocks and performing a subsequent garbage collection operation to consolidate the data within the pages of the refreshed blocks. the host system may reorganize the logical block addresses associated with the blocks and the memory system may perform the refresh operations and the garbage collection operations. the blocks may be refreshed according to an order of access frequency and according to a measure of performance impact on the memory system.
20240281374. ADDRESS MAPPING TABLE COMPRESSION_simplified_abstract_(micron technology, inc.)
Inventor(s): David Aaron Palmer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/06, G06F12/02
CPC Code(s): G06F12/0646
Abstract: methods, systems, and devices for address mapping table compression are described. a memory system may identify, for a region of an address mapping table, sets of sequentially indexed logical addresses that are mapped to sets of sequentially indexed physical addresses. the memory system may select a compression factor for the region based on the sets of sequentially indexed logical addresses. and the memory system may remove subsets of physical addresses from the sets of sequentially indexed physical addresses in the region based on the compression factor.
Inventor(s): Umberto Siciliani of Rubano (IT) for micron technology, inc., Violante Moschiano of Avezzano (IT) for micron technology, inc., Walter Di Francesco of Avezzano (IT) for micron technology, inc.
IPC Code(s): G06F12/0842, G11C16/04, G11C16/08, G11C16/10, G11C16/24, G11C16/30, G11C16/34
CPC Code(s): G06F12/0842
Abstract: a memory device includes a page buffer with multiple registers and a memory array, configured as single-level cell (slc) memory, including a set of sub-blocks coupled with the page buffer. control logic is operatively coupled with the page buffer and causes a first page of slc data to be stored in the multiple registers. the control logic causes a subsequent page of the slc data to be stored in the multiple registers. the control logic causes the subsequent page and the first page of the slc data stored in the multiple registers to be concurrently programmed to the set of sub-blocks. the control logic causes at least some of the operations for programming the first page and the subsequent page to the set of sub-blocks to be performed in parallel.
Inventor(s): Ritesh Tiwari of Bangalore (IN) for micron technology, inc., Sridhar Prudviraj Gunda of Bangalore (IN) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/1027, G06F12/0873
CPC Code(s): G06F12/1027
Abstract: methods, systems, and devices for buffer expansion for random write operations are described. implementations provide buffer expansion for random write operations used to store l2p address translation table data under certain recognized operation workloads. memory locations within the memory system controller are typically allocated for use during various operations. during different operational workloads, the amount of memory required for each of these different allocated memory areas may vary. by recognizing the entry of the memory system into a workload of random write operations, the memory system controller may expand a buffer size used to store the portion of the l2p address translation table data used during the write operations to retain larger portions of the l2p address translation table in the buffer.
20240281390. MEMORY DEVICE WITH 4N AND 8N DIE STACKS_simplified_abstract_(micron technology, inc.)
Inventor(s): Dong Uk Lee of Boise ID (US) for micron technology, inc., Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc., Lingming Yang of Meridian ID (US) for micron technology, inc., Tyler J. Gomm of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/16
CPC Code(s): G06F13/1678
Abstract: a memory device includes a stack of eight memory dies having an 8n architecture and a stack of four memory dies having a 4n architecture. a first half and a second half of the stack of eight memory dies can each include 32 channels divided equally across the first half of dies and across the second half of dies. banks of each of the 32 channels on the first half of dies can be associated with respective first pseudo channels. banks of each of the 32 channels on the second half of dies can be associated with respective second pseudo channels. the stack of four memory dies can include the 32 channels divided equally amongst the dies, and the banks of each of the 32 channels on the stack of four memory dies can be divided equally across the respective first and second pseudo channels.
20240281399. FRAME PACKING USING STORED TEMPLATES_simplified_abstract_(micron technology, inc.)
Inventor(s): Nikesh AGARWAL of Boise ID (US) for micron technology, inc., Chanda MANJULA LINGANAA of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/42
CPC Code(s): G06F13/4221
Abstract: a method performed by a protocol controller for packing a frame includes selecting, based on current contents of at least one message buffer, a stored packing template, and packing the frame in accordance with the selected packing template. the packing comprises packing each slot of the frame with a respective request (e.g., read request, write request) from the message buffer in accordance with the selected packing template. the template is selected from a plurality of stored packing templates. associated host devices on which the protocol controller is arranged are also described.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Febin Sunny of Folsom CA (US) for micron technology, inc., Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F16/22, G06F16/242
CPC Code(s): G06F16/2282
Abstract: an apparatus to compute an attention matrix implementing an attention mechanism in artificial neural networks, having: memory to store key value pairs; a reorder buffer to provide a reordered list of keys from the key value pairs; an analog dot product accelerator configured to compute dot products of key elements of keys from the reordered list of keys with respective query elements of a query row of a query matrix; a processing device configured to generate, based on results of the dot products, a row of attention scores corresponding to the query row of the query matrix for the reordered list of keys; and a further accelerator configured to compute dot products of segments of the attention scores with value elements of respective segments of values from a list of values from the key value pairs to generate an attention matrix.
Inventor(s): Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Saideep Tiku of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06V10/22, G06T7/00, H04N25/79
CPC Code(s): G06V10/235
Abstract: customization of a deep neural network model to analyze different regions of an image at different machine vision acuity levels. a graphical user interface presents an image captured by an image sensing pixel array and receives user interactions with the image to define regions of the machine vision acuity levels. based on the user interactions with the graphical user interface, a region mask is generated to identify the regions of pixels in the image sensing pixel array. according to the region mask, unnecessary computations of low machine vision acuity are removed from the deep neural network model to generate a customized computing model of analyzing image data, captured by the image sensing pixel array, at the machine vision acuity levels.
Inventor(s): Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Saideep Tiku of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06V10/26, G06T7/00, G06V10/147, G06V10/25, G06V10/44, G06V10/82, H04N23/80
CPC Code(s): G06V10/26
Abstract: different machine vision acuity levels for anomaly detection in an image. an image sensing pixel array generates image data representative of the image having a first region (e.g., focal region) and a second region (e.g. periphery). a memory cell array stores a first weight matrix representative of a first kernel of a convolutional neural network and a second weight matrix representative of a second kernel. a logic circuit can apply the first kernel to the first region using the first weight matrix to generate first feature data at a first stride length with quantization at a first precision level. the logic circuit can apply the second kernel to the second region using the second weight matrix to generate second feature data at a second stride length with quantization at a second precision level.
Inventor(s): Saideep Tiku of Folsom CA (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06V20/20, G06F3/147, G06V10/74, G06V10/82, G06V20/52, G06V40/16, G06V40/20
CPC Code(s): G06V20/20
Abstract: an augment reality security system to identify outliers in behaviors. for example, cameras can be each configured to capture images, compress the images, and provide compressed images having embeddings representative of features determined by an artificial neural network. a server computer can receive, from the plurality of cameras, compressed images to generate analytics of embeddings of features in the compressed images, identify from the analytics an anomaly associated with a first face, and determine metrics representative of features of the first face in an image. a pair of augmented reality glasses can have a computing unit to detect a second face in a view through the glasses, communicate with the server computer to determine a match of the second face with the first face based on the metrics, and generate an augmented reality display in the view to identify the first face.
Inventor(s): Nathaniel J. Meier of Boise ID (US) for micron technology, inc., Michael A. Shore of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/406, G11C11/4076, G11C11/408
CPC Code(s): G11C11/40622
Abstract: apparatuses, systems, and methods for controller directed targeted refresh operations. a memory may be coupled to a controller. the memory may identify aggressor addresses based on sampled addresses. the addresses may be sampled based on internal timing logic of the memory and also based on a sampling command received from the controller. the memory may also receive a controller identified aggressor address from the controller. the memory may refresh one or more victim word lines of the identified (either by the memory or the controller) aggressor addresses as part of a targeted refresh operation. victims of controller identified aggressor addresses may be refreshed before memory identified aggressor addresses.
Inventor(s): Jiyun Li of Boise ID (US) for micron technology, inc., Yuan He of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/56, G11C11/4091, G11C11/4094
CPC Code(s): G11C11/5628
Abstract: memory devices including tri-state memory cells are disclosed. a memory device may include a first tri-state cell that may store a first voltage level that is one of three voltage levels, a second tri-state cell that may store a second voltage level that is one of the three voltage levels, and three input/output lines that may access the memory device. the three input/output lines may carry three respective binary signals based on the first voltage level and the second voltage level. a memory device may include a bank including a number of continuous arrays of tri-state memory cells. each of the tri-state memory cells may be accessible by a respective bit line. groups of the bit lines may be associated with respective column-select lines. the bank may include a number of sub-word-line drivers interspersed between the number of continuous arrays. associated systems and methods are also disclosed.
20240282381. HYBRID DYNAMIC WORD LINE START VOLTAGE_simplified_abstract_(micron technology, inc.)
Inventor(s): Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Kulachet Tanpairoj of San Mateo CA (US) for micron technology, inc., Deping He of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/08
CPC Code(s): G11C16/102
Abstract: methods, systems, and devices for hybrid dwlsv are described. one or more controllers may communicate one or more program commands to a nand memory device. the memory device may perform program operations that correspond to the program commands communicated by the controller. the memory device may perform the program operations using a word line start voltage. once the programming operations are complete, the memory device may communicate the lowest word line starting voltage offset associated with performing the program operations to the one or more controllers.
20240282385. ON-DIE CAPACITOR BANKS_simplified_abstract_(micron technology, inc.)
Inventor(s): Mohammed A. Khan of Boise ID (US) for micron technology, inc., Michael Wagner of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/20, H01L25/065, H01L25/18, H10B80/00
CPC Code(s): G11C16/20
Abstract: a method includes dividing an on-die capacitor of a memory device into a plurality of capacitor banks, charging the plurality of capacitor banks sequentially during an initialization of the memory device, determining a supply voltage for the memory device is below a threshold voltage, and discharging the plurality of capacitor banks sequentially to provide power to the memory device in response to determining the supply voltage is below the threshold voltage.
Inventor(s): Lei Zhang of Singapore (SG) for micron technology, inc., Sampath Ratnam of San Jose CA (US) for micron technology, inc., Steven Michael Kientz of Westminster CO (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/26
CPC Code(s): G11C16/3404
Abstract: various embodiments use a feedback-control loop to track slow charge loss (scl) for a memory cell of a memory device, which can be used to adjust one or more read level voltages used to read data from the memory cell.
Inventor(s): Sridhar Prudviraj Gunda of Bangalore (IN) for micron technology, inc., Thibash Rajamani Balakrishnan of Bangalore (IN) for micron technology, inc., Saurav Pundir of Bangalore (IN) for micron technology, inc., Sunil Singh Dhanik of Bangalore (IN) for micron technology, inc.
IPC Code(s): G11C29/44
CPC Code(s): G11C29/44
Abstract: methods, systems, and devices for efficient performance of error rate detection procedures in a memory system are described. a memory system may determine whether a condition for performing an error rate detection procedure has been satisfied. based on determining that the condition has been satisfied, the memory system may add a request for the error rate detection procedure to a queue. the memory system may then perform the error rate detection procedure indicated by the request in the queue based on determining that access activity from a host system has lapsed for a threshold duration.
Inventor(s): Kyungjin Kim of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C16/26, G11C16/34
CPC Code(s): G11C29/52
Abstract: a request to perform a read operation on a multi-bit memory cell is received. a read operation on a respective page of the multi-bit memory cell is performed for each page of the multi-bit memory cell. whether the respective page is at least one of either a lower logical page (lp) or an upper logical page (up) of the multi-bit memory cell is determined responsive to determining that the read operation on the respective page failed. a read error handling operation on the respective page is performed. a read level associated with a successful read of the respective page is obtained from the read error handling operation. an ordering of a plurality of entries of a read retry data structure associated with the read error handling operation is rearranged based on the obtained read level responsive to determining that the respective page is the lp or up.
20240282400. DIFFERENTIAL STROBE FAULT IDENTIFICATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Paul A. Laberge of Shoreview MN (US) for micron technology, inc.
IPC Code(s): G11C29/52
CPC Code(s): G11C29/52
Abstract: methods, systems, and devices for differential strobe fault indication are described. a memory device may be configured to indicate a fault using a read strobe signal. the read strobe signal may be a read data strobe (rdqs) signal, such as a true rdqs (rdqs_t) signal or a complement rdqs (rdqs_c) signal. in some examples, the memory device may indicate the fault based on a characteristic of the read strobe signal, such as a pattern of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. in some examples, a host device may identify a fault type (e.g., recoverable or unrecoverable) based on a fault signature associated with a given characteristic of the read strobe signal. the host device may perform recovery operations based on the fault type identified.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/74, H01L21/265, H01L21/768, H01L21/8234, H01L23/48, H01L23/498, H01L27/06, H01L29/66, H01L29/78, H10B12/00
CPC Code(s): H01L21/743
Abstract: semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. a top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
Inventor(s): David K. Ovard of Meridian ID (US) for micron technology, inc., Thomas Hein of Munich (DE) for micron technology, inc., Timothy M. Hollis of Meridian ID (US) for micron technology, inc., Walter L. Moden of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/498, H01L23/00
CPC Code(s): H01L23/49838
Abstract: systems may include a central processing unit (cpu), a graphics processing unit (gpu), or a field programmable gate array (fpga), or any combination thereof. at least one memory device may be connected to the cpu, the gpu, or the fpga. the memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. a package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. a ball grid array may be supported on the package substrate. each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.
Inventor(s): Raju Ahmed of Boise ID (US) for micron technology, inc., Radhakrishna Kotti of Boise ID (US) for micron technology, inc., David A. Kewley of Boise ID (US) for micron technology, inc., Dave Pratt of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L23/522, H10B61/00, H10B63/00
CPC Code(s): H01L23/528
Abstract: some embodiments include an integrated assembly having a base which includes first circuitry. memory decks are over the base. each of the memory decks has a sense/access line coupled with the first circuitry. the memory decks and base are vertically spaced from one another by gaps. the gaps alternate in a vertical direction between first gaps and second gaps. overlapping conductive paths extend from the sense/access lines to the first circuitry. the conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. the first and second conductive interconnects are laterally offset relative to one another.
Inventor(s): Kishan Chanumolu of Bengaluru (IN) for micron technology, inc., Sandeep Dwivedi of Bengaluru (IN) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/538, H01L25/00, H01L25/065
CPC Code(s): H01L24/06
Abstract: an apparatus includes a die with a first face, a second face opposite the first face, and a third face located between the first face and the second face, i/o cells coupled to the first face of a die, where the i/o cells are configured to be selectively bonded to a package by wirebonded interconnections at a first pitch or flip-chip interconnections at a second pitch that is larger than the first pitch, and a bond area including decoupling capacitors that is located between each i/o cell and the third face of the die.
Inventor(s): Bharat Bhushan of Taichung (TW) for micron technology, inc., Wei Zhou of Boise ID (US) for micron technology, inc., Debjit Datta of Taichung (TW) for micron technology, inc., Chaiyanan Kulchaisit of Hiroshima (JP) for micron technology, inc., Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Akshay N. Singh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/56, H01L23/29
CPC Code(s): H01L24/08
Abstract: a semiconductor device assembly, including a semiconductor die having a frontside surface, a first plurality of bond pads at the frontside surface and a first dielectric layer at the frontside surface; and an interface die having a frontside surface and a backside surface, the interface die including a second plurality of bond pads and a second dielectric layer disposed on the backside surface of the interface die, a third dielectric layer disposed on the frontside surface of the interface die, wherein the third dielectric layer includes a mechanically altered surface opposite the frontside surface of the interface die, and a redistribution layer disposed on the third dielectric layer and above the frontside surface of the interface die, wherein hybrid bonds are disposed between the frontside surface of the semiconductor die and the backside surface of the interface die.
Inventor(s): Jungbae Lee of Taichung (TW) for micron technology, inc., Bong Woo Choi of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/00, H01L23/498
CPC Code(s): H01L24/10
Abstract: methods, apparatuses, and systems related to a device having a delamination reduction mechanism disposed between a solder resist layer and a contact pad of a substrate. the substrate may include a solder opening in the solder resist layer over the contact pad. the delamination reduction mechanism may have bonding strengths relative to the solder resist layer and the contact pad that are greater than a bonding strength associated with a direct contact between the solder resist layer and the contact pad.
20240282751. SUBSTRATES WITH DOWNSET_simplified_abstract_(micron technology, inc.)
Inventor(s): Ling Pan of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Kelvin Aik Boo Tan of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc., See Hiong Leow of Singapore (SG) for micron technology, inc., Chong C. Hui of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/00, H01L23/498
CPC Code(s): H01L25/0657
Abstract: a variety of applications can include systems with packaged electronic devices having multiple dies arranged on a substrate with a downset design. a substrate with a downset design can include an upper portion and a lower portion with a downset portion connecting the upper portion to the lower portion. the downset portion can include through vias to provide conductive paths between the lower portion and the upper portion. dies can be positioned with a region defined by walls of the downset portion with a non-conductive film covering the dies in the region defined by walls of the downset portion. additional dies can be positioned on the non-conductive film and the upper portion of the substrate. a packaged electronic device having a substrate with a downset design can be implemented to raise the neutral axis of the packaged electronic device to near the top surface of the dies.
Inventor(s): Owen R. Fay of Boise ID (US) for micron technology, inc., Kyle K. Kirby of Eagle ID (US) for micron technology, inc., Akshay N. Singh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L21/56, H01L21/60, H01L23/31, H01L23/498
CPC Code(s): H01L25/0657
Abstract: a semiconductor device assembly can include a first semiconductor device and an interposer. the interposer can include a substrate and through vias in which individual vias include an exposed portion and an embedded portion, the exposed portions projecting from one or both of the first surface and the second surface of the substrate, and the embedded portions extending through at least a portion of the substrate. the interposer can include one or more test pads, a first electrical contact, and a second electrical contact. the semiconductor device assembly can include a controller positioned on an opposite side of the interposer from the first semiconductor device and operably coupled to the interposer via connection to the second electrical contact.
Inventor(s): Yoshitaka Nakamura of Boise ID (US) for micron technology, inc., Yi Fang Lee of Boise ID (US) for micron technology, inc., Jerome A. Imonigie of Boise ID (US) for micron technology, inc., Scott E. Sills of Boise ID (US) for micron technology, inc., Aaron Michael Lowe of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/78, H01L29/08, H01L29/10, H01L29/24, H01L29/417, H01L29/45, H10B12/00
CPC Code(s): H01L29/7827
Abstract: some embodiments include an integrated assembly having an access device between a storage element and a conductive structure. the access device has channel material which includes semiconductor material. the channel material has a first end and an opposing second end, and has a side extending from the first end to the second end. the first end is adjacent the conductive structure, and the second end is adjacent the storage element. conductive gate material is adjacent the side of the channel material. a first domed metal-containing cap is over the conductive structure and under the channel material and/or a second domed metal-containing cap is over the channel material and under the storage element. some embodiments include methods of forming integrated assemblies.
Inventor(s): Zia A. Shafi of Boise ID (US) for micron technology, inc., Luca Laurin of Lissone (IT) for micron technology, inc., Durga P. Panda of Boise ID (US) for micron technology, inc., Sara Vigano´ of Monza (IT) for micron technology, inc.
IPC Code(s): H01L29/78, H01L21/8238, H01L27/092, H01L29/66
CPC Code(s): H01L29/7835
Abstract: some embodiments include an integrated assembly having a first gate operatively adjacent a channel region, a first source/drain region on a first side of the channel region, and a second source/drain region on an opposing second side of the channel region. the first source/drain region is spaced from the channel region by an intervening region. the first and second source/drain regions are gatedly coupled to one another through the channel region. a second gate is adjacent a segment of the intervening region and is spaced from the first gate by an insulative region. a lightly-doped region extends across the intervening region and is under at least a portion of the first source/drain region. some embodiments include methods of forming integrated assemblies.
20240284161. CELLULAR SIGNAL MESH NETWORK_simplified_abstract_(micron technology, inc.)
Inventor(s): Kari Crane of Meridian ID (US) for micron technology, inc., Deepti Verma of Boise ID (US) for micron technology, inc., Shruthi Kumara Vadivel of Boise ID (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., Sue-Fern Ng of Boise ID (US) for micron technology, inc.
IPC Code(s): H04W8/18, H04B17/318, H04W28/18, H04W52/02
CPC Code(s): H04W8/183
Abstract: methods and devices related to a cellular signal mesh network are described. in an example, a method can include determining, via a processing resource of a first computing device, whether a cellular signal of the first computing device is below a threshold cellular signal, transmitting from the first computing device to a second computing device first signaling including data representing a request for operational data of the second computing device in response to determining that the cellular signal of the first computing device is below the threshold cellular signal, receiving from the second computing device second signaling comprising the operational data of the second computing device, and transmitting from the first computing device to the second computing device third signaling including data representing at least one of: a voice call, a video call, or a message in response to receiving the second signaling comprising the operational data.
20240284590. SOLDER MASK FAULT FIBER OPTICS SENSOR_simplified_abstract_(micron technology, inc.)
Inventor(s): Chan H. Yoo of Boise ID (US) for micron technology, inc., James M. Derderian of Boise ID (US) for micron technology, inc., Walter L. Moden of Boise ID (US) for micron technology, inc., Christopher Glancey of Boise ID (US) for micron technology, inc.
IPC Code(s): H05K1/02, G01R31/309, H05K3/28
CPC Code(s): H05K1/0269
Abstract: aspects of the present disclosure configure a processor to detect faults in a printed circuit board (pcb) solder mask using an optical waveguide. the processor directs an optical beam to an input of one or more optical waveguides embedded in a protective coating layer of a pcb, the protective coating layer being adjacent to one or more traces of the pcb. the processor measures a beam characteristic of the optical beam that is output by the one or more optical waveguides. the processor detects a disruption of the optical beam that is output by the one or more optical waveguides based on the beam characteristic. the processor detects a fault in the protective coating layer of the pcb based on detecting the disruption of the optical beam that is output by the one or more optical waveguides.
Inventor(s): Lorenzo Fratin of Buccinasco (MI) (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C11/408, G11C11/4094
CPC Code(s): H10B12/485
Abstract: methods, systems, and devices for lateral split digit line memory architectures are described. a memory array may include a first set of word line plates separated from a second set of word line plates by a pillar (e.g., that is configured as a digit line) that interact with the first and second set of word line plates. further, the memory array may include a set of dielectric piers that are positioned between the pillars, where each dielectric pier contacts a first pillar and a second pillar. additionally, the memory array may include a set of storage elements and a set of digit lines that are each coupled with a word line plate, a pillar, and a dielectric material that is positioned between each first and second pillar of the pairs of pillars.
Inventor(s): Lorenzo Fratin of Buccinasco (MI) (IT) for micron technology, inc., Paolo Fantini of Vimercate (MB) (IT) for micron technology, inc., Enrico Varesi of Milano (MI) (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C5/06, G11C5/10, G11C11/408
CPC Code(s): H10B12/485
Abstract: methods, systems, and devices for split pillar and pier memory architectures are described. a memory array may include a first set of word line plates separated from a second set of word line plates by a trench and a set of pairs of pillars (e.g., that are configured as digit lines) that interact with the first and second set of word line plates. further, the memory array may include a set of dielectric piers that are positioned between the pairs of pillars, where each dielectric pier contacts a first pillar from a first pair and a second pillar from a second pair. additionally, the memory array may include a set of storage elements that are each coupled with a word line plate, a pillar, and a dielectric material that is positioned between each first and second pillar of the pairs of pillars.
20240284663. ASYMMETRIC TRANSISTOR DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Srinivas Pulugurtha of Boise ID (US) for micron technology, inc., Dan Mihai Mocuta of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, G11C11/4091
CPC Code(s): H10B12/50
Abstract: a variety of applications can include an apparatus having one or more pairs of transistors sharing a common source region that provide asymmetric transistor devices. the drains of the transistors of a pair sharing a common source region can be structured with the source junction depth being shallower than the drain junction depth of the drain region of at least one of the transistors of the pair. tilted implantation can be used to extend a drain junction depth beyond the distance of the source junction depth by implanting additional dopants. the extension of the drain junction depth can be accomplished without additional masks being used in processing to dope only a drain region and skip doping on a corresponding source region.
Inventor(s): David H. Wells of Boise ID (US) for micron technology, inc., Matthew J. King of Boise ID (US) for micron technology, inc., Indra V. Chary of Boise ID (US) for micron technology, inc., Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc., Lifang Xu of Boise ID (US) for micron technology, inc., Paolo Tessariol of Arcore (MB) (IT) for micron technology, inc., Shuangqiang Luo of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: methods, systems, and devices for merged cavities for conductor formation in a memory die are described. an array of cavities may be formed through a stack of material layers of a memory die, and conductors may be formed at least in part by merging some of the cavities of the array. such cavities may be sized in accordance with a relatively smallest feature that implements a subset of such cavities, and a smallest associated feature may be formed using a first subset of the array of cavities. conductors may be formed at least in part by merging two or more cavities of a second subset of the array of cavities using a material removal operation to remove portions of the stack of material layers. such merging may support conductors being formed with a cross-section that is greater than a cross-section of other features formed using such cavities that are not merged.
Inventor(s): Albert Fayrushin of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Chris M. Carlson of Nampa ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: a microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. at least one pillar, comprising a channel material, extends through the stack structure. a source region, below the stack structure, comprises a doped material. a vertical extension of the doped material protrudes upward to an interface with the channel material at elevation within the stack structure (e.g., an elevation proximate or laterally overlapping in elevation at least one source-side gidl region). the microelectronic device structure may be formed by a method that includes forming a lateral opening through cell materials of the pillar, recessing the channel material to form a vertical recess, and forming the doped material in the vertical recess. additional microelectronic devices are also disclosed, as are related methods and electronic systems.
Micron Technology, Inc. patent applications on August 22nd, 2024
- Micron Technology, Inc.
- G02B27/01
- G06T19/00
- G06V10/82
- CPC G02B27/017
- Micron technology, inc.
- G05F1/575
- G05F1/56
- G05F1/563
- G11C5/14
- CPC G05F1/575
- G06F1/20
- CPC G06F1/206
- G06F3/06
- CPC G06F3/0611
- CPC G06F3/0613
- CPC G06F3/0619
- G11C7/04
- G11C11/406
- G11C16/34
- CPC G06F3/0625
- CPC G06F3/0629
- CPC G06F3/0631
- CPC G06F3/0634
- CPC G06F3/064
- CPC G06F3/0655
- CPC G06F3/0659
- G06F9/54
- G06F12/02
- G06F12/0802
- G06F12/0873
- G06F12/0875
- G06F12/0893
- G06F12/1045
- G11C7/08
- G11C7/10
- G11C8/08
- G11C11/22
- G11C11/4074
- G11C11/408
- G11C11/4091
- G11C11/4096
- G06F7/544
- G06F17/16
- CPC G06F7/5443
- G06F9/30
- CPC G06F9/30185
- G06F9/4401
- CPC G06F9/4408
- G06F9/455
- G06F13/40
- CPC G06F9/45558
- G06F9/50
- CPC G06F9/5027
- G06F9/48
- G06F15/80
- CPC G06F9/5033
- G06F11/10
- CPC G06F11/1004
- G06F11/07
- CPC G06F11/1064
- G06F11/14
- G06F13/16
- CPC G06F11/1068
- CPC G06F11/1407
- G06F11/16
- CPC G06F11/1658
- G06F11/263
- CPC G06F11/263
- G06F11/273
- CPC G06F11/2733
- CPC G06F12/0238
- CPC G06F12/0246
- G06F12/126
- G06F12/0891
- G06F12/123
- CPC G06F12/0253
- G06F12/06
- CPC G06F12/0646
- G06F12/0842
- G11C16/04
- G11C16/08
- G11C16/10
- G11C16/24
- G11C16/30
- CPC G06F12/0842
- G06F12/1027
- CPC G06F12/1027
- CPC G06F13/1678
- G06F13/42
- CPC G06F13/4221
- G06F16/22
- G06F16/242
- CPC G06F16/2282
- G06V10/22
- G06T7/00
- H04N25/79
- CPC G06V10/235
- G06V10/26
- G06V10/147
- G06V10/25
- G06V10/44
- H04N23/80
- CPC G06V10/26
- G06V20/20
- G06F3/147
- G06V10/74
- G06V20/52
- G06V40/16
- G06V40/20
- CPC G06V20/20
- G11C11/4076
- CPC G11C11/40622
- G11C11/56
- G11C11/4094
- CPC G11C11/5628
- CPC G11C16/102
- G11C16/20
- H01L25/065
- H01L25/18
- H10B80/00
- CPC G11C16/20
- G11C16/26
- CPC G11C16/3404
- G11C29/44
- CPC G11C29/44
- G11C29/52
- CPC G11C29/52
- H01L21/74
- H01L21/265
- H01L21/768
- H01L21/8234
- H01L23/48
- H01L23/498
- H01L27/06
- H01L29/66
- H01L29/78
- H10B12/00
- CPC H01L21/743
- H01L23/00
- CPC H01L23/49838
- H01L23/528
- H01L23/522
- H10B61/00
- H10B63/00
- CPC H01L23/528
- H01L23/538
- H01L25/00
- CPC H01L24/06
- H01L21/56
- H01L23/29
- CPC H01L24/08
- CPC H01L24/10
- CPC H01L25/0657
- H01L21/60
- H01L23/31
- H01L29/08
- H01L29/10
- H01L29/24
- H01L29/417
- H01L29/45
- CPC H01L29/7827
- H01L21/8238
- H01L27/092
- CPC H01L29/7835
- H04W8/18
- H04B17/318
- H04W28/18
- H04W52/02
- CPC H04W8/183
- H05K1/02
- G01R31/309
- H05K3/28
- CPC H05K1/0269
- CPC H10B12/485
- G11C5/06
- G11C5/10
- CPC H10B12/50
- H10B43/27
- H10B43/10
- CPC H10B43/27
- H10B41/10
- H10B41/27
