Micron Technology, Inc. patent applications on August 1st, 2024
Patent Applications by Micron Technology, Inc. on August 1st, 2024
Micron Technology, Inc.: 40 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (12), H01L23/00 (4), G11C5/06 (3), H01L23/528 (3), H01L25/18 (3) G06F3/0659 (2), G06F3/0611 (2), G06F12/0802 (2), G01R31/2851 (1), G11C11/221 (1)
With keywords such as: memory, device, data, die, dies, coupled, methods, include, conductive, and systems in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Jihye Gale Shin of Palo Alto CA (US) for micron technology, inc., Kazuaki Ohara of Sunnyvale CA (US) for micron technology, inc., Rachael R. Skreen of Meridian CA (US) for micron technology, inc., Soujanya Venigalla of Newark CA (US) for micron technology, inc., Rosa Maria Avila-Hernandez of Boise ID (US) for micron technology, inc.
IPC Code(s): G01R31/28
CPC Code(s): G01R31/2851
Abstract: methods, systems, and devices for memory device operation are described. a register of a first memory die of multiple memory dies in a memory device may be configured to indicate that the first memory die has a first characteristic associated with a first set of performance criteria. also, a register of a second memory die of the multiple memory dies may be configured to indicate that the second memory die has a second characteristic associated with a second set of performance criteria. data received from a host device that is associated with the first set of performance criteria may be stored in the first memory die based on the first memory die having the first characteristic associated with the first set of performance criteria. in some examples, the registers store relative characteristics of the memory dies in relation to the other memory dies in the memory device.
Inventor(s): Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G01S7/41, G01S13/86, G01S13/89
CPC Code(s): G01S7/417
Abstract: systems, devices, and methods related to a radar and an artificial neural network are described. for example, the radar can have at least one processing unit configured to execute instructions implementing matrix computation of the artificial neural network. the artificial neural network is configured to identify features in the radar image in an output responsive to an input containing a radar image. optionally, the radar can further include an image sensor to generate an optical image as part of the input to artificial neural network. instead of outputting the radar images and/or the optical images, the radar may output a description of the features identified via the artificial neural network from the radar image.
Inventor(s): Donghua Zhou of Suzhou City (CN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: methods, systems, and apparatuses include receiving a current free space value and a historic delta value. a delta value is calculated using the current free space value, a target free space value, and the historic delta value. a delta region is determined using the delta value. a new host rate is calculated using the determined delta region, the calculated delta value, and the historic delta value. the new host rate is sent to a host device causing the host device to change a current host rate to the new host rate.
Inventor(s): Amit Bhardwaj of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the plurality of memory planes, to perform operations that include, identifying a first block residing on a memory plane of the memory device, wherein the first block is associated with an error condition; and responsive to identifying the first block, performing an error recovery operation to replace the first block with a second block, wherein the second block resides on the memory plane.
Inventor(s): Haibo Li of Cupertino CA (US) for micron technology, inc., Xiangyu Tang of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: a memory device of a first array of memory cells configured as quad-level cell (qlc) memory or penta-level cell (plc) memory and including one or more first planes. a second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. the first and second sets of memory cells are associated with a shared wordline. the control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.
20240256142. MANAGING PARTIALLY PROGRAMMED BLOCKS_simplified_abstract_(micron technology, inc.)
Inventor(s): Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Pitamber Shukla of San Jose CA (US) for micron technology, inc., Zhongyuan Lu of Boise ID (US) for micron technology, inc., Niccolo' Righetti of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: methods, systems, and devices for managing partially programmed blocks are described. based on writing data stored in a first block to a second block, a determination of whether to program the first block into a fully programmed state may be made based on whether the first block is storing the data in the partially programmed state. based on determining whether to program the first block, the first block may be maintained in the fully programmed state until an erase operation is performed for the first block.
20240256145. SCAN FRAGMENTATION IN MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc., Christopher M. Smitchger of Boise ID (US) for micron technology, inc., Saeed Sharifi Tehrani of San Diego CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0616
Abstract: a memory system includes a memory device and a processing device, operatively coupled to the memory device. the processing device performs operations comprising: identifying one or more mandatory scan wordlines of the memory device and one or more remaining wordlines of the memory device; performing a plurality of scan iterations with respect to a plurality of pages of the memory device, such that performing each scan iteration comprises: identifying, among the remaining wordlines, one or more scheduled scan wordlines of the memory device, scanning a subset of pages of the memory device that are addressable by the mandatory scan wordlines and the scheduled scan wordlines; wherein a combination of a first plurality of pages addressable by the scheduled scan wordlines selected by the plurality of scan iterations and a second plurality of pages addressable by the mandatory wordlines comprises the plurality of pages of the memory device.
20240256152. MEMORY CHANNEL CONTROLLER OPERATION_simplified_abstract_(micron technology, inc.)
Inventor(s): David G. Springberg of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0622
Abstract: the present disclosure includes systems, apparatuses, and methods related to memory channel controller operation. for example, a data type associated with an access request may be determined. the access request may be executed by utilizing, responsive to determining the access request is associated with a first data type, a first memory channel controller coupled to a first memory device to access a first memory address range, associated with the first data type, allocated to the first memory device. the access request may be executed by utilizing, responsive to determining the access request is associated with a second data type, the first memory channel controller and a second memory channel controller coupled to a second memory device to access a second memory address range, associated with the second data type, allocated among the first memory device and the second memory device.
Inventor(s): Yu-Chung LIEN of San Jose CA (US) for micron technology, inc., Ching-Huang LU of Fremont CA (US) for micron technology, inc., Zhenming ZHOU of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0625
Abstract: in some implementations, a memory device may detect a read command associated with reading data stored by the memory device. the memory device may determine whether the read command is from a host device in communication with the memory device. the memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. the memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.
Inventor(s): Glen E. Hush of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0626
Abstract: methods, systems, and devices related to sense amplifiers of a memory device serving as a static random access memory (sram) resource. for example, a memory array of a memory device can be coupled to sense amplifiers. the sense amplifiers can be electrically disconnected from digit lines of the memory array. data can be stored in the sense amplifiers. the data can be communicated from the sense amplifiers to a processing device external to the memory array and the sense amplifiers. the sense amplifiers can receive data from the processing device and, when electrically disconnected from the number of digit lines, store the received data.
Inventor(s): Jihye Gale Shin of Palo Alto CA (US) for micron technology, inc., Kazuaki Ohara of Sunnyvale CA (US) for micron technology, inc., Rachael R. Skreen of Meridian CA (US) for micron technology, inc., Soujanya Venigalla of Newark CA (US) for micron technology, inc., Rosa Maria Avila-Hernandez of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0634
Abstract: methods, systems, and devices for memory device configuration based on host behavior are described. a first memory die of multiple memory dies in a memory device may be programmed to have a first characteristic associated with a first set of performance criteria. based on programming the first memory die to have the first characteristic, data associated with the first set of performance criteria may be received. based on the data being associated with the first set of performance criteria, the data may be stored in the first memory die based on the first memory die having the first characteristics associated with the first set of performance criteria.
20240256187. TEMPERATURE MONITORING FOR MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Aaron P. Boehm of Boise ID (US) for micron technology, inc., Todd Jackson Plum of Boise ID (US) for micron technology, inc., Scott D. Van De Graaff of Boise ID (US) for micron technology, inc., Scott E. Schaefer of Boise ID (US) for micron technology, inc., Mark D. Ingram of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for temperature monitoring for memory devices are described for monitoring one or more temperature ranges experienced by a memory device. the memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more temperature ranges. the memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. the indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. the host device may use information included in the indication to perform an operation associated with the memory device.
Inventor(s): Hari Giduturi of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a memory system can include a stack of memory dies such as including a primary die and two or more secondary dies. the primary die can communicate with an external host device and with the secondary dies. in an example, the primary die can issue a command to the secondary dies using a first command message that includes an opcode field specifying a memory operation, a first chip identification field specifying a selected first die of the secondary dies, and one or more operands. in an example, each of the secondary dies receives the same first command message.
Inventor(s): Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc.
IPC Code(s): G06F9/48
CPC Code(s): G06F9/485
Abstract: methods, systems, and apparatuses mitigate a stall condition in an iterative bit flipping decoder. a codeword is received and current bit is selected. in response to detecting the risk of the stall condition and further in response to determining the current bit satisfies the bit flipping criterion, it is determined that the current bit was flipped in a previous iteration. the flipping of the current bit is bypassed in response to determining the current bit was flipped in the previous iteration.
Inventor(s): Jay Sarkar of San Jose CA (US) for micron technology, inc., Ipsita Ghosh of New Garia, Kolkata (IN) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/0784
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations including selecting sample data residing in the memory device; running a test on the sample data regarding a set of error-handling operations; and generating log data comprising a first order of the set of error-handling operations to be performed on data residing in a segment of the memory device.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1004
Abstract: apparatuses, systems, and methods for bounded fault compliant metadata storage. memory devices include a first data terminal and a second data terminal. as part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. the two locations may be remote from each other.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1076
Abstract: apparatuses, systems, and methods for bounded fault compliant metadata storage. memory devices include a first data terminal and a second data terminal. as part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. the two locations may be remote from each other.
Inventor(s): Zhongguang Xu of San Jose CA (US) for micron technology, inc., Guang Hu of Mountain View CA (US) for micron technology, inc., Xianganfg Luo of Fremont CA (US) for micron technology, inc., Jung Sheng Hoei of Newark CA (US) for micron technology, inc., Ting Luo of Santa Clara CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc., Jianmin Huang of San Carlos CA (US) for micron technology, inc.
IPC Code(s): G06F12/06
CPC Code(s): G06F12/0607
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to generate virtual or superblocks using multiple partial good blocks. the controller identifies a first partial good block (pgb) in a set of memory components, the first pgb having first subset of word line groups (wgrs) that are categorized as being non-defective. the controller searches for a second pgb in the set of memory components having a second subset of wgrs that are categorized as being non-defective. the controller computes a total quantity of wgrs based on the first quantity of wgrs in the first subset of wgrs and a second quantity of wgrs in the second subset of wgrs and, in response, combines the first pgb and the second pgb to form an individual virtual block.
Inventor(s): Peter L. Brown of Eagle ID (US) for micron technology, inc., Glen E. Hush of Boise ID (US) for micron technology, inc., Troy A. Manning of Meridian ID (US) for micron technology, inc., Timothy P. Finkbeiner of Boise ID (US) for micron technology, inc., Troy D. Larsen of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F12/0802
CPC Code(s): G06F12/0802
Abstract: methods, systems, and devices related to sense amplifiers of a memory device serving as a static random access memory (sram) cache. for example, a memory array can be coupled to sense amplifiers. in a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. in the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. in the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. in a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.
Inventor(s): David Boles of Austin TX (US) for micron technology, inc.
IPC Code(s): G06F12/0802, G06F3/06
CPC Code(s): G06F12/0802
Abstract: systems, methods, and computer readable media for tracking memory deltas at a cache line granularity. the method includes receiving a base address for a physical memory region, receiving a list of empty log memory buffers associated with a delta logging session, and responsive to determining that a cache line associated with the physical memory region may be in a modified state, storing the modified cache line and metadata associated with the modified cache line in an active log memory buffer referenced by the list of empty log memory buffers. the method also includes determining that the active log memory buffer is full and appending a flag to the active log memory buffer, thereby marking the active log memory buffer as a full log memory buffer. the method also includes storing a list of full log memory buffers, wherein the list is visible to a host processor.
Inventor(s): Amit Bhardwaj of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F12/10, G06F12/02
CPC Code(s): G06F12/10
Abstract: disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (lbas), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an lba associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available lba within the first zone to the first physical memory block, and storing the data in the first physical memory block.
20240256473. NEUROMORPHIC MEMORY DEVICE AND METHOD_simplified_abstract_(micron technology, inc.)
Inventor(s): Brent Keeth of Boise ID (US) for micron technology, inc., Frank F Ross of Boise ID (US) for micron technology, inc., Richard C Murphy of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F13/16, G06N3/004, H01L25/065, H01L25/18
CPC Code(s): G06F13/1668
Abstract: apparatus and methods are disclosed, including memory devices and systems. example memory devices, systems and methods include a stack of memory dies, a controller die, and a buffer. example memory devices, systems and methods include one or more neuromorphic layers logically coupled between one or more dies in the stack of memory dies and a host interface of the controller die.
Inventor(s): Fa-Long Luo of San Jose CA (US) for micron technology, inc., Tamara Schmitz of Scotts Valley CA (US) for micron technology, inc., Jeremy Chritz of Seattle WA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): G06N3/08, G06N3/04, G06N3/045, H04W4/02, H04W4/38, H04W4/40, H04W4/90
CPC Code(s): G06N3/08
Abstract: systems, methods, and apparatuses related to cooperative learning neural networks are described. cooperative learning neural networks may include neural networks which utilize sensor data received wirelessly from at least one other wireless communication device to train the neural network. for example, cooperative learning neural networks described herein may be used to develop weights which are associated with objects or conditions at one device and which may be transmitted to a second device, where they may be used to train the second device to react to such objects or conditions. the disclosed features may be used in various contexts, including machine-type communication, machine-to-machine communication, device-to-device communication, and the like. the disclosed techniques may be employed in a wireless (e.g., cellular) communication system, which may operate according to various standardized protocols.
Inventor(s): Parth Khopkar of Seattle WA (US) for micron technology, inc., Shakti Nagnath Wadekar of West Lafayette IN (US) for micron technology, inc., Abhishek Chaurasia of Redmond WA (US) for micron technology, inc., Andre Xian Ming Chang of Bellevue WA (US) for micron technology, inc.
IPC Code(s): G06V20/58, G06V10/82
CPC Code(s): G06V20/58
Abstract: methods, systems, and devices for techniques to implement transformers with multi-task neural networks are described. a vehicle system may employ one or more transformer models in a machine learning system to generate an indication of a one or more objects in an image, one or more drivable areas in an image, one or more lane lines in an image, or a combination thereof. the multi-task system may include a feature extractor which uses a set of convolutional layers to generate a corresponding set of representation vectors of the image. the system may pass the representation vectors to a set of transformer models, such that each of the transformer models share a common input. each transformer model may use the representation vectors to generate a respective indication.
Inventor(s): Fuad Badrieh of Boise ID (US) for micron technology, inc., Thomas H. Kinsley of () for micron technology, inc., Baekkyu Choi of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C5/06, G06F13/16, G11C11/22, G11C11/408, G11C11/4091, G11C11/56
CPC Code(s): G11C5/063
Abstract: methods and devices for dynamic allocation of a capacitive component in a memory device are described. a memory device may include one or more voltage rails for distributing supply voltages to a memory die. a memory device may include a capacitive component that may be dynamically coupled to a voltage rail based on an identification of an operating condition on the memory die, such as a voltage droop on the voltage rail. the capacitive component may be dynamically coupled with the voltage rail to maintain the supply voltage on the voltage rail during periods of high demand. the capacitive component may be dynamically switched between voltage rails during operation of the memory device based on operating conditions associated with the voltage rails.
Inventor(s): Tomoharu Tanaka of Yokohama (JP) for micron technology, inc., Yoshihiko Kamata of Yokohama (JP) for micron technology, inc., Yoshiaki Fukuzumi of Yokohama (JP) for micron technology, inc.
IPC Code(s): G11C5/14, G11C5/06, G11C11/4074
CPC Code(s): G11C5/145
Abstract: a memory device includes an array of strings of memory cells, a local bitline coupled with a plurality of the strings of memory cells, and a sense transistor having a gate terminal coupled with the local bitline. the memory device further includes a series of transistors have a data read path between a source line and the sense transistor and between the sense transistor and a global bitline that is coupled with a page buffer. a micropump is integrated within the series of transistors. control logic is coupled with the series of transistors and to, during a read operation of a memory cell of the array and in response to the sense transistor turning on, activate the micropump to cause a constant read current to flow between the global bitline and the source line.
20240257855. MEMORY CELL SENSING ARCHITECTURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Daniele Vimercati of El Dorado Hills CA (US) for micron technology, inc., Eric Carman of San Francisco CA (US) for micron technology, inc.
IPC Code(s): G11C11/22, G11C5/06, G11C5/10
CPC Code(s): G11C11/221
Abstract: techniques and configurations for electronic memory are described. an apparatus may include a first set of memory cells coupled with a first plate line and a word line, where a memory cell in the first set of memory cells may be coupled with a first bit line, and a second set of memory cells coupled with a second plate line and the word line, where a memory cell of the second set of memory cells may be coupled with a second bit line. the apparatus may also include a sense component having a first node coupled with the first bit line and a first capacitor and a second node coupled with the second bit line and a second capacitor. also, a set of capacitors may be coupled with both nodes. the capacitors may support adjustment of the voltage of the nodes of the sense component.
Inventor(s): Richard T. Housley of Boise ID (US) for micron technology, inc., Quinn L. Roberts of Boise ID (US) for micron technology, inc., Shruthi Kumara Vadivel of Boise ID (US) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc., Tien Minh Quan Tran of Singapore (SG) for micron technology, inc., Zhen Feng Yow of Singapore (SG) for micron technology, inc., Wei Deng Leong of Singapore (SG) for micron technology, inc., Kah Sing Chooi of Singapore (SG) for micron technology, inc., Nils Monserud of Half Moon Bay CA (US) for micron technology, inc.
IPC Code(s): G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): G11C16/0483
Abstract: a method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers of different compositions relative one another. the stack extends from individual die areas to and across scribe-line area that is between immediately-adjacent of the individual die areas. a registration mark is formed in the scribe-line area. the registration mark comprises parallel first bars atop the stack having first spaces therebetween. a masking material is directly above the stack, the first bars, and the first spaces. the masking material comprises parallel second bars having second spaces therebetween. the second spaces individually have width that is less than width of individual of the second bars. some of the masking material is spaced laterally-outward of the second bars. vertical thickness of the some masking material that is laterally-outward of the second bars have a vertical thickness laterally-outward of the first spaces that is greater than vertical thickness of the second bars. ratio of the vertical thickness of the some masking material that is laterally-outward of the second bars divided by the width of the second bars is 6.0 to 9.6. after forming the registration mark, the first bars and the first and second tiers in the scribe-line area are cut through to form individual die that individually comprise one of the individual die areas. other embodiments, including structure independent of method, are disclosed.
Inventor(s): Tawalin Opastrakoon of Boise ID (US) for micron technology, inc., Renato C. Padilla of Folsom CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of San Jose CA (US) for micron technology, inc., Sampath K. Ratnam of Boise ID (US) for micron technology, inc., Michael G. Miller of Boise ID (US) for micron technology, inc., Gary F. Besinga of San Jose CA (US) for micron technology, inc., Christopher M. Smitchger of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/26
CPC Code(s): G11C16/3468
Abstract: a configuration setting manager of a memory device receives a request to perform an adjustment operation on one or more configuration setting values of the memory device; calculate one or more updated configuration setting values by applying a multiplier value to the one or more configuration setting values based on a configuration adjustment definition associated with the one or more configuration setting values, wherein the multiplier value is associated with a number of memory operations performed on the memory device; and store the one or more updated configuration setting values to one or more corresponding configuration registers.
Inventor(s): Eleuterio Mannella of L'Aquila (IT) for micron technology, inc., Massimo Rossini of Rome (IT) for micron technology, inc.
IPC Code(s): G11C29/38, G06F1/04, G06F1/26
CPC Code(s): G11C29/38
Abstract: a memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. the power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. the power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.
Inventor(s): Trupti D. Gawai of Boise ID (US) for micron technology, inc., David S. Pratt of Meridian ID (US) for micron technology, inc., Ahmed M. Elsied of Boise ID (US) for micron technology, inc., David A. Kewley of Boise ID (US) for micron technology, inc., Dale W. Collins of Boise ID (US) for micron technology, inc., Raju Ahmed of Boise ID (US) for micron technology, inc., Chelsea M. Jordan of Boise ID (US) for micron technology, inc., Radhakrishna Kotti of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/522, H01L23/528
CPC Code(s): H01L21/76883
Abstract: methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. in some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. the method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.
20240258233. STAIRCASE LANDING PADS VIA RIVETS_simplified_abstract_(micron technology, inc.)
Inventor(s): Yiping Wang of Boise ID (US) for micron technology, inc., Harsh Narendrakumar Jain of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L21/28, H01L21/311, H01L21/768
CPC Code(s): H01L23/528
Abstract: methods, systems, and devices for staircase landing pads via rivets are described. a memory device may include a staircase region with a stack of materials that includes a set of word lines, where the set of word lines progressively decrease in length to form a staircase structure. the staircase region may additionally include a rivet that couples a first word line from the set of word lines with a conductive pillar. additionally, the conductive pillar may traverse the stack perpendicularly to the set of word lines and may couple the first word line with supporting circuitry. in some cases, a first thickness of the first word line adjacent to the conductive pillar may be greater than a second thickness of other word lines adjacent to the conductive pillar. the staircase region may additionally include an oxide material that isolates the conductive pillar from the other word lines.
Inventor(s): Jong Sik Paek of Taichung (TW) for micron technology, inc.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/768, H01L23/00, H01L23/31, H01L23/498, H01L25/10
CPC Code(s): H01L23/5386
Abstract: stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. in some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. the dielectric structure includes openings corresponding to the bond pads. the module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. the semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.
Inventor(s): Joanna Nassar of Cupertino CA (US) for micron technology, inc.
IPC Code(s): H01L23/544, H01L21/82
CPC Code(s): H01L23/544
Abstract: a method for mechanical self-alignment and slip-resistance in bonding semiconductor substrates is provided. the method includes providing a first semiconductor substrate with a first surface and a second semiconductor substrate with a second surface. next, the method includes etching a first mechanical alignment structure into the first surface and then etching a second mechanical alignment structure into the second surface, such that the first and second mechanical alignment structures are topographically inverse. what follows is optically aligning the first substrate to the second substrate, such that the first and second surface face one another, and then bringing the substrate surfaces into contact. next, the substrates mechanically self-align, such that the topographically inverse structures inter-fit. finally, the method includes bonding both substrates, such that planar bonding regions form between the surfaces and slanted bonding regions form between the mechanical alignment structures.
Inventor(s): Travis M. Jensen of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/05
Abstract: an apparatus comprising a substrate having conductive traces and associated integral terminal pads on a surface thereof, the terminal pads having an irregular surface topography formed in a thickness of a single material of the conductive traces and integral terminal pads. solder balls may be bonded to the terminal pads, and one or more microelectronic components operably coupled to conductive traces of the substrate on a side thereof opposite the terminal pads. methods of fabricating terminal pads on a substrate, and electronic systems including substrates having such terminal pads are also disclosed.
Inventor(s): Blaine J. Thurgood of Nampa ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, G11C5/04, H01L23/00, H01L25/00, H01L25/18
CPC Code(s): H01L25/0652
Abstract: a semiconductor device assembly is provided. the assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. the first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75%, or even more of an area of the package substrate.
20240260171. CROSSTALK CANCELLATION FOR SIGNAL LINES_simplified_abstract_(micron technology, inc.)
Inventor(s): M. Ataul Karim of Boise ID (US) for micron technology, inc., David K. Ovard of Meridian ID (US) for micron technology, inc., Aparna U. Limaye of Boise ID (US) for micron technology, inc., Timothy M. Hollis of Meridian ID (US) for micron technology, inc.
IPC Code(s): H05K1/02, H04B3/32, H04B3/487
CPC Code(s): H05K1/0233
Abstract: methods, systems, and devices for crosstalk cancellation for signal lines are described. in some examples, a device (e.g., a host device or a memory device) may generate a first signal and may invert the first signal to obtain an inverted first signal. the device may obtain a second signal based on attenuating a first range of frequencies of the inverted first signal and a second range of frequencies of the inverted first signal, where the first range of frequencies is below a first threshold frequency and the second range of frequencies is above a second threshold frequency that is greater than the first threshold frequency. the device may transmit the first signal via a first signal line of a set of signal lines and the second signal line via a second signal line of the set of signal lines.
Inventor(s): Dong Wan Kim of Boise ID (US) for micron technology, inc., Russell A. Benson of Boise ID (US) for micron technology, inc., Byung Yoon Kim of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/053
Abstract: a method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. a channel region is between the one and the another source/drain regions. a conductive gate is operatively proximate the channel region. the conductive gate comprises part of one of a plurality of conductive-gate lines in a substrate. lines of conductive material are formed directly above and directly against individual of the one and another source/drain regions. individual of the lines of the conductive material are between immediately-laterally-adjacent of the conductive-gate lines. the lines of the conductive material directly above the another source/drain regions are etched through to form islands of the conductive material that are individually directly above and directly against the individual one source/drain regions. storage elements are formed that are individually electrically coupled to individual of the one source/drain regions through individual of the islands of the conductive material. other embodiments, including structure, are disclosed.
Inventor(s): Kamal M. Karda of Boise ID (US) for micron technology, inc., Haitao Liu of Boise ID (US) for micron technology, inc., Si-Woo Lee of Boise ID (US) for micron technology, inc., Chandra Mouli of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, H01L23/528, H01L29/423
CPC Code(s): H10B12/33
Abstract: methods, apparatuses, and systems related to a memory device having transistor body contacts that extend vertically across stacked circuit layers and connect to body portions of data access transistors are described. a memory device may include storage cells and corresponding access circuits on each of the stacked layers. the vertically extending transistor body contacts may provide a route for leakage away from data storage circuits when the data access transistors are off.
Inventor(s): Wen Wei LUM of Singapore (SG) for micron technology, inc., Kelvin Aik Boo TAN of Singapore (SG) for micron technology, inc., Seng Kim YE of Singapore (SG) for micron technology, inc.
IPC Code(s): H10B80/00, H01L21/48, H01L23/00, H01L23/498, H01L25/00, H01L25/18
CPC Code(s): H10B80/00
Abstract: implementations described herein relate to various semiconductor device assemblies. in some implementations, a molded memory device may include multiple stacked nand dies electrically coupled to one another via multiple wire bonds. the molded memory device may include a molded casing surrounding the multiple stacked nand dies and encapsulating the multiple wire bonds, with the molded casing including a first mold surrounding a first portion of a first nand die, of the multiple stacked nand dies, and a second mold partially surrounding a second portion of the first nand die and each additional nand die, of the multiple nand dies. the molded memory device may include multiple copper contacts configured to couple the molded memory device to a substrate associated with a system in package, with the plurality of copper contacts being disposed in the first mold.
Micron Technology, Inc. patent applications on August 1st, 2024
- Micron Technology, Inc.
- G01R31/28
- CPC G01R31/2851
- Micron technology, inc.
- G01S7/41
- G01S13/86
- G01S13/89
- CPC G01S7/417
- G06F3/06
- CPC G06F3/0608
- CPC G06F3/0611
- CPC G06F3/0613
- CPC G06F3/0616
- CPC G06F3/0622
- CPC G06F3/0625
- CPC G06F3/0626
- CPC G06F3/0634
- CPC G06F3/0659
- G06F9/48
- CPC G06F9/485
- G06F11/07
- CPC G06F11/0784
- G06F11/10
- CPC G06F11/1004
- CPC G06F11/1076
- G06F12/06
- CPC G06F12/0607
- G06F12/0802
- CPC G06F12/0802
- G06F12/10
- G06F12/02
- CPC G06F12/10
- G06F13/16
- G06N3/004
- H01L25/065
- H01L25/18
- CPC G06F13/1668
- G06N3/08
- G06N3/04
- G06N3/045
- H04W4/02
- H04W4/38
- H04W4/40
- H04W4/90
- CPC G06N3/08
- G06V20/58
- G06V10/82
- CPC G06V20/58
- G11C5/06
- G11C11/22
- G11C11/408
- G11C11/4091
- G11C11/56
- CPC G11C5/063
- G11C5/14
- G11C11/4074
- CPC G11C5/145
- G11C5/10
- CPC G11C11/221
- G11C16/04
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- CPC G11C16/0483
- G11C16/34
- G11C16/10
- G11C16/26
- CPC G11C16/3468
- G11C29/38
- G06F1/04
- G06F1/26
- CPC G11C29/38
- H01L21/768
- H01L23/522
- H01L23/528
- CPC H01L21/76883
- H01L21/28
- H01L21/311
- CPC H01L23/528
- H01L23/538
- H01L21/48
- H01L21/56
- H01L23/00
- H01L23/31
- H01L23/498
- H01L25/10
- CPC H01L23/5386
- H01L23/544
- H01L21/82
- CPC H01L23/544
- CPC H01L24/05
- G11C5/04
- H01L25/00
- CPC H01L25/0652
- H05K1/02
- H04B3/32
- H04B3/487
- CPC H05K1/0233
- H10B12/00
- CPC H10B12/053
- H01L29/423
- CPC H10B12/33
- H10B80/00
- CPC H10B80/00
