Micron Technology, Inc. patent applications on April 18th, 2024
Patent Applications by Micron Technology, Inc. on April 18th, 2024
Micron Technology, Inc.: 35 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (10), H01L33/32 (6), H10B41/27 (5), H10B43/27 (4), H01L33/62 (4)
With keywords such as: memory, device, command, material, data, semiconductor, cells, include, region, and methods in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Jean-Sebastien Materne Lehn of Boise ID (US) for micron technology, inc.
IPC Code(s): C23C16/455, C01B32/05, C23C16/26
Abstract: methods, systems, and devices for depositing carbon conducting films by atomic layer deposition are described. for instance, a device may react a first precursor with a base material to form a carbon compound on a material, where the first precursor is an acetylene, a diacetylene, a tri-acetylene, a polyacetylene, an alkene, or an arene and includes at least one germanium, silicon, or tin. additionally, the device may react a second, carbon-containing precursor with the carbon compound to form a layer on the base material.
20240125851.MULTI-MODAL MEMORY APPARATUSES AND SYSTEMS_simplified_abstract_(micron technology, inc.)
Inventor(s): Kenneth M. Curewitz of Plymouth MA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc., John D. Porter of Boise ID (US) for micron technology, inc., Bryce D. Cook of Boise ID (US) for micron technology, inc., Jeffrey P. Wright of Boise ID (US) for micron technology, inc.
IPC Code(s): G01R31/319, G01R31/3185
Abstract: a memory controller and a physical interface layer may accommodate multiple memory types. in some examples, the memory controller and/or phy may include a register that includes operating parameters for multiple operating modes. different operating modes may be compatible with different memory types. in some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. the system may provide multiple interfaces for communicating with the memory. the different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.
Inventor(s): Chung-Yi Lee of Boise ID (US) for micron technology, inc., Reha M. Bafrali of Mountain View CA (US) for micron technology, inc.
IPC Code(s): G03F1/38, G03F1/36, G03F7/00
Abstract: some embodiments include a reticle which includes first pattern features and second pattern features. a first optimal dose of actinic radiation is associated with the first pattern features and a second optimal dose of the actinic radiation is associated with the second pattern features. the second pattern features are larger than the first pattern features. each of the second pattern features has a configuration which includes a central region laterally surrounded by an outer region, with the central region being of different opacity than the outer region. the configurations of the second pattern features balance the second optimal dose of the actinic radiation to be within about 5% of the first optimal dose of the actinic radiation. some embodiments include photo-processing methods.
20240126434.SPEED BINS TO SUPPORT MEMORY COMPATIBILITY_simplified_abstract_(micron technology, inc.)
Inventor(s): Eric V. Pohlmann of Boise ID (US) for micron technology, inc., Neal J. Koyle of Nampa ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for speed bins to support memory compatibility are described. a host device may read a value of a register including serial presence detect data of a memory module. the serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. the host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. the timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.
Inventor(s): Emanuele Confalonieri of Segrate (IT) for micron technology, inc., Antonino Caprí of Bergamo (IT) for micron technology, inc., Nicola Del Gatto of Cassina de' Pecchi (IT) for micron technology, inc., Federica Cresci of Milan (IT) for micron technology, inc., Massimiliano Turconi of Gorgonzola MI (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: an apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. the plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent ras channels (e.g., channels for independent ras accesses). data received at the memory controller via different memory channels of one ras channel can be aligned at various circuits and/or components of the memory controller.
20240126447.ADDRESS VERIFICATION AT A MEMORY DEVICE_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: methods, systems, and devices for address verification at a memory device are described. the memory device may receive a read command for a read address. based on the read command, the memory device may read data from the read address and a first set of error detection bits that is based on a write address associated with the data. the memory device may generate, based on the first set of error detection bits and a second set of error detection bits that is based on the read address, an address match signal that indicates whether the read address matches the write address. and the memory device may provide the data and an indication of the address match signal to a host device.
20240126448.ADAPTIVE READ DISTURB SCAN_simplified_abstract_(micron technology, inc.)
Inventor(s): Animesh R. Chowdhury of Boise ID (US) for micron technology, inc., Kishore K. Muchherla of San Jose CA (US) for micron technology, inc., Nicola Ciocchini of Boise ID (US) for micron technology, inc., Akira Goda of Setagaya (JP) for micron technology, inc., Jung Sheng Hoei of Newark CA (US) for micron technology, inc., Niccolo' Righetti of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: apparatuses, systems, and methods for adapting a read disturb scan. one example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.
Inventor(s): Qi Dong of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: apparatuses, systems, and methods for buffer threshold monitoring to reduce data loss are provided herein. in a number of embodiments of the present disclosure, a method can include buffering data in a first memory device, writing the buffered data from the first memory device to a second memory device, determining that the first memory device is storing at least a threshold amount of data, and sending a first signal to the second memory device in response to determining that the first memory device is storing at least the threshold amount of data, wherein the first signal causes the second memory device to enter an increased write performance mode.
Inventor(s): Steven R. Narum of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: one or more data items is received by a processing device managing one or more memory devices partitioned into a plurality of die partitions. the one or more data items is determined to be written sequentially to one or more blocks within a die partition of the plurality of die partitions. metadata associated with the one or more data items is written sequentially to one or more blocks across the plurality of die partitions.
20240126476.ACTIVATE INFORMATION ON PRECEDING COMMAND_simplified_abstract_(micron technology, inc.)
Inventor(s): John David Porter of Boise ID (US) for micron technology, inc., Bryan David Kerstetter of Kuna ID (US) for micron technology, inc., Kwang-Ho Cho of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a method and a device is provided for utilizing unused valid (v) bits residing on a previous command to transmit additional activate information to a memory device. additional activate information may be transmitted to the memory device without increasing the trcd time, or increasing the command/address (ca) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
20240126477.READ DATA ALIGNMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Yu-Sheng Hsu of San Jose CA (US) for micron technology, inc., Chihching Chen of Milpitas CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: systems, apparatuses, and methods related to a controller architecture for read data alignment are described. an example method can include sending a first notification from a physical layer to each of a number of memory controllers, wherein the first notification indicates that the physical layer and/or a memory device coupled to the physical layer is busy, and blocking commands on each of the number of memory controllers in response to receiving the first notification to cause read data alignment. the method can also include sending a second notification from the physical layer to each of the number of memory controllers, wherein the second notification indicates that the physical layer and/or the memory device coupled to the physical layer is no longer busy, and resuming processing commands on each of the number of memory controllers in response to receiving the second notification.
Inventor(s): Jason Duong of Milpitas CA (US) for micron technology, inc., Fangfang Zhu of San Jose CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Juane Li of Milpitas CA (US) for micron technology, inc., Chih-Kuo Kao of Fremont CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
Abstract: a system can include a memory device and a processing device coupled with the memory device. the processing device can receive, from a host system, a command of a type; determine a weighted count of the command according to the type of the command; track, based on the weighted count, a first count of commands of the type; determine whether the first count of commands of the type satisfies a threshold criterion for commands of the type; and responsive to determining that the first count of commands of the type satisfies the threshold criterion, transmit a notification to the host system to refrain from transmitting commands of the type.
20240126685.DYNAMIC VOLTAGE SUPPLY FOR MEMORY CIRCUIT_simplified_abstract_(micron technology, inc.)
Inventor(s): Hua Tan of Shanghai (CN) for micron technology, inc., Junjun Wang of Shanghai (CN) for micron technology, inc., De Hua Guo of Shanghai (CN) for micron technology, inc.
IPC Code(s): G06F12/02
Abstract: methods, systems, and devices for dynamic voltage supply for memory circuit are described. an apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. an apparatus may include a memory array and a controller. the controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. the controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. the controller may determine a second temperature is greater than a second temperature threshold at a second time. the controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.
Inventor(s): Kishore Kumar Muchherla of Fremont CA (US) for micron technology, inc., Peter Feeley of Boise ID (US) for micron technology, inc., Ashutosh Malshe of Fremont CA (US) for micron technology, inc., Daniel J. Hubbard of Boise ID (US) for micron technology, inc., Christopher S. Hale of Boise ID (US) for micron technology, inc., Kevin R. Brandt of Boise ID (US) for micron technology, inc., Sampath K. Ratnam of Boise ID (US) for micron technology, inc., Yun Li of Fremont CA (US) for micron technology, inc., Marc S. Hamilton of Eagle ID (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F3/06, G06F12/00, G06F12/06, G06F12/0891
Abstract: a memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.
Inventor(s): Evan C. Pearson of Boise ID (US) for micron technology, inc., John H. Gentry of Boise ID (US) for micron technology, inc., Michael J. Scott of Boise ID (US) for micron technology, inc., Greg S. Gatlin of Mountain Home ID (US) for micron technology, inc., Lael H. Matthews of Meridian ID (US) for micron technology, inc., Anthony M. Geidl of Boise ID (US) for micron technology, inc., Michael Roth of Boise ID (US) for micron technology, inc., Markus H. Geiger of Boise ID (US) for micron technology, inc., Dale H. Hiscock of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/06, G06F11/07, G11C11/407, G11C29/04, H01L25/065
Abstract: memory devices and systems with post-packaging master die selection, and associated methods, are disclosed herein. in one embodiment, a memory device includes a plurality of memory dies. each memory die of the plurality includes a command/address decoder. the command/address decoders are configured to receive command and address signals from external contacts of the memory device. the command/address decoders are also configured, when enabled, to decode the command and address signals and transmit the decoded command and address signals to every other memory die of the plurality. each memory die further includes circuitry configured to enable, or disable, or both individual command/address decoders of the plurality of memory dies. in some embodiments, the circuitry can enable a command/address decoder of a memory die of the plurality after the plurality of memory dies are packaged into a memory device.
Inventor(s): Paul Philip Grahek of Boise ID (US) for micron technology, inc., Jacob Walter Rice of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C7/10
Abstract: a method and a device is provided for implementing a mode register to transmit additional activate information to a memory device. additional activate information may be transmitted to the memory device without increasing the trcd time, or increasing the command/address (ca) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
20240127877.DIFFERENTIAL STORAGE IN MEMORY ARRAYS_simplified_abstract_(micron technology, inc.)
Inventor(s): Durai Vishak Nirmal Ramaswamy of Boise ID (US) for micron technology, inc., Giorgio Servalli of Fara Gera d'Adda (IT) for micron technology, inc., Angelo Visconti of Appiano Gentile (IT) for micron technology, inc., Marcello Mariani of Milano (IT) for micron technology, inc., Alessandro Calderoni of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/22, G11C7/06
Abstract: methods, systems, and devices for differential storage in memory arrays are described. a memory device may include pairs of memory cells configured to store a single logic state (e.g., a single bit of information). additionally, the memory device may include sense amplifiers configured to sense the logic state based on a difference between a voltage of a first ferroelectric memory cell of the pair of memory cells and a voltage of a second ferroelectric memory cell of the pair of memory cells. in one example, the memory device may include pairs of memory cells within a single memory array on a single level. here, each memory cell pair may include a memory cells that are each coupled with a same word line and plate line. additionally, each memory cell pair may include memory cells each coupled with different digit lines.
Inventor(s): Vamsi Rayaprolu of San Jose CA (US) for micron technology, inc., Ashutosh Malshe of Fremont CA (US) for micron technology, inc., Gary Besinga of Boise ID (US) for micron technology, inc., Roy Leonard of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/10, G11C16/16, G11C16/26, G11C16/32
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations comprising determining a data validity metric value with respect to a set of memory cells of the memory device; responsive to determining that the data validity metric value satisfies a first threshold criterion, performing a data integrity check on the set of memory cells to obtain a data integrity metric value; and responsive to determining that the data integrity metric value satisfies a second threshold criterion, performing an error handling operation on the data stored on the set of memory cells to generate corrected data.
Inventor(s): Daniel S. Miller of Boise ID (US) for micron technology, inc., Yoshinori Fujiwara of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/46, G11C29/12, G11C29/44
Abstract: methods, apparatuses, and systems related to masking of self-test results are described. a memory device may include a self-test circuit that is configured to selectively suspend collection of test results from one or more portions of a self-test when a temperature of the memory device exceeds a temperature threshold.
Inventor(s): Scott E. SCHAEFER of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/46, G11C7/10, G11C29/12, G11C29/44
Abstract: implementations described herein relate to performing a memory built-in self-test and indicating a status of the memory built-in self-test. a memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. the memory device may identify, based on the one or more bits, that the memory built-in self-test is enabled. the memory device may set a dmi bit of the memory device to a first value and perform the memory built-in self-test based on identifying that the memory built-in self-test is enabled. the memory device may set the dmi bit of the memory device to a second value based on a completion of the memory built-in self-test.
Inventor(s): YUTAKA NAKAE of Hiroshima (JP) for micron technology, inc., NOBUYUKI NAKAMURA of Hiroshima (JP) for micron technology, inc.
IPC Code(s): H01L23/48, H01L21/306, H01L21/324, H01L21/48, H01L23/00
Abstract: according to one or more embodiments of the disclosure, a through-silicon via (tsv)-bump structure is provide. the tsv-bump structure comprises a tsv in a semiconductor substrate and a bump on the tsv. the bump includes a conductive plug portion and a step structure portion under the conductive plug portion. the step structure is configured to electrically couple the tsv and the conductive plug portion with each other.
Inventor(s): Hong Wan Ng of Singapore (SG) for micron technology, inc., Chin Hui Chong of Singapore (SG) for micron technology, inc., Hem P. Takiar of Fremont CA (US) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc., Kelvin Tan Aik Boo of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/48, H01L23/498, H01L27/08
Abstract: substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. in one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. the first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. the first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. the first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
Inventor(s): Chin Hui CHONG of Singapore (SG) for micron technology, inc., Seng Kim YE of Singapore (SG) for micron technology, inc., Hong Wan NG of Singapore (SG) for micron technology, inc., Kelvin Aik Boo TAN of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L23/498, H01L21/48, H01L23/00, H01L25/00, H01L25/065
Abstract: implementations described herein relate to various semiconductor device assemblies. in some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.
20240128189.ANTIFUSE DEVICE HAVING INTERCONNECT JUMPER_simplified_abstract_(micron technology, inc.)
Inventor(s): Christopher G. Wieduwilt of Boise ID (US) for micron technology, inc., James S. Rehmeyer of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L23/528, H01L27/112, H01L29/86
Abstract: an antifuse device, including a gate having a gate dielectric layer; a first doping region connected to a first end of the gate; a second doping region connected to a second end of the gate, the second end being opposite to the first end of the gate; a channel that is disposed under the gate and that connects the first doping region and the second doping region; and an interconnection jumper that electrically connects the first doping region and the second doping region.
Inventor(s): Martin Jared Barclay of Middleton ID (US) for micron technology, inc., Mark Tunik of Portland OR (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L21/768, H01L23/535, H10B20/00, H10B41/10, H10B41/27, H10B41/50, H10B43/10, H10B43/27, H10B43/50
Abstract: disclosed is a three-dimensional memory device. in one embodiment, a device is disclosed comprising a source plate; plugs fabricated on or partially formed in the source plate; a stack formed on the substrate and plugs comprising alternating insulating layers and conductive layers and channel-material strings of memory cells extending through the insulating layers and conductive layers; a first set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the first set of pillars terminates atop a respective plug in the plurality of plugs; and a second set of pillars extending through the stack formed by a process including etching the alternating insulating layers and conductive layers and depositing a pillar material therein, wherein each pillar in the second set of pillars terminates in the source plate.
Inventor(s): Hong Wan Ng of Singapore (SG) for micron technology, inc., Seng Kim Ye of Singapore (SG) for micron technology, inc.
IPC Code(s): H01L25/00, H01L23/00, H01L23/31, H01L25/065, H01L25/18
Abstract: stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. in one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. the plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.
Inventor(s): Zaiyuan Ren of Boise ID (US) for micron technology, inc., Thomas Gehrke of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L33/00, H01L33/16, H01L33/32
Abstract: light emitting diodes (“leds”) with n-polarity and associated methods of manufacturing are disclosed herein. in one embodiment, a method for forming a light emitting diode on a substrate having a substrate material includes forming a nitrogen-rich environment at least proximate a surface of the substrate without forming a nitrodizing product of the substrate material on the surface of the substrate. the method also includes forming an led structure with a nitrogen polarity on the surface of the substrate with a nitrogen-rich environment.
Inventor(s): Martin F. Schubert of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): H01L33/62, H01L33/06, H01L33/10, H01L33/14, H01L33/32, H01L33/36, H01L33/38, H01L33/40, H01L33/42, H01L33/44, H01L33/46, H01L33/60
Abstract: solid state lighting (“ssl”) devices with improved contacts and associated methods of manufacturing are disclosed herein. in one embodiment, an ssl device includes an ssl structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. the ssl device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the ssl structure. the first or second contact is configured to provide a current density profile in the ssl structure based on a target current density profile.
Inventor(s): Vladimir Odnoblyudov of Eagle ID (US) for micron technology, inc., Martin F. Schubert of Mountain View CA (US) for micron technology, inc.
IPC Code(s): H01L33/62, H01L21/78, H01L25/075, H01L27/04, H01L27/15, H01L33/00, H01L33/06, H01L33/32, H01L33/38, H01L33/40, H01L33/64
Abstract: solid-state transducers (“ssts”) and vertical high voltage ssts having buried contacts are disclosed herein. an sst die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. the sst can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. an interconnect can be formed between at least one first contact and one second contact. the interconnects can be covered with a plurality of package materials.
Inventor(s): James Ruane of San Jose CA (US) for micron technology, inc., Robert W. Strong of Folsom CA (US) for micron technology, inc.
IPC Code(s): H04L9/08, G06F9/32, G06F9/4401, G06F12/02, G06F12/14, G06F21/78, H04L9/32
Abstract: a processing device is configured to process an initial set of command types. a command extension module and a digital signature are received. the digital signature is generated based on the command extension module using a private key of a key pair. the command extension module, once installed by the processing device, enables the processing device to process a new command type that is not included in the initial set of command types. the digital signature is verified using a public key of the key pair. based on a successful verification of the digital signature, the command extension module is temporarily installed by loading the command extension module in a volatile memory device.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/11582
Abstract: a microelectronic device comprising tiers of alternating dielectric materials and conductive materials, pillars extending through the tiers, and a doped dielectric material adjacent to the tiers. the doped dielectric material comprises a heterogeneous chemical composition comprising one or more dopants. conductive contact structures are in the doped dielectric material. additional microelectronic devices, microelectronic systems, and methods of forming microelectronic devices are disclosed.
Inventor(s): Shyam Surthi of Boise ID (US) for micron technology, inc., Richard J. Hill of Boise ID (US) for micron technology, inc., Gurtej S. Sandhu of Boise ID (US) for micron technology, inc., Byeung Chul Kim of Boise ID (US) for micron technology, inc., Francois H. Fabreguette of Boise ID (US) for micron technology, inc., Chris M. Carlson of Nampa ID (US) for micron technology, inc., Michael E. Koltonski of Boise ID (US) for micron technology, inc., Shane J. Trapp of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27
Abstract: an electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. a pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. the storage node segments are separated by a vertical portion of the tunnel region. a high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
Inventor(s): Yongjun Hu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/1157, G11C5/06, H01L27/11524, H01L27/11578
Abstract: methods, systems, and devices for single crystal silicon cores for stacked memory cells are described. a memory device may be formed using silicon cores that are each associated with a set of multiple memory cells. multiple silicon cores may extend along a first direction, and multiple sleeves of memory materials and conductive materials may be formed around each silicon core. each sleeve of memory materials may be associated with a respective memory cell and each conductive material may be associated with a word line, such that each silicon core may be associated with multiple memory cells. the respective sleeves of memory materials and conductive materials may be formed from larger sleeves of material that may be etched into sections of the memory materials and the conductive materials along the silicon cores.
Inventor(s): S M Istiaque Hossain of Boise ID (US) for micron technology, inc., Christopher J. Larsen of Boise ID (US) for micron technology, inc., Anikumar Chandolu of Boise ID (US) for micron technology, inc., Wesley O. Mckinsey of Nampa ID (US) for micron technology, inc., Tom J. John of Boise ID (US) for micron technology, inc., Arun Kumar Dhayalan of Boise ID (US) for micron technology, inc., Prakash Rau Mokhna Rau of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/35, H10B41/27, H10B41/35, H10B43/20
Abstract: an electronic device comprising a lower deck and an upper deck adjacent to a source. each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. another conductive material is in the upper deck and the lower deck of the one or more non-array regions. additional electronic devices and related systems and methods of forming an electronic device are also disclosed.
20240130143.MEMORY AND STORAGE ON A SINGLE CHIP_simplified_abstract_(micron technology, inc.)
Inventor(s): Innocenzo Tortorelli of Cernusco sul Naviglio (MI) (IT) for micron technology, inc., Agostino Pirovano of Milano (MI) (IT) for micron technology, inc., Matteo Impalà of Milano (MI) (IT) for micron technology, inc., Mattia Robustelli of Milano (MI) (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/24, H01L45/00
Abstract: a single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. in particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. for the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. the process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. the memory and storage cells are independently addressable via wordline and bitline selection.
Micron Technology, Inc. patent applications on April 18th, 2024
- Micron Technology, Inc.
- C23C16/455
- C01B32/05
- C23C16/26
- Micron technology, inc.
- G01R31/319
- G01R31/3185
- G03F1/38
- G03F1/36
- G03F7/00
- G06F3/06
- G06F12/02
- G06F12/00
- G06F12/06
- G06F12/0891
- G06F11/07
- G11C11/407
- G11C29/04
- H01L25/065
- G11C7/10
- G11C11/22
- G11C7/06
- G11C16/34
- G11C16/10
- G11C16/16
- G11C16/26
- G11C16/32
- G11C29/46
- G11C29/12
- G11C29/44
- H01L23/48
- H01L21/306
- H01L21/324
- H01L21/48
- H01L23/00
- H01L23/498
- H01L27/08
- H01L25/00
- H01L23/528
- H01L27/112
- H01L29/86
- H01L21/768
- H01L23/535
- H10B20/00
- H10B41/10
- H10B41/27
- H10B41/50
- H10B43/10
- H10B43/27
- H10B43/50
- H01L23/31
- H01L25/18
- H01L33/00
- H01L33/16
- H01L33/32
- H01L33/62
- H01L33/06
- H01L33/10
- H01L33/14
- H01L33/36
- H01L33/38
- H01L33/40
- H01L33/42
- H01L33/44
- H01L33/46
- H01L33/60
- H01L21/78
- H01L25/075
- H01L27/04
- H01L27/15
- H01L33/64
- H04L9/08
- G06F9/32
- G06F9/4401
- G06F12/14
- G06F21/78
- H04L9/32
- H01L27/11582
- H01L27/1157
- G11C5/06
- H01L27/11524
- H01L27/11578
- H10B43/35
- H10B41/35
- H10B43/20
- H01L27/24
- H01L45/00
