Meta platforms technologies, llc (20240274587). 3D CHIPLET INTEGRATION USING FAN-OUT WAFER-LEVEL PACKAGING simplified abstract

3D CHIPLET INTEGRATION USING FAN-OUT WAFER-LEVEL PACKAGING

Organization Name

meta platforms technologies, llc

Inventor(s)

Rajendra D. Pendse of Fremont CA (US)

Ronald Ho of Los Altos Hills CA (US)

Maryam Rahimi of Sunnyvale CA (US)

Janani Chandrasekhar of Fremont CA (US)

Jaesik Lee of San Jose CA (US)

Aswani Kurra of Surrey (CA)

3D CHIPLET INTEGRATION USING FAN-OUT WAFER-LEVEL PACKAGING - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240274587 titled '3D CHIPLET INTEGRATION USING FAN-OUT WAFER-LEVEL PACKAGING

The abstract describes a circuit assembly consisting of multiple sub-packages, each containing different chiplets with active circuitry and memory, arranged to overlap in a specific direction.

• The circuit assembly includes a first sub-package with a chiplet facing in one direction, a second sub-package with a chiplet facing in the opposite direction, and a memory sub-package.
• The chiplets in the first and second sub-packages have active circuitry on their frontside.
• The sub-packages are positioned to overlap each other in the first direction.
• The memory sub-package contains memory components.
• The arrangement of the sub-packages allows for efficient integration of active circuitry and memory in a compact space.

Potential Applications: - This technology could be used in compact electronic devices where space is limited. - It could be applied in high-performance computing systems that require efficient integration of active circuitry and memory.

Problems Solved: - Addresses the challenge of integrating active circuitry and memory components in a small footprint. - Provides a solution for optimizing space utilization in circuit assemblies.

Benefits: - Improved efficiency in circuit assembly design. - Enhanced performance in electronic devices with limited space constraints.

Commercial Applications: Title: "Integrated Circuit Assembly for Compact Electronic Devices" This technology could be utilized in smartphones, tablets, wearable devices, and other compact electronics to enhance performance and functionality.

Questions about the technology: 1. How does the arrangement of the sub-packages contribute to the efficiency of the circuit assembly? 2. What are the potential challenges in implementing this technology in different electronic devices?

Original Abstract Submitted

a circuit assembly may include a first sub-package a first chiplet including an active frontside that includes active circuitry and faces in a first direction, a second sub-package including a second chiplet including an active frontside that includes active circuitry and faces in a second direction opposite the first direction, and a memory sub-package including a memory. the first sub-package, the second sub-package, and the memory sub-package may be arranged so as to overlap each other in the first direction. various other devices, systems, and methods are also disclosed.