Meta Platforms Technologies, LLC patent applications on July 4th, 2024
Patent Applications by Meta Platforms Technologies, LLC on July 4th, 2024
Meta Platforms Technologies, LLC: 20 patent applications
Meta Platforms Technologies, LLC has applied for patents in the areas of G06F9/30 (4), G06F3/01 (3), G06V40/16 (2), G06N3/0464 (2), G06F9/38 (2) G06F9/3013 (2), G01S15/8993 (1), G06K7/1417 (1), H04N25/616 (1), H04N23/741 (1)
With keywords such as: vector, array, data, registers, memory, configured, register, group, user, and based in patent application abstracts.
Patent Applications by Meta Platforms Technologies, LLC
Inventor(s): Anton Andreevich Shkel of Aliso Viejo CA (US) for meta platforms technologies, llc, Gengxi Lu of Fremont CA (US) for meta platforms technologies, llc, Doruk Senkal of Redmond WA (US) for meta platforms technologies, llc, Julio Isla Garcia of Redmond WA (US) for meta platforms technologies, llc
IPC Code(s): G01S15/89, G06F3/01, G06T13/40, G06V40/16
CPC Code(s): G01S15/8993
Abstract: a headset includes a frame and a plurality of transducers positioned on the frame to transmit beams towards one or more portions of a face of a user of the headset. the plurality of transducers receive reflected beams from the one or more portions of the face and generate sensor data that varies in response to the received reflected beams. the headset also includes a controller configured to use a machine learning model to generate an estimate of an expression of the user using the sensor data.
Inventor(s): Scott SHILL of Plano TX (US) for meta platforms technologies, llc, Tony DAVID of San Jose CA (US) for meta platforms technologies, llc, Kirk Erik BURGESS of Newark CA (US) for meta platforms technologies, llc
IPC Code(s): G01S19/48, G01S19/49
CPC Code(s): G01S19/485
Abstract: according to examples, a system for determining a location using a plurality of geo-location techniques is described. the system may include a processor and a memory storing instructions. the processor, when executing the instructions, may cause the system to receive sensor data associated with the location, receive image information associated with the location, analyze the image information associated with the location, and provide a localization and mapping analysis for the location. the processor, when executing the instructions, may then determine an analyzed list of features and a primary landmark associated with the location, and determine location information for the location based on the analyzed list of features and the primary landmark.
Inventor(s): Matthew Thomas Hunwardsen of Moorpark CA (US) for meta platforms technologies, llc
IPC Code(s): G02B27/01, G02B1/118, G02B5/20, G02B5/26, G02B27/00
CPC Code(s): G02B27/0172
Abstract: an illumination optical component for a head mounted device includes an input aperture, an optical substrate, a hot mirror layer, and exit feature voids. the input aperture is configured to accept near-infrared light from a light source. the optical substrate has a refractive index. the hot mirror layer is disposed on the optical substrate. the hot mirror layer is configured to confine the near-infrared light to be recycled within the optical substrate and configured to pass visible light. the exit feature voids are patterned into an eye-side of the hot mirror layer. the exit feature voids are configured to illuminate an eyebox region with near-infrared illumination light.
Inventor(s): Renate Eva Klementine Landig of Kirkland WA (US) for meta platforms technologies, llc, Nagi Hosni Elabbasi of Southborough MA (US) for meta platforms technologies, llc, Andrew John Ouderkirk of Kirkland WA (US) for meta platforms technologies, llc
IPC Code(s): G02F1/29
CPC Code(s): G02F1/29
Abstract: a fluidic optical element includes a bilayer having a fluid layer and a gel layer directly overlying the fluid layer, and a primary electrode disposed over a surface of the bilayer. the geometry of an interface between the fluid layer and the gel layer and hence the optical response of the bilayer to incident light may be manipulated using the principle of dielectrophoresis.
Inventor(s): Jiayang Xu of Seattle WA (US) for meta platforms technologies, llc
IPC Code(s): G06F3/01, G06F3/042, G06F3/04886
CPC Code(s): G06F3/011
Abstract: in one embodiment, a method includes rendering, for one or more displays of an extended reality (xr) display device of a user, an xr user interface with one or more interactable elements positioned on a first hand of the user based on a first set of landmarks of the first hand; detecting one or more touchpoints by one or more digits of a second hand of the user on the xr user interface based on a projection of one or more of the digits on the second hand onto the first hand based on a second set of landmarks of the second hand, wherein the touchpoints are detected based on a distance between a distal end of the digits and the interactable elements being within a threshold value; and rendering a display window that provides an indication of the detected touchpoints with the interactable elements.
20240220255. DATA PARALLELISM_simplified_abstract_(meta platforms technologies, llc)
Inventor(s): Reza Tusi of San Jose CA (US) for meta platforms technologies, llc, Tomonari Tohara of Sunnyvale CA (US) for meta platforms technologies, llc, David Vakrat of Kfar Saba (IL) for meta platforms technologies, llc, Javid Jaffari of San Diego CA (US) for meta platforms technologies, llc, Yuan Liu of San Jose CA (US) for meta platforms technologies, llc
IPC Code(s): G06F9/30
CPC Code(s): G06F9/3013
Abstract: in one embodiment, a computing system may set data to a first group of registers. the first group of registers may be configured to be accessed during a single operation cycle. the system may set a number of patterns to a second group of registers. each pattern of the number of patterns may include an array of index for the data stored in the first group of registers. the system may select, for a first vector register associated with a vector engine, a first pattern from the patterns stored in the second group of registers. the system may load a first portion of the data from the first group of registers to the first vector register based on the first pattern selected for the first vector register from the patterns stored in the second group of registers.
Inventor(s): Reza Tusi of San Jose CA (US) for meta platforms technologies, llc, Tomonari Tohara of Sunnyvale CA (US) for meta platforms technologies, llc, Vignesh Vivekraja of Santa Clara CA (US) for meta platforms technologies, llc, Javid Jaffari of San Diego CA (US) for meta platforms technologies, llc
IPC Code(s): G06F9/30, G06F9/38
CPC Code(s): G06F9/3013
Abstract: in one embodiment, a computing system may load data from a memory unit into a number of registers according to a first order by which the data is arranged. the registers may be configured to be accessed during a single operation cycle. the system may determine a second order for the data based on one or more subsequent operations to process the data. the system may read the data from the registers according to the second order during one or more operation cycles. the data read from the registers may be arranged in the second order. the system may transmit the data arranged in the second order to an execution unit configured to execute the one or more subsequent operations to process the data arranged in the second order.
Inventor(s): Tomonari Tohara of Sunnyvale CA (US) for meta platforms technologies, llc, Vignesh Vivekraja of Santa Clara CA (US) for meta platforms technologies, llc, Alagappan Valliappan of Kirkland WA (US) for meta platforms technologies, llc, Andrey Bushev of Kirkland WA (US) for meta platforms technologies, llc, Javid Jaffari of San Diego CA (US) for meta platforms technologies, llc
IPC Code(s): G06F9/30
CPC Code(s): G06F9/30178
Abstract: in one embodiment, a computing system may set data to a first group of registers. the first group of registers may be configured to be accessed during a single operation cycle. the system may set a number of patterns to a second group of registers. each pattern of the number of patterns may include an array of index for the data stored in the first group of registers. the system may select, for a first vector register associated with a vector engine, a first pattern from the patterns stored in the second group of registers. the system may load a first portion of the data from the first group of registers to the first vector register based on the first pattern selected for the first vector register from the patterns stored in the second group of registers.
Inventor(s): Vignesh Vivekraja of Santa Clara CA (US) for meta platforms technologies, llc, Tomonari Tohara of Sunnyvale CA (US) for meta platforms technologies, llc, Reza Tusi of San Jose CA (US) for meta platforms technologies, llc, Abuduwaili Tuoheti of San Jose CA (US) for meta platforms technologies, llc, Javid Jaffari of San Diego CA (US) for meta platforms technologies, llc, Vlad Fruchter of Los Altos CA (US) for meta platforms technologies, llc, David Vakrat of Kfar Saba (IL) for meta platforms technologies, llc, Ohad Meitav of Sunnyvale CA (US) for meta platforms technologies, llc
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/3893
Abstract: in one embodiment, a system comprising a processor and a non-transitory memory coupled to the processor comprising instructions executable by the processor. the processor, comprising an internal memory; a multiply-accumulate (mac) array; a first vector register array; a second vector register array; and a third vector register array, is operable when executing a first instruction among the instructions to feed a weight vector array from the second vector register array to the mac array, broadcast an input activation vector to the mac array, multiply an input activation value broadcast to the mac unit from the input activation vector and a weight value fed to the mac unit from the weight vector array at each mac unit in the mac array, and store a partial output activation vector to the third vector register array, wherein the partial output activation vector is the output of the mac array.
Inventor(s): Vignesh Vivekraja of Santa Clara CA (US) for meta platforms technologies, llc, Tomonari Tohara of Sunnyvale CA (US) for meta platforms technologies, llc, Reza Tusi of San Jose CA (US) for meta platforms technologies, llc, Abuduwaili Tuoheti of San Jose CA (US) for meta platforms technologies, llc, Weiping Liu of Fremont CA (US) for meta platforms technologies, llc, Javid Jaffari of San Diego CA (US) for meta platforms technologies, llc
IPC Code(s): G06F9/445, G06N3/0464
CPC Code(s): G06F9/44505
Abstract: in one embodiment, a method includes accessing a computational graph representing computations to be executed on a computing system comprising a plurality of execution units (eus), identifying a set of candidate mapped-graphs for the computational graph, where each node in a candidate mapped-graph is mapped to an eu capable of calculating the node, ensuring that each edge from a first node to a second node in each candidate mapped-graph satisfies memory constraints, determining an expected cost for executing each candidate mapped-graph using mapped-eus in the candidate mapped-graph for calculating respective nodes, and selecting a candidate mapped-graph with a least expected cost from the set of candidate mapped-graphs.
Inventor(s): Shiyu Liu of Sunnyvale CA (US) for meta platforms technologies, llc, Soroush Heidari of Sunnyvale CA (US) for meta platforms technologies, llc, Tomonari Tohara of Sunnyvale CA (US) for meta platforms technologies, llc, Reza Tusi of San Jose CA (US) for meta platforms technologies, llc, Javid Jaffari of San Diego CA (US) for meta platforms technologies, llc
IPC Code(s): G06F17/16
CPC Code(s): G06F17/16
Abstract: a method implemented by a digital signal processor (dsp) including application-specific processing engines is provided. the method includes accessing, by the application-specific processing engines a configurable microcode. the configurable microcode includes a set of instructions configured to cause the application-specific processing engines to execute a matrix-based arithmetic algorithm. the method includes executing, by the application-specific processing engines, and based on the configurable microcode, the matrix-based arithmetic algorithm. executing the matrix-based arithmetic algorithm includes receiving, by the application-specific processing engines, one or more input matrices, performing, by the application-specific processing engines, a plurality of computations based on the one or more input matrices by iteratively executing one or more of a predetermined set of arithmetic operations until the execution of the matrix-based arithmetic algorithm is completed, and generating, by the application-specific processing engines, an output corresponding to the completed execution of the matrix-based arithmetic algorithm.
Inventor(s): Bhramara TIRUPATI of Redmond WA (US) for meta platforms technologies, llc
IPC Code(s): G06F40/47, G10L15/00
CPC Code(s): G06F40/47
Abstract: the disclosed technology includes capturing speech audio from a sound source, modifying the captured speech audio to have speech patterns that match that of the user, and playing back the modified speech audio content to the user to facilitate comprehension. such a design once tested has applicability in social situations for international visitors as well as immigrant populations in a foreign country. another use case for this technology would be improving reading and listening comprehension in children or assisting special needs children and adults with an assistive technology. in such cases, the playback audio could be the voice of a caretaker, parent or a medical professional as appropriate for the situation.
Inventor(s): Alexander FAABORG of Mountain View CA (US) for meta platforms technologies, llc, Joseph GARDNER of Burlingame CA (US) for meta platforms technologies, llc
IPC Code(s): G06K7/14, G06F3/01, G06V20/20, G06V30/224, G06V40/16
CPC Code(s): G06K7/1417
Abstract: in some implementations, the disclosed systems and methods can be in sleep mode as its user traverses the real-world environment and can awaken upon a trigger, such as the wrist being raised (as detected, for example, by cameras or sensors on a smart wristband in communication with the xr device). in some implementations, the disclosed systems and methods can capture images of a user wearing the device while looking in the mirror.
Inventor(s): Vignesh Vivekraja of Santa Clara CA (US) for meta platforms technologies, llc, Tomonari Tohara of Sunnyvale CA (US) for meta platforms technologies, llc, Reza Tusi of San Jose CA (US) for meta platforms technologies, llc, Abuduwaili Tuoheti of San Jose CA (US) for meta platforms technologies, llc, Javid Jaffari of San Diego CA (US) for meta platforms technologies, llc, Vlad Fruchter of Los Altos CA (US) for meta platforms technologies, llc, David Vakrat of Kfar Saba (IL) for meta platforms technologies, llc, Ohad Meitav of Sunnyvale CA (US) for meta platforms technologies, llc
IPC Code(s): G06N3/0464, G06F7/544, G06F17/15, H03H17/02
CPC Code(s): G06N3/0464
Abstract: in one embodiment, a system comprising a processor and a non-transitory memory coupled to the processor comprising instructions executable by the processor. the processor, comprising an internal memory; a multiply-accumulate (mac) array; a first vector register array; a second vector register array; and a third vector register array, is operable when executing instructions to transfer weights for m filters and an input activation tensor from an external memory to the internal memory, insert paddings to the input activation tensor in the internal memory based on first configuration parameters, configure the mac array to a required shape based on second configuration parameters for convolution operations between the input activation tensor and the m filters, and calculate a row of the output activation tensor by performing the convolution operations on corresponding r rows of the input activation tensor with the m filters, wherein r is a filter height.
Inventor(s): Zohar Barzelay of Sunnyvale CA (US) for meta platforms technologies, llc, Maxim Bluvshtein of Redmond WA (US) for meta platforms technologies, llc
IPC Code(s): G06T19/00, G06N3/08, G06T15/06
CPC Code(s): G06T19/00
Abstract: a method for resolving body-garment collisions in avatars for immersive reality applications is provided. the method includes forming a two-dimensional projection of a dressed avatar in an immersive reality application running in a headset, identifying, from the two-dimensional projection, an area that includes a garment collision, and replacing a pixel in the area that includes the garment collision, with a pixel indicative of a garment for the dressed avatar, to form a new two-dimensional projection of the dressed avatar. a system and a non-transitory, computer-readable medium storing instructions to perform the above method, are also provided.
20240223562. CLOUD VIRTUAL REALITY ECOSYSTEM_simplified_abstract_(meta platforms technologies, llc)
Inventor(s): Eric Harvard Cosky of Redwood City CA (US) for meta platforms technologies, llc
IPC Code(s): H04L9/40
CPC Code(s): H04L63/10
Abstract: a method for virtual reality cloud computing includes receiving, from a client device, a request by a user of the client device to execute a application, the application being provided by a third-party cloud service comprising a plurality of hosts. the method further includes selecting, from the plurality of hosts, a particular host to service the request, and receiving, from the particular host, connection parameters that are required for establishing a streaming connection to the particular host. the method further includes, in response to the request, providing the connection parameters to a streaming client executing on the client device, and instructing the streaming client to establish the streaming connection to the particular host and to execute the application.
Inventor(s): Nayeong KIM of Berkeley CA (US) for meta platforms technologies, llc, Chun-Wei CHAN of Foster City CA (US) for meta platforms technologies, llc
IPC Code(s): H04N19/167, G06T7/11, H04N19/176
CPC Code(s): H04N19/167
Abstract: one embodiment of the present invention sets forth a technique for generation region-based user interest levels for use during video encoding. the technique includes identifying a plurality of view events associated with a frame of a video content, wherein each view event comprises field of view information indicating a region in the frame at which an interest of a given user was directed when the frame was being rendered, processing the field of view information included in at least a subset of the plurality of view events to generate per-pixel interest levels for a plurality of pixels in the frame, determining a plurality of regions in the frame including the plurality of pixels, generating per-region interest levels for the plurality of regions based on the per-pixel interest levels, and transmitting the per-region interest levels to one or more encoders for encoding the video content in a manner that accounts for the plurality of view events.
Inventor(s): Jinglun Gao of San Mateo CA (US) for meta platforms technologies, llc, Jun Hu of San Jose CA (US) for meta platforms technologies, llc, Shan Tong of Sunnyvale CA (US) for meta platforms technologies, llc
IPC Code(s): H04N23/741, G01J1/42, H04N1/00, H04N23/51, H04N23/65, H04N23/74
CPC Code(s): H04N23/741
Abstract: hyperlapse imaging is described. a device may include a camera, a sensor and a data store. the camera is configured to capture images. the sensor detects ambient light properties. captured images and the ambient light properties are processed in bulk to generate a hyperlapse video.
Inventor(s): Song Chen of Redmond WA (US) for meta platforms technologies, llc, Xinqiao Liu of Medina WA (US) for meta platforms technologies, llc, Tsung-Hsun Tsai of Redmond WA (US) for meta platforms technologies, llc, Qing Chao of Redmond WA (US) for meta platforms technologies, llc, Michael Hall of Bellevue WA (US) for meta platforms technologies, llc, David Maurice Moore of Redmond WA (US) for meta platforms technologies, llc, Sharvil Shailesh Talati of Belmont WA (US) for meta platforms technologies, llc
IPC Code(s): H04N25/616, H04N25/131, H04N25/53, H04N25/67, H04N25/771
CPC Code(s): H04N25/616
Abstract: systems and methods of the present disclosure include a digital image sensor pixel configured to perform digital correlated double-sampling (d-cds) operations to compensate for fixed pattern noise (fpn) induced by comparator propagation delay variation across a digital pixel array. the pixel and d-cds operations also support quantization of incident light using two pixel memory banks. the pixel includes data retention logic coupled to selectively lock and unlock the output of a comparator. the output of the comparator is combined with memory bank write enable signals to convert photodiode charge into digital pixel values stored in the two memory banks. the digital pixel values stored in the memory banks may be added or subtracted to generate an fpn compensated digital pixel value.
Inventor(s): Adam Richard WEBER of Sammamish WA (US) for meta platforms technologies, llc, Jason HOWSER of Bothell WA (US) for meta platforms technologies, llc, Maxwell MILROY of Seattle WA (US) for meta platforms technologies, llc
IPC Code(s): H05K9/00, H05K1/02
CPC Code(s): H05K9/0035
Abstract: aspects of the present disclosure are directed to a flexible printed circuit board (fpc) assembly including an fpc, an electrical connector mounted on a first surface of the fpc and configured to transfer data and power signals, and a shield can mounted on a second surface of the fpc. the electrical connector can be a usb-c connector. the second surface of the fpc can be opposite the first surface of the fpc. the shield can can surround an area on the second surface of the fpc that overlaps an area of the first surface of the fpc on which the electrical connector is mounted. electromagnetic discharge (esd) protection components can be mounted on the fpc within the shield can. the shield can can be configured as a strain-relief to stiffen the fpc, and can electromagnetically shield the esd protection components.
Meta Platforms Technologies, LLC patent applications on July 4th, 2024
- Meta Platforms Technologies, LLC
- G01S15/89
- G06F3/01
- G06T13/40
- G06V40/16
- CPC G01S15/8993
- Meta platforms technologies, llc
- G01S19/48
- G01S19/49
- CPC G01S19/485
- G02B27/01
- G02B1/118
- G02B5/20
- G02B5/26
- G02B27/00
- CPC G02B27/0172
- G02F1/29
- CPC G02F1/29
- G06F3/042
- G06F3/04886
- CPC G06F3/011
- G06F9/30
- CPC G06F9/3013
- G06F9/38
- CPC G06F9/30178
- CPC G06F9/3893
- G06F9/445
- G06N3/0464
- CPC G06F9/44505
- G06F17/16
- CPC G06F17/16
- G06F40/47
- G10L15/00
- CPC G06F40/47
- G06K7/14
- G06V20/20
- G06V30/224
- CPC G06K7/1417
- G06F7/544
- G06F17/15
- H03H17/02
- CPC G06N3/0464
- G06T19/00
- G06N3/08
- G06T15/06
- CPC G06T19/00
- H04L9/40
- CPC H04L63/10
- H04N19/167
- G06T7/11
- H04N19/176
- CPC H04N19/167
- H04N23/741
- G01J1/42
- H04N1/00
- H04N23/51
- H04N23/65
- H04N23/74
- CPC H04N23/741
- H04N25/616
- H04N25/131
- H04N25/53
- H04N25/67
- H04N25/771
- CPC H04N25/616
- H05K9/00
- H05K1/02
- CPC H05K9/0035
