MICRON TECHNOLOGY, INC. patent applications published on July 4th, 2024

Summary of the patent applications from MICRON TECHNOLOGY, INC. on July 4th, 2024

1. **Summary**: Micron Technology, Inc. has recently filed patents for innovative memory device architectures aimed at improving performance and efficiency. These patents focus on low resistance crosspoint architectures, integrated assemblies for enhanced memory storage, and advanced memory circuitry designs. The key aspects include the use of thermal barrier materials, conductive vias, and optimized memory circuitry formation. These technologies aim to address issues such as high resistance, inefficient connectivity, and performance limitations in electronic systems.

2. **Key Points of Patents**:

  * Low resistance crosspoint architecture for memory devices.
  * Use of thermal barrier material to enhance performance.
  * Formation of conductive vias to improve connectivity.
  * Integrated assembly with memory regions and an intermediate region.
  * H-shaped structure with doped-semiconductor material.
  * Memory circuitry formation with transistors and digitline structures.
  * Secure memory device assembly with hook-shaped engagement structures.

3. **Notable Applications**:

  * Memory devices in electronic systems.
  * High-speed data storage applications.
  * Semiconductor manufacturing industry.
  * Integrated circuit design.
  * Improved memory capacity and data processing speeds.
  * Enhanced reliability and durability of memory devices.

Patent applications for MICRON TECHNOLOGY, INC. on July 4th, 2024

MEASURING A TIMING MARGIN OF A MEMORY DEVICE USING AN INTERNAL OSCILLOSCOPE (18606138)

Main Inventor

Brandon Richard Nixon

UNIFIED SEQUENCER CONCURRENCY CONTROLLER FOR A MEMORY SUB-SYSTEM (18601586)

Main Inventor

Fangfang Zhu

MULTI-TIER HEALTH STATUS IN A MEMORY DEVICE (18540716)

Main Inventor

Sheng-Huang Lee

FOLDING OPERATIONS FOR IMPROVED SEQUENTIAL READ PERFORMANCE (18395222)

Main Inventor

Nitul Gohain

Test Memory Sub-Systems through Validation of Responses to Proof of Space Challenges (18608114)

Main Inventor

Joseph Harold Steinmetz

TECHNIQUES FOR CONCURRENT HOST SYSTEM ACCESS AND DATA FOLDING (18534363)

Main Inventor

Nitul Gohain

COMMAND PRIORITIZATION TECHNIQUES FOR REDUCING LATENCY IN A MEMORY SYSTEM (18407086)

Main Inventor

Christopher Joseph Bueb

TRUTH TABLE EXTENSION FOR STACKED MEMORY SYSTEMS (18604050)

Main Inventor

Joseph T. Pawlowski

COUNTER-BASED MULTIPLICATION USING PROCESSING IN MEMORY (18607653)

Main Inventor

Dmitri Yudanov

EMPTY PAGE DETECTION (18400027)

Main Inventor

Kyungjin Kim

COORDINATED ERROR PROTECTION (18435710)

Main Inventor

Scott E. Schaefer

REDUNDANCY-BASED ERROR DETECTION IN A MEMORY DEVICE (18608460)

Main Inventor

Scott E. Schaefer

MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE (18608652)

Main Inventor

Robert Mason

MACHINE LEARNING MODEL AGGREGATION (18393357)

Main Inventor

Pavana Prakash

REFLOW PROTECTION FOR A MODULE SEMICONDUCTOR DEVICE (18523151)

Main Inventor

Minjian WU

TECHNIQUES FOR INDICATING ROW ACTIVATION (18408228)

Main Inventor

Graziano Mirichigni

DYNAMIC PROGRAMMING TIME FOR A MEMORY DEVICE (18538652)

Main Inventor

Yue WANG

SIGNAL DEVELOPMENT CIRCUITRY LAYOUTS IN A MEMORY DEVICE (18408252)

Main Inventor

Daniele Vimercati

CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS (18409992)

Main Inventor

Innocenzo Tortorelli

MULTI-PROGRAM OF MEMORY CELLS WITHOUT INTERVENING ERASE OPERATIONS (18604858)

Main Inventor

Ezra Edward Hartz

FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTRIBUTIONS (18604276)

Main Inventor

Sheyang Ning

MEMORY DEVICE HAVING AN IMPROVED ECC ARCHITECTURE (17802009)

Main Inventor

Christophe Laurent

METHODS AND SYSTEMS FOR REDUCING ECC POWER CONSUMPTION (17802034)

Main Inventor

Christophe Laurent

SEMICONDUCTOR DEVICE WITH A MULTI-LAYERED ENCAPSULANT AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS (18602553)

Main Inventor

Shijian Luo

CROSSLINKING A BACK GRINDING TAPE FOR A SEMICONDUCTOR WAFER (18390795)

Main Inventor

Ankur Harish SHAH

SEMICONDUCTOR SUBSTRATE WITH A SACRIFICIAL ANNULUS (18508239)

Main Inventor

Jeremy E. Minnich

SEMICONDUCTOR DEVICE HAVING CONTACT PLUG (18483748)

Main Inventor

TAKAYOSHI TASHIRO

SEMICONDUCTOR INTERCONNECT STRUCTURES WITH VERTICALLY OFFSET BONDING SURFACES, AND ASSOCIATED SYSTEMS AND METHODS (18610263)

Main Inventor

Kyle K. Kirby

SEMICONDUCTOR ASSEMBLIES USING EDGE STACKING AND METHODS OF MANUFACTURING THE SAME (18608868)

Main Inventor

Thomas H. Kinsley

DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE (18607999)

Main Inventor

Vijayakrishna J. Vankayala

Method for Compensating Electrical Device Variabilities in Configurable-Output Circuit and Device (18601429)

Main Inventor

Pierguido Garofalo

APPARATUSES INCLUDING ONE OR MORE SEMICONDUCTOR DEVICES AND RELATED SYSTEMS (18609928)

Main Inventor

Michael G. Placke

Memory Circuitry And Methods Used In Forming Memory Circuitry (18527091)

Main Inventor

Jordan D. Greenlee

Integrated Assemblies, and Methods of Forming Integrated Assemblies (18604811)

Main Inventor

John D. Hopkins

LOW RESISTANCE CROSSPOINT ARCHITECTURE (18409413)

Main Inventor

Rajasekhar Venigalla