MICRON TECHNOLOGY, INC. patent applications on July 4th, 2024
Patent Applications by MICRON TECHNOLOGY, INC. on July 4th, 2024
MICRON TECHNOLOGY, INC.: 35 patent applications
MICRON TECHNOLOGY, INC. has applied for patents in the areas of G06F3/06 (8), G06F11/07 (4), G11C7/10 (4), H01L25/065 (4), H01L23/00 (3) G06F3/0659 (2), H01L21/6836 (2), G11C29/42 (2), G06F1/14 (1), G11C13/003 (1)
With keywords such as: memory, data, device, substrate, material, devices, region, configured, cells, and include in patent application abstracts.
Patent Applications by MICRON TECHNOLOGY, INC.
Inventor(s): Brandon Richard Nixon of Meridian ID (US) for micron technology, inc.
IPC Code(s): G06F1/14
CPC Code(s): G06F1/14
Abstract: a known randomized data pattern at a predetermined reference voltage of the internal oscilloscope is inputted to an internal oscilloscope of the receiving device for each delay tap element of a plurality of consecutive delay tap elements applied to a system clock of a receiving device. a first delay tap element among the plurality of consecutive delay tap elements in which an output of the internal oscilloscope matches the known randomized data pattern is identified. responsive to identifying the first delay tap element, a last delay tap element among the plurality of consecutive delay tap elements in which the output of the internal oscilloscope matches the known randomized data pattern is identified.
Inventor(s): Fangfang Zhu of San Jose CA (US) for micron technology, inc., Jiangli Zhu of San Jose CA (US) for micron technology, inc., Ying Y. Tai of Mountain View CA (US) for micron technology, inc.
IPC Code(s): G06F1/3234, G06F1/3206, G06F1/329
CPC Code(s): G06F1/3275
Abstract: a temperature value associated with a memory device is identified. a power limit for the memory device is determined based on the temperature value. a current power usage level of the memory device is determined. responsive to determining that the current power usage level of the memory device does not satisfy the power limit, a power-limited mode for the memory device is determined to be entered.
Inventor(s): Sheng-Huang Lee of Meridian ID (US) for micron technology, inc., Lu Tong of Singapore (SG) for micron technology, inc., Lawrence Celso Miranda of San Jose CA (US) for micron technology, inc., Lakshmi Kalpana Vakati of San Jose CA (US) for micron technology, inc., Ekamdeep Singh of San Jose CA (US) for micron technology, inc., Ashish Ghai of Saratoga CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F11/07
CPC Code(s): G06F3/061
Abstract: control logic in a memory device identifies a segment of the plurality of segments of a memory array of a memory device, and determines a health status for the segment from a plurality of possible health statuses, the plurality of possible health statuses comprising three or more health statuses. the control logic further provides the health status for the segment to a memory sub-system controller associated with the memory device, wherein the memory sub-system controller is to perform a corresponding action with respect to the segment based on the health status, and wherein the corresponding action is different for each of the plurality of possible health statuses.
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Nicola Colella of Capodrise (CE) (IN) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0613
Abstract: methods, systems, and devices for folding operations for improved sequential read performance are described. a memory system may perform a single-die access operation to program data to source data blocks of the memory system. the memory system may reorder the data during folding to destination data blocks of the memory system such that a multi-die access operation may be performed to sequentially read the data from the destination data blocks. for example, data may be programmed to the source data blocks in a first order as part of a single-die access operation, and the data may be folded to the destination data blocks in a second order as part of a single-die access operation, where the supports sequentially reading the data from the destination data blocks as part of a multi-die access operation.
Inventor(s): Joseph Harold Steinmetz of Loomis CA (US) for micron technology, inc., Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: a memory sub-system, such as a solid-state drive (ssd), having host interface configured to receive at least read commands and write commands from an external host system. the ssd has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. during an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: methods, systems, and devices for techniques for concurrent host system access and data folding are described. a memory system may determine to transfer (e.g., fold) data from a set of source data blocks to a set of destination data blocks. the memory system may receive a command to access a first source data block of the set of source data blocks concurrent with the data transfer. the memory system may generate a first order for transferring respective portions of the data that is based on a second order associated with a sequential read of the data from the set of destination data blocks. based on the accessing the first source data block being concurrent with the data transfer, the first order may exclude a first portion of the data from the first source data block such that the data transfer and the accessing may be concurrently performed.
Inventor(s): Christopher Joseph Bueb of Folsom CA (US) for micron technology, inc., Olivier Duval of Pacifica CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F9/455
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for command prioritization techniques for reducing latency in a memory system are described. in some examples, a host system may receive a set of commands from one or more virtual machines to access a common memory system. the host system may store the set of command in a command queue associated with the memory system and arrange the set of command according to order that is based on one or more identified pattern of accessing sequential addresses in the set of commands. the host system may transmit the set of command to the memory system based on the order and the memory system may execute the commands according to the order.
Inventor(s): Joseph T. Pawlowski of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06, H01L25/065, H01L25/18
CPC Code(s): G06F3/0659
Abstract: techniques for extending a truth table of a stacked memory system are provided. in an example, a storage system can include a stack of first memory die configured to store data and a logic die. the logic die can include an interface circuit configured to receive multiple memory requests from an external host using a first command bus, a second command bus, and a data bus, and a controller configured to interface with the stack of first memory die to store and retrieve the data from the stack of first memory die. the logic die can include a second memory having a faster access time than devices of the stack of first memory die, and the interface circuit can directly access the second memory in response to a first memory request of the multiple of memory requests.
Inventor(s): Dmitri Yudanov of Sacramento CA (US) for micron technology, inc.
IPC Code(s): G06F7/544, G06F3/06, G06F7/523, G06N3/08
CPC Code(s): G06F7/5443
Abstract: the present disclosure is directed to systems and methods for a memory device such as, for example, a processing-in-memory device that is configured to perform multiplication operations in memory using a popcount operation. a multiplication operation may include a summation of multipliers being multiplied with corresponding multiplicands. the inputs may be arranged in particular configurations within a memory array. sense amplifiers may be used to perform the popcount by counting active bits along bit lines. one or more registers may accumulate results for performing the multiplication operations.
20240220345. EMPTY PAGE DETECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Kyungjin Kim of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F11/07
CPC Code(s): G06F11/076
Abstract: aspects of the present disclosure configure a system component, such as a memory sub-system controller, to detect erroneous empty pages. the controller detects a read error associated with reading data from a set of memory components in accordance with an individual read level of a plurality of read levels. in response to detecting the read error, the controller computes one or more check failure unit count values corresponding to the individual read level. the controller compares the one or more check failure unit count values to a threshold value and determines whether the read error corresponds to an empty page read error based on a result of comparing the one or more check failure unit count values to the threshold value.
20240220354. COORDINATED ERROR PROTECTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Aaron P. Boehm of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/07, G06F11/10
CPC Code(s): G06F11/0793
Abstract: methods, systems, and devices for coordinated error protection are described. a set of data and an indication of whether a first management procedure performed by a memory device on the set of data detected one or more errors in the set of data may be received at a host device. at the host device, a second error management procedure may be performed on the set of data received from the memory device. based on the received indication and the second error management procedure, multiple bits indicating whether one or more errors associated with the set of data were detected at the memory device, the host device, or both may be generated. the set of data may be validated or discarded based on the multiple bits.
Inventor(s): Scott E. Schaefer of Boise ID (US) for micron technology, inc., Aaron P. Boehm of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for redundancy-based error detection in a memory device are described. a memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.
Inventor(s): Robert Mason of Boise ID (US) for micron technology, inc., Scott A. Stoller of Boise ID (US) for micron technology, inc., Pitamber Shukla of Boise ID (US) for micron technology, inc., Kenneth W. Marr of Boise ID (US) for micron technology, inc., Chi Ming Chu of Boise ID (US) for micron technology, inc., Hossein Afkhami of Berkeley CA (US) for micron technology, inc.
IPC Code(s): G06F11/14, G06F9/30
CPC Code(s): G06F11/1471
Abstract: exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. the self-recovery manager detects a failure of a memory device. the self-recovery manager retrieves a set of register values from the memory device. the self-recovery manager stores the set of register values from the memory device. the self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. the self-recovery manager compares the set of register values with the re-initialized set of register values. the self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.
20240220860. MACHINE LEARNING MODEL AGGREGATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Pavana Prakash of Houston TX (US) for micron technology, inc., Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Febin Sunny of Folsom CA (US) for micron technology, inc., Saideep Tiku of Fort Collins CO (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: methods and systems associated with a machine learning model aggregation are described. a system can include a first computing device, a second computing device, a local federated server, and a global federated server. the first computing device and the second computing device can train respective first and second machine learning models based on gathered memory usage data and device characteristic data associated with a respective first plurality of memory devices and second plurality of memory devices. the local federated server can aggregate the first machine learning model and the second machine learning model into a third machine learning model. the global federated server can aggregate the third machine learning model with a fourth machine learning model comprising a plurality of aggregated machine learning models into a fifth machine learning model and predict aging of the first plurality of memory devices and the second plurality of memory devices.
Inventor(s): Minjian WU of Shanghai (CN) for micron technology, inc.
IPC Code(s): G11C5/00, G11C11/4078
CPC Code(s): G11C5/005
Abstract: in some implementations, a memory device may configure a reflow critical data region in a non-volatile memory that is associated with at least one reflow protection measure for data stored in the reflow critical data region. the memory device may write a set of data to the reflow critical data region. the memory device may determine that a reflow process associated with the memory device has been completed. the memory device may reconfigure the reflow critical data region to remove the at least one reflow protection measure based on determining that the reflow process has been completed.
20240221798. TECHNIQUES FOR INDICATING ROW ACTIVATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Graziano Mirichigni of Vimercate (IT) for micron technology, inc., Efrem Bolandrina of Fiorano al Serio (IT) for micron technology, inc.
IPC Code(s): G11C7/10, G11C8/18
CPC Code(s): G11C7/1063
Abstract: methods, systems, and devices for techniques for indicating row activation are described. a memory device may receive an indication associated with an activation command, which may enable the memory device to begin some aspects of an activation operation before receiving the associated activation command. the indication may include a location of a next row to access as part of the activation command. the indication may be included in a previous activation command or in a precharge command. the memory device may begin activation operations for the next row before the precharge operation of the current row is complete. the memory device may receive the activation command for the next row after receiving the indication, and may complete the activation operations upon receiving the activation command.
Inventor(s): Yue WANG of Beijing City (CN) for micron technology, inc., Jingcheng YUAN of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C7/10, G11C7/20, G11C7/22
CPC Code(s): G11C7/1096
Abstract: in some implementations, a memory device may receive a write command indicating data to be programmed. the memory device may determine a programming time, from a first programming time and a second programming time, to be used to program the data, wherein the programming time indicates an amount of time to be associated with programming the data, and wherein the first programming time is associated with a first amount of time and the second programming time is associated with a second amount of time. the memory device may program the data to a memory of the memory device using the programming time.
Inventor(s): Daniele Vimercati of El Dorado Hills CA (US) for micron technology, inc.
IPC Code(s): G11C7/12, G11C7/10, G11C7/18
CPC Code(s): G11C7/12
Abstract: methods, systems, and devices for signal development circuitry layouts in a memory device are described. a memory device may include signal development circuitry that is positioned in multiple levels of a memory die relative to a substrate. for example, a set of first transistors used for developing access signals may be located on a first level of a memory die, and a set of second transistors used for developing the access signals may be located on a second level of the memory die. formation of the set of first transistors and the set of second transistors may involve processing operations that are common with the formation of other transistors on a respective level, such as cell selection transistors, deck selection transistors, shunting transistors, and other transistors of the respective level.
Inventor(s): Innocenzo Tortorelli of Cernusco Sul Naviglio (IT) for micron technology, inc., Fabio Pellizzer of Boise ID (US) for micron technology, inc., Mattia Robustelli of Milano (IT) for micron technology, inc., Alessandro Sebastiani of Piacenza (IT) for micron technology, inc.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/003
Abstract: methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. a pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. the selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
Inventor(s): Ezra Edward Hartz of Meridian ID (US) for micron technology, inc.
IPC Code(s): G11C16/14, G11C16/10, G11C16/26, G11C16/30, G11C16/34
CPC Code(s): G11C16/14
Abstract: a memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled with the array of memory cells. the control logic causes first data to be programmed to a plurality of memory cells of the array of memory cells, the first data including a first voltage distribution programmed relative to a first threshold voltage (vt) level. the control logic causes, without erasing the plurality of memory cells, second data to be programmed to the plurality of memory cells, the second data including a second voltage distribution programmed relative to a second vt level, wherein the second vt level is higher than the first vt level.
Inventor(s): Sheyang Ning of San Jose CA (US) for micron technology, inc., Lawrence Celso Miranda of San Jose CA (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/04, G11C16/08, G11C16/24, G11C16/26, G11C16/34
CPC Code(s): G11C16/16
Abstract: a memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. the control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. the control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.
Inventor(s): Christophe Laurent of Agrate Brianza (IT) for micron technology, inc., Riccardo Muzzetto of Arcore (IT) for micron technology, inc.
IPC Code(s): G11C29/42, G11C29/52
CPC Code(s): G11C29/42
Abstract: the present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected error correction code (ecc) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ecc operation on the stored codeword based on the selected ecc protection level. the encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ecc protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.
Inventor(s): Christophe Laurent of Agrate Brianza (IT) for micron technology, inc.
IPC Code(s): G11C29/42
CPC Code(s): G11C29/42
Abstract: the present disclosure relates to a method for operating an array of memory cells, the method comprising the steps of storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in a number of parity cells of the memory array, the parity data corresponding to one of a plurality of selectable error correction code (ecc) correction capabilities from a minimum ecc correction capability to a maximum ecc correction capability, calculating an ecc syndrome from the stored user data and parity data, based on the ecc syndrome, determining a number of errors in the data, and, based on the determined number of errors, selecting an ecc correction capability of the plurality of ecc correction capabilities. related memory devices and systems are also herein disclosed.
Inventor(s): Shijian Luo of Boise ID (US) for micron technology, inc., Jonathan S. Hacker of Meridian ID (US) for micron technology, inc.
IPC Code(s): H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L21/563
Abstract: a semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.
Inventor(s): Ankur Harish SHAH of Singapore (SG) for micron technology, inc., Venkateswarlu BHAVANASI of Singapore (SG) for micron technology, inc., Wen How SIM of Singapore (SG) for micron technology, inc., Harjashan Veer SINGH of South Richmond Hill NY (US) for micron technology, inc.
IPC Code(s): H01L21/683, H01L21/304
CPC Code(s): H01L21/6836
Abstract: implementations described herein relate to various semiconductor device assemblies and methods of forming the same. in some implementations, a semiconductor assembly may include a semiconductor wafer including a face including one or more circuit elements and a back grinding tape adhered to the face. the back grinding tape may include a polymer base layer and an adhesive layer adhering the back grinding tape to the face of the semiconductor wafer, and the back grinding tape may exhibit a damping ratio of less than approximately 0.8. the back grinding tape may include at least one of infrared-activated crosslinking groups or thermally activated crosslinking groups such that a degree of crosslinking associated with the back grinding tape may vary according to at least one of an amount of heat applied to the back grinding tape or an amount of infrared radiation applied to the back grinding tape.
Inventor(s): Jeremy E. Minnich of Boise ID (US) for micron technology, inc., Andrew M. Bayless of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/683, H01L21/306, H01L21/782, H01L25/065
CPC Code(s): H01L21/6836
Abstract: a semiconductor substrate is provided. the semiconductor substrate includes a center portion and a peripheral portion. the semiconductor substrate further includes an annulus of sacrificial material disposed at a front side of the semiconductor substrate and extending at least partially through the semiconductor substrate. the annulus of sacrificial material separates the center portion of the substrate from the peripheral portion of the substrate at the front side. the semiconductor substrate can be thinned to expose the annulus of sacrificial material and disconnect the peripheral portion from the center portion. in doing so, the thinned substrate may have a planar substrate edge void of sharp edges, thereby increasing its mechanical robustness.
20240222268. SEMICONDUCTOR DEVICE HAVING CONTACT PLUG_simplified_abstract_(micron technology, inc.)
Inventor(s): TAKAYOSHI TASHIRO of Higashihiroshima (JP) for micron technology, inc., HIROKI YAMAWAKI of Higashihiroshima (JP) for micron technology, inc., AKIRA KANEKO of Higashihiroshima (JP) for micron technology, inc.
IPC Code(s): H01L23/522, H01L21/768, H01L23/528, H01L23/532
CPC Code(s): H01L23/5226
Abstract: an apparatus that includes a first interlayer insulating film having a contact hole; a contact plug embedded in the contact hole, the contact plug including a main part and a barrier metal part located between an outer wall of the main part and an inner wall of the contact hole; a second interlayer insulating film covering the first interlayer insulating film; and a first conductive pattern embedded in the second interlayer insulating film and connected to the contact plug. apart of the second interlayer insulating film is embedded in a gap between a top part of the outer wall of the main part of the contact plug and a top part of the inner wall of the contact hole.
Inventor(s): Kyle K. Kirby of Eagle ID (US) for micron technology, inc.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065
CPC Code(s): H01L24/08
Abstract: semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. in one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. the interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. the plurality of conductive elements and the continuous region can have coplanar end surfaces. the interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. the perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.
Inventor(s): Thomas H. Kinsley of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/00, H01L23/053, H01L23/24, H01L23/31, H01L23/498, H01L23/522
CPC Code(s): H01L25/0652
Abstract: semiconductor assemblies and packages using edge stacking and associated systems and methods are disclosed herein. a semiconductor package may include (1) a base substrate having a base surface, (2) one or more dies attached over the base surface, and (3) a mold material encapsulating the base substrate and the one or more dies. the package may further include connectors on a side surface thereof, wherein the connectors are electrically coupled to the base substrate and/or the one or more dies. the connectors may be further configured to electrically couple the package to one or more neighboring semiconductor packages and/or electrical circuits.
Inventor(s): Vijayakrishna J. Vankayala of Allen TX (US) for micron technology, inc.
IPC Code(s): H03L7/191, G11C7/10, H03K19/20, H03L7/197
CPC Code(s): H03L7/191
Abstract: a memory device includes a clock input configured to receive a clock from a host device. the memory device also includes a command input configured to receive command and address bits from the host device. the memory device further includes multiple die stacked in a three-dimensional stack. a first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. the first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. the memory device also includes one or more transmitters configured to transmit the multiple clocks using inter-die interconnects between the multiple die.
Inventor(s): Pierguido Garofalo of San Donato Milanese (IT) for micron technology, inc.
IPC Code(s): H03M1/06
CPC Code(s): H03M1/0648
Abstract: a method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. the compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. a switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. an electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.
Inventor(s): Michael G. Placke of McKinney TX (US) for micron technology, inc.
IPC Code(s): H05K7/14, G06F3/06, H05K1/18
CPC Code(s): H05K7/1492
Abstract: memory devices may include a substrate supporting at least one semiconductor device thereon. the substrate may include an interface located proximate to an end of the substrate and sized, shaped, and configured to provide external electrical connection to the at least one semiconductor device. hook-shaped engagement structures may be located proximate to, and laterally outward from, the interface, the engagement structures extending laterally beyond a longitudinal remainder of a lateral periphery of the substrate trailing the engagement structures. the end of the substrate may lack screw keep-outs. a carrier may include posts shaped, positioned, and configured to be positioned in throats of the hook-shaped engagement structures to secure the end of the substrate to the carrier. sidewalls may extend longitudinally from a crossbar for placement along the remainder of the lateral periphery of the substrate.
Inventor(s): Jordan D. Greenlee of Nampa ID (US) for micron technology, inc., Ying Rui of Meridian ID (US) for micron technology, inc., Silvia Borsari of Boise ID (US) for micron technology, inc., Prashant Raghu of Boise ID (US) for micron technology, inc., Elisabeth Barr of Boise ID (US) for micron technology, inc., Yen Ting Lin of Boise ID (US) for micron technology, inc., Albert P. Chan of Boise ID (US) for micron technology, inc., Martin Chen of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: a method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. a channel region is between the one and the another source/drain regions. a conductive gate is operatively proximate the channel region. digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. the digitline structures individually comprise a conductive digitline and an insulator material thereatop. the insulator material has a top. first insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. second insulating material is formed over the first insulating material. the second insulating material has a maximum vertical thickness directly above the digitline structures that is greater than its minimum lateral thickness over the longitudinal sides of the digitline structures. the first insulating material is etched through to expose the one source/drain regions. storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. other embodiments, including structure, are disclosed.
Inventor(s): John D. Hopkins of Meridian ID (US) for micron technology, inc., Jordan D. Greenlee of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27, H10B41/41, H10B41/50, H10B43/40, H10B43/50
CPC Code(s): H10B43/27
Abstract: some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. the intermediate region has a first edge proximate the first memory region and has a second edge proximate the second memory region. channel-material-pillars are arranged within the first and second memory regions. conductive posts are arranged within the intermediate region. doped-semiconductor-material is within the intermediate region and is configured as a substantially h-shaped structure having a first leg region along the first edge, a second leg region along the second edge, and a belt region adjacent the panel. some embodiments include methods of forming integrated assemblies.
20240224825. LOW RESISTANCE CROSSPOINT ARCHITECTURE_simplified_abstract_(micron technology, inc.)
Inventor(s): Rajasekhar Venigalla of Boise ID (US) for micron technology, inc., Patrick M. Flynn of Boise ID (US) for micron technology, inc., Josiah Jebaraj Johnley Muthuraj of Meridian ID (US) for micron technology, inc., Efe Sinan Ege of Boise ID (US) for micron technology, inc., Kevin Lee Baker of Boise ID (US) for micron technology, inc., Tao Nguyen of Boise ID (US) for micron technology, inc., Davis Weymann of Boise ID (US) for micron technology, inc.
IPC Code(s): H10N70/00, G11C13/00, H01L21/768, H01L23/522, H01L23/528, H10B63/00, H10N70/20
CPC Code(s): H10N70/8616
Abstract: methods, systems, and devices for a low resistance crosspoint architecture are described. a manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. the manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. the manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
MICRON TECHNOLOGY, INC. patent applications on July 4th, 2024
- MICRON TECHNOLOGY, INC.
- G06F1/14
- CPC G06F1/14
- Micron technology, inc.
- G06F1/3234
- G06F1/3206
- G06F1/329
- CPC G06F1/3275
- G06F3/06
- G06F11/07
- CPC G06F3/061
- CPC G06F3/0613
- CPC G06F3/0619
- CPC G06F3/064
- G06F9/455
- CPC G06F3/0659
- H01L25/065
- H01L25/18
- G06F7/544
- G06F7/523
- G06N3/08
- CPC G06F7/5443
- CPC G06F11/076
- G06F11/10
- CPC G06F11/0793
- CPC G06F11/1068
- G06F11/14
- G06F9/30
- CPC G06F11/1471
- G06N20/00
- CPC G06N20/00
- G11C5/00
- G11C11/4078
- CPC G11C5/005
- G11C7/10
- G11C8/18
- CPC G11C7/1063
- G11C7/20
- G11C7/22
- CPC G11C7/1096
- G11C7/12
- G11C7/18
- CPC G11C7/12
- G11C13/00
- CPC G11C13/003
- G11C16/14
- G11C16/10
- G11C16/26
- G11C16/30
- G11C16/34
- CPC G11C16/14
- G11C16/16
- G11C16/04
- G11C16/08
- G11C16/24
- CPC G11C16/16
- G11C29/42
- G11C29/52
- CPC G11C29/42
- H01L21/56
- H01L23/00
- H01L23/31
- CPC H01L21/563
- H01L21/683
- H01L21/304
- CPC H01L21/6836
- H01L21/306
- H01L21/782
- H01L23/522
- H01L21/768
- H01L23/528
- H01L23/532
- CPC H01L23/5226
- H01L25/00
- CPC H01L24/08
- H01L23/053
- H01L23/24
- H01L23/498
- CPC H01L25/0652
- H03L7/191
- H03K19/20
- H03L7/197
- CPC H03L7/191
- H03M1/06
- CPC H03M1/0648
- H05K7/14
- H05K1/18
- CPC H05K7/1492
- H10B12/00
- CPC H10B12/33
- H10B43/27
- H10B41/27
- H10B41/41
- H10B41/50
- H10B43/40
- H10B43/50
- CPC H10B43/27
- H10N70/00
- H10B63/00
- H10N70/20
- CPC H10N70/8616
