Kioxia corporation (20240321323). MEMORY DEVICE simplified abstract
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Takeshi Sugimoto of Kamakura Kanagawa (JP)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240321323 titled 'MEMORY DEVICE
The memory device described in the abstract consists of memory cells arranged in layers, with each layer containing groups of memory cells arranged in different directions.
- Memory cells are organized in a first direction, with groups of memory cells in each layer arranged in a second direction intersecting the first direction.
- The groups of memory cells are further arranged in a third direction that intersects both the first and second directions.
- First wirings in each layer are arranged in the third direction and connected to the groups of memory cells in that layer.
- First transistors are connected to the first wirings, with second wirings connected to the first transistors of each layer.
- Third wirings extend in the first direction and are connected to a memory cell in each layer, while fourth wirings extend in the first direction and are connected to the gate of a corresponding first transistor in each layer.
Potential Applications: - This memory device could be used in various electronic devices such as smartphones, tablets, and computers. - It may find applications in data storage systems, servers, and other computing devices requiring high-speed memory access.
Problems Solved: - The memory device addresses the need for efficient and compact memory storage solutions. - It provides a structured and organized way to store and access data in electronic devices.
Benefits: - Improved memory access speed and efficiency. - Compact design for space-saving in electronic devices. - Enhanced data storage capabilities for better performance.
Commercial Applications: Title: Advanced Memory Device for High-Speed Data Storage This technology could be commercially applied in the production of consumer electronics, data centers, and other computing devices requiring high-performance memory solutions. The market implications include improved device performance, increased data storage capacities, and enhanced user experience.
Questions about the technology: 1. How does the memory device's unique arrangement of memory cells improve data access speed? 2. What are the potential cost implications of implementing this memory device in electronic devices?
Original Abstract Submitted
a memory device includes memory cells for each of layers arranged in a first direction, the memory cells of each layer including groups of memory cells, the memory cells of each group being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions, first wirings arranged in the third direction in each layer and respectively connected to the groups in each layer, first transistors each connected to a corresponding first wiring, second wirings each connected to the first transistors of a corresponding layer, third wirings each extending in the first direction and connected to a memory cell in each layer, and fourth wirings each extending in the first direction and connected to a gate of a corresponding first transistor in each layer.
