Kioxia Corporation patent applications published on September 28th, 2023

Summary of the patent applications from Kioxia Corporation on September 28th, 2023

Kioxia Corporation has recently filed patents for various semiconductor memory devices and storage devices. These devices utilize different materials and structures to improve performance and functionality. Some notable applications include:

• A storage device that uses a memory cell with a variable resistance element and a switching element. The switching element has snapback current-voltage characteristics, allowing it to handle high currents without damage.
• A magnetic memory device that utilizes a magnetoresistive effect element. This element consists of ferromagnetic layers, non-magnetic layers, and a metallic oxide layer containing platinum.
• A magnetic memory system that arranges magnetic members and wirings in a specific direction. A control circuit is used to write data into the magnetic members located between the wirings.
• A semiconductor memory device with multiple conductive layers and a peripheral circuit. The peripheral circuit includes components such as nodes, charging and discharging circuits, address select circuit, transistors, and amplifier circuits.
• A semiconductor device with layers made of silicon, insulating layers made of silicon and oxygen, and a conductive layer. These layers are arranged in a specific pattern and separated from each other.
• A semiconductor memory device with conductive layers, a semiconductor layer, and a gate insulating film. The lengths of the semiconductor layer at certain positions are smaller than others.
• A semiconductor memory device with a layer stack and a pillar. The pillar extends through the layer stack, and the second insulator in the pillar is divided into two parts of different thicknesses.
• A semiconductor memory device with multiple layers of conductive material and a bit line. A pillar extends through the conductive layers and is connected to the bit line via a via contact.
• A method of manufacturing a semiconductor device involving the formation and etching of films containing oxygen, nitrogen, and halogen substances.

Overall, Kioxia Corporation's recent patent filings demonstrate their focus on developing innovative semiconductor memory and storage devices with improved performance and functionality. These patents cover various aspects of device structures, materials, and manufacturing processes.

Patent applications for Kioxia Corporation on September 28th, 2023

TEMPLATE, METHOD FOR MANUFACTURING TEMPLATE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE (17898052)

Inventor Kazuya FUKUHARA

Brief explanation

The abstract describes a template that has a base material with a first surface. The template has two patterns - a first pattern with protruding portions in a central region and an outer peripheral region, and a second pattern with a protrusion portion in a different region. The first pattern protrudes to a higher level than the base material, while the second pattern protrudes even further. An optical layer is present in the central region, but the bottom surface of the outer peripheral region is not covered by the optical layer.

Abstract

According to one embodiment, a template includes a base material with a first surface at a first level. A first pattern on the template includes first protruding portions in a first region that protrude to a second level beyond the first level, a first recess portion between an adjacent pair of first protruding portions in a central portion of the first region, and a second recess portion between another adjacent pair of first protruding portions in an outer peripheral portion of the first region. A second pattern on the template includes a protrusion portion in a second region outside the first region. The protrusion portion protrudes to a third level. An optical layer is in the first recess portion and at least a portion of a bottom surface of the second recess portion is not covered by the optical layer.

MEMORY SYSTEM, HOST DEVICE AND INFORMATION PROCESSING SYSTEM FOR ERROR CORRECTION PROCESSING (18204854)

Inventor Shinichi KANNO

Brief explanation

The abstract describes a memory system that consists of a nonvolatile memory and a controller. The controller is responsible for managing the nonvolatile memory. The controller also sends a signal to an external source, indicating a specific state of either the nonvolatile memory or the controller itself.

Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.

SEMICONDUCTOR DEVICE AND HOST DEVICE (17900074)

Inventor Tomoaki SUZUKI

Brief explanation

This abstract describes a semiconductor device that has terminals connected to a host. The device includes two bridge chips, each connected to different terminals. The bridge chips are connected to multiple chips, with the first bridge chip connected to first chips and the second bridge chip connected to second chips. The first terminal is used to transmit a signal that designates which bridge chip should enable signal transmission to its connected chips. When the signal designates the first bridge chip, it allows signal transmission to the first chips, but disables it when the signal does not designate the first bridge chip. Similarly, the second bridge chip enables signal transmission to the second chips when designated by the signal, and disables it otherwise.

Abstract

A semiconductor device includes terminals connectable to a host, first and second bridge chips connected to the terminals, first chips connected to the first bridge chip, and second chips connected to the second bridge chip. The terminals includes a first terminal through which a first signal designating a bridge chip is transmitted. The first bridge chip is configured to enable signal transmission to at least one of the first chips when the first signal designates the first bridge chip, and disable the signal transmission to the first chips when the first signal does not designate the first bridge chip. The second bridge chip is configured to enable signal transmission to at least one of the second chips when the first signal designates the second bridge chip, and disable the signal transmission to the second chips when the first signal does not designate the second bridge chip.

MEMORY SYSTEM CONTROLLING NONVOLATILE MEMORY (18327108)

Inventor Naoki ESAKA

Brief explanation

The abstract describes a memory system controller that performs different operations on different blocks of memory. It performs a write operation and data erase operation multiple times on certain blocks, and a different write operation and data erase operation on other blocks. If a certain block is defective, the controller selects a different block and writes data to it in a specific write mode.

Abstract

According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM (17901837)

Inventor Mitsunori TADOKORO

Brief explanation

This abstract describes a memory system that consists of two chips and a processor. The processor receives commands from an external device and generates messages addressed to the two chips. These messages are then input into a repeater, which has an input port and two output ports connected to the chips. The repeater writes the messages to a shared memory, and when each chip is ready, it reads the corresponding message from the shared memory and outputs it to the respective chip. This system allows for efficient communication between the processor and the chips, ensuring that the messages are delivered to the correct chip when it is ready to receive them.

Abstract

A memory system includes a non-volatile memory including first and second chips, a processor configured to generate first messages in response to a command from an external device, the first messages addressed to the first and second chips, and a repeater including an input port to which the first messages are input and first and second output ports connected to the first and second chips. The repeater is configured to write the first messages input via the input port to a shared memory, read the first message addressed to the first chip from the shared memory when the first chip is ready, and output the first message to the first chip through the first output port, and read the first message addressed to the second chip when the second chip is ready, and output the second message to the second chip through the second output port.

MEMORY SYSTEM (17899398)

Inventor Takashi TAKEMOTO

Brief explanation

This abstract describes a memory system that consists of a nonvolatile memory and a controller. The controller is designed to divide data into clusters, compress each cluster, and assign the compressed clusters to encoding frames based on a predetermined rule. According to this rule, if a certain condition is met, a portion of a cluster is allocated to an empty space in an encoding frame in a first state. However, if there are no encoding frames in the first state or the condition is not met, the entire cluster is allocated to an encoding frame in a second state. The controller also encodes the data in each encoding frame and writes it into the nonvolatile memory.

Abstract

A memory system includes a nonvolatile memory and a controller. The controller is configured to segment data into clusters, perform a compression with respect to each of the clusters, allocate the clusters subjected to the compression to encoding frames in accordance with a predetermined rule. According to the predetermined rule, at least a part of a cluster is allocated to a vacant space of an encoding frame in a first state, when a predetermined condition is met, and an entirety of a cluster is allocated to an encoding frame in a second state, when no encoding frame in the first state exists or when the predetermined condition is not met. The controller is further configured to encode data in each of the encoding frames and write the encoded data into the nonvolatile memory.

IDENTIFICATION AND TOLERANCE OF HOST ERRORS RELATED TO COMMAND PROTOCOLS IN NON-VOLATILE MEMORY DEVICES (17700651)

Inventor Nigel Horspool

Brief explanation

The abstract describes a system, method, and computer-readable media for managing write commands to superblocks in a storage device. When a write command and write data are received from a host, indicating that the data should be written to a first superblock, the storage device checks if the first superblock has enough space to store the data. If it doesn't, the storage device either writes the data to a reserved capacity within the first superblock or to a second superblock.

Abstract

Various implementations described herein relate to systems, methods, and non-transitory computer-readable media for managing write commands to superblocks, including receiving, by a storage device from a host, a write command and a write data. The write command indicates that the write data is to be written to a first superblock of the storage device. The storage device determines the first superblock lacks sufficient capacity to store the write data. In response to determining that the first superblock lacks the sufficient capacity to store the write data, the storage device programs the write data to at least one of a reserved capacity of the first superblock or a second superblock.

MEMORY SYSTEM AND METHOD (17898381)

Inventor Hotaka UEKI

Brief explanation

This abstract describes a memory system that consists of a non-volatile memory and a memory controller. The memory controller is responsible for managing write commands received from a host. These commands can include two types of write commands: one for writing data associated with a first stream and another for writing data associated with a second stream. 

When these write commands are queued, the memory controller follows a specific sequence of operations. First, it acquires a predetermined amount of the first write data from the host and then transmits it to the non-volatile memory. After completing this first operation, it moves on to the second operation, where it acquires a predetermined amount of the second write data from the host and transmits it to the non-volatile memory.

In summary, the memory controller handles write commands from the host, performs operations to acquire and transmit the associated data to the non-volatile memory, and follows a specific sequence where the second operation starts after the completion of the first operation.

Abstract

A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to queue write commands received from a host. The commands may include a first write command to write first write data associated with a first stream and a second write command to write second write data associated with a second stream. When the first and second write commands are queued, the memory controller repeatedly performs a sequence of a first operation of acquiring a predetermined amount of the first write data from the host and then transmitting to the non-volatile memory, and a second operation of acquiring the predetermined amount of the second write data from the host and then transmitting to the non-volatile memory. The second operation in the sequence is started after completion of the first operation in the sequence.

NONVOLATILE STORAGE DEVICE, HOST, AND METHOD OF CONTROLLING NONVOLATILE STORAGE DEVICE (17940741)

Inventor Keigo HONDA

Brief explanation

The abstract describes a nonvolatile storage device that consists of a storage medium and a controller. The storage medium is designed to store a key-value pair, where a key and a corresponding value are stored together. The controller is responsible for generating identification information that identifies the key and sending this information to a host device.

Abstract

According to one embodiment, there is provided a nonvolatile storage device including a storage medium and a controller. The storage medium is configured to store a key-value pair in which a key and a value form a pair. The controller is configured to generate identification information identifying the key and transmit the identification information to a host.

MEMORY SYSTEM CONTROLLING NONVOLATILE MEMORY (17943266)

Inventor Tatsuya SASAKI

Brief explanation

The abstract describes a memory system that can connect to multiple hosts. It includes a communication interface and a virtual controller creation unit. The virtual controller creation unit creates a virtual controller when a host is connected to the communication interface. An access management unit manages permission information, which determines which hosts are allowed to access specific namespaces. Based on this permission information, the virtual controller creation unit creates a virtual controller for each host, allowing them to access a nonvolatile memory.

Abstract

According to one embodiment, a memory system includes a communication interface connectable to a plurality of hosts. A virtual controller creation unit creates a virtual controller based on connection of a host to the communication interface. An access management unit manages permission information indicating a correspondence between each of the plurality of namespaces and a host permitted to access the namespace. The virtual controller creation unit create, based on the permission information, a first virtual controller to which a namespace that a first host connected to the communication interface is permitted to access is attached, as a virtual controller to be used by the first host to access a nonvolatile memory.

PAGE BUFFER ENHANCEMENTS (18204858)

Inventor Neil Buxton

Brief explanation

The abstract describes a memory storage system that includes a semiconductor memory device and a controller. The memory device has a memory array and multiple buffers, while the controller is connected to these buffers. The controller can send a command to the memory device to transfer data from the controller to a specific group of buffers. It can also send a command to transfer data from the memory array to the same group of buffers.

Abstract

A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.

MEMORY SYSTEM AND SHIFT REGISTER MEMORY (18309038)

Inventor Yuta AIBA

Brief explanation

This abstract describes a memory system that includes a shift register memory and a controller. The shift register memory stores data in shift strings. The controller is responsible for changing the shift pulse, which is used to read the first data from the shift strings, to a different shift pulse in order to write second data to the shift strings and read it back. The controller also generates likelihood information based on the read result of the second data. Finally, the controller performs soft decision decoding for the first data using the likelihood information.

Abstract

According to one embodiment, a memory system includes a shift register memory and a controller. The shift register memory includes data storing shift strings. The controller changes a shift pulse, which is to be applied to the data storing shift strings from which first data is read by applying a first shift pulse, to a second shift pulse to write second data to the data storing shift strings and to read the second data from the data storing shift strings. The controller creates likelihood information of data read from the data storing shift strings in accordance with a read result of the second data. The controller performs soft decision decoding for the first data using the likelihood information.

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY (18326086)

Inventor Shinichi KANNO

Brief explanation

The abstract describes a memory system controller that organizes a series of write commands in a specific order. These write commands are then transferred from a host's write buffer to an internal buffer in the same order. Finally, the controller writes the transferred data to a specific storage region within the memory system.

Abstract

According to one embodiment, a controller of a memory system reorders a plurality of first write commands in an order in which writing within a first zone is executed sequentially from a next write location within the first zone. The controller transfers a plurality of write data associated with the plurality of first write commands reordered from a write buffer of a host to an internal buffer in a same order as the order of the plurality of first write commands reordered, and writes the plurality of write data transferred to the internal buffer to a first storage region managed as the first zone.

RESOURCE ALLOCATION OF A TASK (17897095)

Inventor Daiki WATANABE

Brief explanation

The abstract describes a device that controls the allocation of resources for a task. The device acquires information about the different parts of the task and their dependencies. It also acquires information about the available resources for the task. The device then calculates a score for different ways of processing the task based on the dependencies and resource allocation. It searches for the best combination of processing steps and outputs the corresponding resource allocation.

Abstract

In a resource allocation control device, a dependency information acquisition unit acquires dependency information indicating subdivided process items that constitute a task and a dependency of the process items. A resource information acquisition unit acquires resource information that is information indicating what kind of resource allocation is possible for the task. A score calculation unit calculates a score for a processing procedure of the process items based on the dependency information, and the resource allocation. A search unit searches for a combination of which the score is excellent. An output unit outputs resource allocation corresponding to the excellent score found by the search unit.

SOFT ERROR DETECTION AND CORRECTION FOR DATA STORAGE DEVICES (18325370)

Inventor Ofir Kanter

Brief explanation

This abstract describes systems and methods for detecting soft errors in non-volatile memory. It explains that the process involves decoding a codeword from the memory to obtain input data, and then determining the validity of the input data using a first signature after processing it through a data path. If the input data is determined to be valid, it is sent to a host.

Abstract

Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, errors introduced after reading a codeword from a non-volatile memory, and before providing data to a host. Embodiments can include decoding the codeword from the non-volatile memory to obtain at least input data, and determining validity of the input data using a first signature after processing the input data through a data path. If it is determined that the input data is valid using the first signature, the input data is sent to a host.

MEMORY SYSTEM AND STORAGE DEVICE (18327165)

Inventor Shogo OCHIAI

Brief explanation

The abstract describes a memory system that includes different types of memory and a processor. The memory system has a nonvolatile memory, a primary cache memory, and a secondary cache memory. The processor uses logical-to-physical address conversion information to access data in the nonvolatile memory. Depending on whether the processor is performing the first processing or the second processing on the nonvolatile memory, it decides to store the corresponding logical-to-physical address conversion information in either the primary cache memory or the secondary cache memory as cache data.

Abstract

A memory system of an embodiment includes a nonvolatile memory, a primary cache memory, a secondary cache memory, and a processor. The processor performs address conversion by using logical-to-physical address conversion information relating to data to be addressed in the nonvolatile memory. Based on whether first processing is performed on the nonvolatile memory or second processing is performed on the nonvolatile memory, the processor controls to store whether the logical-to-physical address conversion information relating to the first processing to be in the primary cache memory as cache data or logical-to-physical address conversion information relating to the second processing to be in the secondary cache memory as cache data.

STORAGE SYSTEM AND PROCESSING METHOD OF STORAGE SYSTEM (17941391)

Inventor Hiroyuki Takatsu

Brief explanation

The abstract describes a storage system that consists of a volatile memory divided into three areas. 

The first area stores a logical address provided by an external device, along with the corresponding physical address of a nonvolatile storage medium and additional information related to the association between the logical and physical addresses.

The second area stores information indicating the states of multiple ranges of the logical address.

The third area stores information indicating the state of a specific range of the logical address, which includes the multiple ranges mentioned in the second area.

Abstract

According to one embodiment, a storage system including a volatile memory with a first area, a second area, and a third area. The first area stores a logical address specified by an external device, a physical address of a nonvolatile storage medium associated with the logical address, and first information related to association between the logical address and the physical address. The second area stores a first number of second information indicating states of the first number of first ranges of the logical address. The third area stores third information indicating a state of a second range of the logical address, which includes the first number of the first ranges.

MEMORY SYSTEM, METHOD OF CONTROLLING MEMORY SYSTEM, AND HOST SYSTEM (17841390)

Inventor Nana KAWAMOTO

Brief explanation

This abstract describes a memory system that consists of a board, a memory controller, and a semiconductor memory. The memory controller can be configured to use different ports as signal ports based on certain conditions. If a signal input to a third port or a command received from outside the memory system meets the first condition, the memory controller will use the first port as the first signal port and the second port as the second signal port. On the other hand, if the signal input or command satisfies the second condition, the memory controller will switch the roles of the first and second ports.

Abstract

According to one embodiment, a memory system includes a board, a memory controller, and a semiconductor memory. When a signal input to a third port or a command received from an outside of the memory system satisfies a first condition, the memory controller is configured to use a first port as a first signal port and to use a second port as a second signal port. When the signal input to the third port or the command received from the outside of the memory system satisfies a second condition, the memory controller is configured to use the first port as the second signal port and to use the second port as the first signal port.

PHOTODETECTION APPARATUS, ELECTRONIC APPARATUS AND PHOTODETECTION METHOD (17942752)

Inventor Masahiro HAYASHI

Brief explanation

The abstract describes an information processing apparatus that is capable of acquiring and processing objective and explanatory variables. The apparatus includes components such as an objective variable acquirer, which collects a multi-dimensional objective variable, and an explanatory variable acquirer, which collects an explanatory variable. The objective variable dimension compressor reduces the number of dimensions of the objective variable. The influence degree calculator then uses the explanatory variable to calculate the influence degree on a new objective variable, which is determined by setting a basis characterizing the objective variable and a coefficient weighting the basis.

Abstract

An information processing apparatus has an objective variable acquirer configured to acquire a multi-dimensional objective variable, an objective variable dimension compressor configured to compress the number of dimensions of the objective variable, an explanatory variable acquirer configured to acquire an explanatory variable, and an influence degree calculator configured to set at least one of a basis characterizing the objective variable and a coefficient weighting the basis as a new objective variable and calculate an influence degree on the new objective variable by using the explanatory variable.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE (17931604)

Inventor Yoshiyuki TAKASU

Brief explanation

This abstract describes a semiconductor device that consists of two conductors, an insulator, and two contacts. The first conductor has a pad portion, which is divided into two sub portions. Each sub portion has two end portions. The first sub portion is next to the second pad portion, while the second sub portion is next to the first insulator. The length of the second sub portion is shorter than the length of the first sub portion.

Abstract

A semiconductor device according to one embodiment includes first and second conductors, a first insulator, and first and second contacts. The first conductor includes a first pad portion. The first pad portion includes first and second sub portions. Each of the first and second sub portions includes one and another end portions. The first sub portion is adjacent to the second pad portion. The second sub portion is adjacent to the first insulator. A length of the second sub portion of the first pad portion is less than a length of the first sub portion of the first pad portion.

SEMICONDUCTOR MEMORY DEVICE (17901590)

Inventor Keita HASEGAWA

Brief explanation

This abstract describes a semiconductor memory device that consists of two chips and multiple bonding pads. The first chip has memory pillars that go through multiple wiring layers in one direction. The second chip is connected to the first chip. The bonding pads are located at the interface between the two chips. Among these bonding pads, there is a first bonding pad that connects a specific memory pillar to one of several transistors, and a second bonding pad that is next to the first bonding pad and connects another memory pillar to one of the transistors. The second memory pillar is not adjacent to the first memory pillar in the specified direction.

Abstract

A semiconductor memory device includes a first chip, a second chip, and a multiple of bonding pads. The first chip has a multiple of memory pillars that penetrate a multiple of wiring layers in a first direction. The second chip is bonded to the first chip. The multiple of bonding pads are provided at a bonding face between the first chip and the second chip. The multiple of bonding pads include a first bonding pad that electrically connects a first memory pillar among the multiple of memory pillars to one of a multiple of transistors, and a second bonding pad that neighbors the first bonding pad when seen from the first direction, and which electrically connects a second memory pillar among the multiple of memory pillars to one of the multiple of transistors. The second memory pillar does not neighbor the first memory pillar when seen from the first direction.

SEMICONDUCTOR DEVICE (17898363)

Inventor Mitsunori MATSUBA

Brief explanation

The abstract describes a semiconductor device that consists of two main components: a semiconductor circuit and a storage circuit. The semiconductor circuit is responsible for carrying out various operations and consumes different amounts of current depending on the operating condition. There are two operating conditions mentioned: the first and the second. Under the first operating condition, the semiconductor circuit consumes a certain amount of current called the first operating current. Under the second operating condition, it consumes a different amount of current called the second operating current.

The storage circuit in the device is used to store the relationship between the operating conditions and the corresponding operating currents. In other words, it keeps track of which operating condition corresponds to which current consumption. This information is important for the proper functioning of the semiconductor device.

Overall, this abstract provides a brief overview of a semiconductor device that has the ability to adjust its current consumption based on different operating conditions, and it includes a storage circuit to store this information.

Abstract

A semiconductor device includes a semiconductor circuit and a storage circuit. The semiconductor circuit consumes a first operating current when operating under a first operating condition and a second operating current when operating under a second operating condition. The second operating current is different from the first operating current. The storage circuit stores a correspondence between the first and second operating currents and the first and second operating conditions, respectively.

MEMORY DEVICE (17807802)

Inventor Hiroshi Maejima

Brief explanation

The abstract describes a structure consisting of multiple conductors arranged along different axes. The first conductor has a memory pillar with a semiconductor and a charge accumulation layer. The second conductor is in contact with the first memory pillar. The third conductor is positioned at a distance from the first conductor and extends along both axes. It contains a second memory pillar with a semiconductor and a charge accumulation layer. The fourth conductor is in contact with the second memory pillar. Finally, the fifth conductor is connected to both the first and second memory pillars.

Abstract

A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.

SEMICONDUCTOR MEMORY DEVICE (17897074)

Inventor Hideyuki KATAOKA

Brief explanation

The abstract describes a semiconductor storage device that has a memory string consisting of memory transistors and a control circuit. The control circuit is designed to respond to specific commands by performing read operations on the memory. 

During the first read operation, the voltage of a particular word line is initially decreased from a higher voltage to a lower voltage, and then increased back to the higher voltage.

If a second command is received during the first read operation, the control circuit will perform a second read operation. In this case, the voltage of a different word line is set to a specific read voltage and then increased to the higher voltage.

The voltages of the word lines that are not selected for either the first or second read operation are maintained at a constant level between these two operations.

Abstract

A semiconductor storage device includes a memory string including memory transistors and a control circuit. The control circuit is configured to in response to a first command, perform a first read operation, and in response to a second command received during the first read operation, perform a second read operation. During the first read operation, a voltage of a first selected word line is decreased from a read pass voltage to a first read voltage and then increased to the read pass voltage. During the second read operation, a voltage of a second word line is set to a second read voltage and then increased to the read pass voltage. Voltages of word lines neither selected during the first nor second read operation are maintained between the first and second read operations.

MEMORY SYSTEM AND REFRESH METHOD (17897758)

Inventor Rei Kasedo

Brief explanation

This abstract describes a memory system that consists of a non-volatile memory with multiple physical blocks. The system also includes a controller that performs a refresh operation on these blocks, which involves rewriting data from one set of blocks to another set of blocks within the memory. During a specific time period from the last write operation to each block in the first set to the completion of the refresh for each block, the controller has the ability to dynamically control when the refresh operation for each block starts.

Abstract

A memory system includes a non-volatile memory provided with a plurality of physical blocks, and a controller configured to execute a refresh for the plurality of blocks of the non-volatile memory to rewrite data of a first plurality of blocks to a second plurality of blocks provided in the plurality of blocks. In a first time period from a previous writing to each block provided in the first plurality of blocks to completion of the refresh for each block, the controller is capable of dynamically controlling a time at which the refresh for each block is started.

CLUSTERING FOR READ THRESHOLDS HISTORY TABLE COMPRESSION IN NAND STORAGE SYSTEMS (17703199)

Inventor Nimrod Bregman

Brief explanation

The abstract describes a flash memory system that includes a flash memory and a circuit for performing operations on the flash memory. The circuit is designed to obtain reference voltages from read samples and multiple sets of reference voltages. It also calculates distances between the obtained reference voltages and each set of reference voltages. The circuit then determines the set of reference voltages that minimizes the distance between the obtained reference voltages and that set. Finally, the circuit uses this set of reference voltages to perform read operations on specific locations in the flash memory.

Abstract

A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain reference voltages from one or more read samples, and a plurality of sets of reference voltages. The circuit may be configured to obtain a plurality of distances, each being a distance between a point corresponding to the obtained reference voltages and a point corresponding to a respective set of reference voltages. The circuit may be configured to determine a first set of reference voltages such that a distance between the point corresponding to the obtained reference voltages and a point corresponding to the first set of reference voltage is a minimum distance of the plurality of distances. The circuit may be configured to perform read operations on locations of the flash memory with the first set of reference voltages.

SEMICONDUCTOR MEMORY DEVICE (17943487)

Inventor Keisuke SUDA

Brief explanation

The abstract describes a semiconductor memory device that consists of memory blocks arranged in one direction and bit lines arranged in another direction. The memory blocks also have layers of conductive material and semiconductor layers that extend in a third direction. Electric charge accumulating films are placed between the conductive layers and the semiconductor layers. The conductive layers and a second conductive layer are separated between the memory blocks.

Abstract

A semiconductor memory device includes memory blocks arranged in a first direction and bit lines that are arranged in a second direction, and are arranged with the memory blocks in a third direction. The memory block includes first conductive layers arranged in the third direction, a second conductive layer disposed on a side opposite to the bit lines in the third direction with respect to the first conductive layers, semiconductor layers that extend in the third direction, are opposed to the first conductive layers, have one ends in the third direction electrically connected to the second conductive layer, and have the other ends in the third direction electrically connected to the bit lines, and electric charge accumulating films disposed between the first conductive layers and the semiconductor layers. The first conductive layers and the second conductive layer are separated between the memory blocks.

SEMICONDUCTOR MEMORY DEVICE (17897089)

Inventor Tomoki NAKAGAWA

Brief explanation

This abstract describes a semiconductor memory device that uses a voltage supply circuit to generate various operation voltages, including a negative voltage. The device also includes control signal lines connected to a memory string, and a row decoder with transistors in the control signal lines. A control circuit is used to control the transistors and supply the negative voltage to the row decoder when the voltage on one of the control signal lines drops to a negative level during a specific time period.

Abstract

A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

SEMICONDUCTOR STORAGE DEVICE (17901239)

Inventor Jun DEGUCHI

Brief explanation

The abstract describes a semiconductor storage device that has a memory cell array with multiple word line groups and blocks. Each word line group has multiple word lines, and each block has multiple memory cells. The memory cells in each block are connected to the word lines in the corresponding word line group. The device also includes a row decoder with multiple word line group decoders, one for each word line group. These decoders are designed to independently drive a word line in one word line group without affecting the word lines in other groups when all word line groups are activated at the same time.

Abstract

A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

SEMICONDUCTOR STORAGE DEVICE (17902725)

Inventor Mina HATAKEYAMA

Brief explanation

The abstract describes a semiconductor storage device that consists of multiple conductive layers and a circuit. The conductive layers are arranged in a specific pattern and separated by a semiconductor layer and a charge storage layer. The circuit is responsible for performing various operations on the device. In a verification operation, the circuit applies different voltages to the conductive layers to ensure the accuracy of a write operation. The abstract does not provide any specific details about the purpose or application of the device.

Abstract

A semiconductor storage device includes a circuit, a first plurality of conductive layers arranged along a first direction, extending along a second direction, and including first through third layers, the first layer between the second and third layers, a second plurality of conductive layers including fourth through sixth layers corresponding to the first through third layers and separated therefrom, a semiconductor layer extending between the first and second pluralities, and a charge storage layer between the semiconductor layer and the first and second pluralities. The circuit applies, in a verification operation of a write operation on the first conductive layer, a verification voltage to the first layer, a voltage smaller than the verification voltage to the fourth layer, a read voltage larger than the verification voltage to the second and fifth conductive layers, and a second voltage smaller than the read voltage to the third or sixth conductive layer.

SEMICONDUCTOR MEMORY DEVICE (17930625)

Inventor Masahiko IGA

Brief explanation

The abstract describes a semiconductor memory device that can perform write and erase operations. During the write operation, a first program voltage is applied to a conductive layer, and this voltage increases with each iteration of a write loop. During the erase operation, a program voltage control operation is performed, and an erase voltage is applied to a wiring. The program voltage control operation includes applying a second program voltage to another conductive layer, and this voltage also increases with each iteration of a write loop. The magnitude of the first program voltage is adjusted based on the magnitude of the second program voltage.

Abstract

A semiconductor memory device performs a write operation and an erase operation. The write operation includes a first program operation that applies a first program voltage to a first conductive layer. The first program voltage increases by a first offset voltage together with an increase in an execution count of a first write loop. An erase operation includes a program voltage control operation and an erase voltage supply operation that applies an erase voltage to a first wiring. The program voltage control operation includes a second program operation that applies a second program voltage to a third conductive layer. The second program voltage increases by a second offset voltage together with an increase in a number of times of execution of a second write loop. A magnitude of the first program voltage is adjusted according to a magnitude of the second program voltage.

MEMORY SYSTEM CONTROLLING NONVOLATILE MEMORY (17902279)

Inventor Kyoka KONISHI

Brief explanation

In this abstract, a memory system is described that includes a controller. The controller monitors the number of program/erase cycles of a block and measures the number of error bits in the data read from memory cells connected to word lines. If the number of error bits exceeds a threshold, the controller identifies a group of word lines that are causing the errors. The controller then selects a parameter set based on the average number of error bits in the identified word line group. This parameter set is used to change the program operation for the identified word line group.

Abstract

According to one embodiment, each time the number of program/erase cycles of a block increases by a first number of times, a controller of a memory system measures the number of error bits of data read from a plurality of memory cells connected to each of a plurality of word lines. The controller identifies a word line group including a word line corresponding to the number of error bits which is greater than a threshold. The controller selects, based on an average number of error bits of the identified word line group, a parameter set to be applied to the identified word line group from a plurality of parameter sets. The controller changes, to the selected parameter set, a parameter set defining a program operation for the identified word line group.

MEMORY SYSTEM (17896828)

Inventor Naoki KIMURA

Brief explanation

The abstract describes a memory system that consists of a connector with two terminals, a non-volatile memory, and a controller. The controller includes a control circuit with two nodes, a first signal line connected to the first terminal, and a second signal line connected to the second terminal. There is also a resistance element that connects the first and second signal lines. The first signal line can be pulled up to either a first or second power level.

Abstract

A memory system includes: a connector including a first terminal and a second terminal, each of which is capable of being connected to a host device; a non-volatile memory; and a controller connected between the connector and the non-volatile memory. The controller includes: a control circuit including a first node and a second node; a first signal line connected between the first terminal and the first node and capable of being pulled up to a first power level or a second power level; a second signal line connected to the second terminal; and a first resistance element including one end connected to the first signal line and the other end connected to the second signal line.

VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE (17901512)

Inventor Takumi FUJIMOTO

Brief explanation

The abstract describes a circuit that generates voltage using multiple charge pumps. These charge pumps are connected to a node called the first node. The circuit also includes a control circuit that determines the number of active charge pumps based on the voltage level at the first node. If the voltage at the first node meets a certain condition within a specific time period, the control circuit activates a certain number of charge pumps. This circuit design allows for efficient voltage generation based on the specific requirements of the system.

Abstract

A voltage generation circuit includes a plurality of charge pumps connected to a first node, and a control circuit that controls the number of active charge pumps among the plurality of charge pumps based on a period in which a voltage of the first node satisfies a condition.

MEMORY SYSTEM AND NONVOLATILE MEMORY (17887985)

Inventor Katsuhiko IWAI

Brief explanation

This abstract describes a memory system that consists of a nonvolatile memory and a control circuit. The nonvolatile memory has multiple word lines, bit lines, and storage elements. The control circuit includes an error correction code (ECC) circuit that detects and fixes data errors in the storage elements. It reads data from the storage elements connected to a specific word line using a certain voltage, and if any errors are detected, it corrects the data using the ECC circuit. The corrected data is then written back to the storage elements on that page.

Abstract

A memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of word lines, a plurality of bit lines, and a plurality of storage elements. The control circuit includes an ECC circuit that detects and corrects a data error stored in the plurality of storage elements, acquires first data by reading data stored in the plurality of storage elements of a page connected to the same word line with a first read voltage, acquires second data obtained by correcting the first data when the first data can be corrected by the ECC circuit, and writes data based on the second data to the plurality of storage elements of the page.

ETCHING METHOD, ETCHING APPARATUS, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF TEMPLATE (17930637)

Inventor Noriko SAKURAI

Brief explanation

The abstract describes a method of etching, which is a process used in manufacturing to selectively remove material from a substrate. In this particular method, there are two processes involved. 

The first process involves either forming a layer on the substrate that contains halogen (a group of elements including chlorine, fluorine, bromine, etc.) or exposing the substrate to a gas atmosphere containing halogen.

The second process involves removing a portion of both the first layer and the substrate underneath it. This is done by supplying the portion of the first layer with ions sourced from a solid material.

Overall, this method provides a way to etch a substrate by using a halogen-containing layer and ions from a solid material.

Abstract

An example of an etching method according to the present disclosure, includes: performing a first process which includes forming a first layer containing halogen or holding the substrate in a gas atmosphere containing halogen; and performing a second process which includes removing a portion of the first layer and a portion of the substrate under the portion of the first layer by supplying the portion of the first layer with ions sourced from a solid material.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ETCHING GAS (18325640)

Inventor Takaya ISHINO

Brief explanation

The abstract describes a method of manufacturing a semiconductor device. The method involves using a specific type of etching gas that contains a chain hydrocarbon compound expressed as CHF, where C represents carbon, H represents hydrogen, and F represents fluorine. The compound has a carbon chain with terminal carbon atoms that are only bonded to fluorine atoms, not hydrogen atoms. The etching gas is used to etch a film in the manufacturing process.

Abstract

In one embodiment, a method of manufacturing a semiconductor device includes etching a film with etching gas that includes a chain hydrocarbon compound expressed as CHFwhere C, H and F respectively denote carbon, hydrogen and fluorine, “x” denotes an integer of three or more, and “y” and “z” respectively denote integers of one or more. Furthermore, the CHFis the chain hydrocarbon compound in which each of terminal carbon atoms on a carbon chain of the chain hydrocarbon compound is bonded only to fluorine atoms out of hydrogen and fluorine atoms.

SUBSTRATE PROCESSING APPARATUS AND METHOD OF SUBSTRATE PROCESSING (17930856)

Inventor Kenji MASUI

Brief explanation

The abstract describes a substrate processing apparatus that is used to hold and process a substrate. The apparatus includes a stage that holds the substrate, a freezing solution supply part that supplies a freezing solution to the substrate, a cooling part that cools the freezing solution to create a freezing film, and a thawing solution supply part that supplies a thawing solution to the substrate to thaw the freezing film. The thawing solution is supplied through a nozzle that extends in a specific direction, with one end of the nozzle located on the outer periphery of the stage and the other end located on the central part of the stage. The thawing solution may have different supply volumes, temperatures, or supply timings between the central part and the outer periphery of the stage.

Abstract

A substrate processing apparatus according to one embodiment includes a substrate holding part having a stage holding the substrate, a freezing solution supply part supplying the freezing solution to the substrate, a cooling part cooling the freezing solution to form a freezing film, and a thawing solution supply part having a nozzle extending in a first direction including a central part of the stage in a plan view, wherein an end and an other end opposite to the end of the nozzle in the first direction are located on an outer periphery outside of the central part, and the thawing solution supply part supplies a thawing solution having at least one of a different supply volume, temperature, or supply timing between the central part and the outer periphery to the substrate to thaw the freezing film.

SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD (17898143)

Inventor Takaumi MORITA

Brief explanation

The abstract describes a substrate processing apparatus that uses a chemical solution to process a substrate. The apparatus includes a tank to hold the solution, a lid to cover the tank, and a holding member to secure the substrate during processing. The lid has a pipe that dispenses gas into the tank, which can be an inert gas to improve the stability of the process. In some cases, the lid may come into direct contact with the chemical solution.

Abstract

According to one embodiment, a substrate processing apparatus includes a processing tank configured to store a chemical solution for processing a substrate by immersion in a chemical solution. The substrate is held by a holding member during the processing. A lid is configured to open and close an upper end portion of the processing tank. The lid has a first bubble dispensing pipe formed or integrated therein. The first bubble dispensing pipe is configured to dispense a gas into the processing tank. A bottom surface side of the lid on a processing tank side may come into direct contact with the chemical solution in some examples. The first bubble dispensing pipe may dispense an inert gas into the chemical solution to improve process stability or the like.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF FORMING PATTERN (17930544)

Inventor Toshiaki Komukai

Brief explanation

This abstract describes a method of manufacturing a semiconductor device. The process involves applying a resin on a first surface of a layer, which has two holes of different depths. A pattern is then formed on the resin, creating a convex part above one of the holes. A protecting layer is applied, exposing a portion of the convex part. The resin in the first hole is removed, while still connected to the convex part. Finally, the first hole is processed to create a third hole that connects with the original hole and has a different depth.

Abstract

A method of manufacturing a semiconductor device includes applying a resin on a first surface of a first layer, the first layer comprising a first hole having a first depth and a second hole having a second depth, forming a pattern on the resin, the pattern comprising a convex part above the first hole a diameter of the convex part being smaller than a diameter of an opening of the first hole, forming a protecting layer exposing a part of the convex part, removing the resin in the first hole, the resin in the hole being connected with the convex part, and processing the first hole to form a third hole connecting with the first hole and having a third depth in the first layer below the first hole.

ELECTRONIC APPARATUS (17900051)

Inventor Kazuyuki MATSUZAKI

Brief explanation

This abstract describes an electronic device that consists of two substrates and an elastic member. The first substrate has a metal member on its surface, while the second substrate is connected to the first substrate and has electronic components mounted on it. The elastic member is in contact with the second substrate or the electronic components and is also in thermal contact with the metal member on the first substrate.

Abstract

An electronic apparatus includes a first substrate, a second substate, and an elastic member. The first substrate has a first surface on which a metal member is provided. The second substrate is coupled to the first substrate above the first surface and on which a plurality of electronic components is mounted. The second substrate has a second surface that faces away from the first surface. The elastic member has an inner surface that contacts the second surface or at least one of the electronic components and an outer surface that faces the first surface and is in thermal contact with the metal member.

SEMICONDUCTOR STORAGE DEVICE (17901812)

Inventor Hiroshi NAKAKI

Brief explanation

The abstract describes a semiconductor storage device that consists of a stacked structure with alternating conductive and insulating layers. There are conductive lines that run in one direction and are arranged in a different direction, and insulators that divide the conductive layers. Columnar bodies are present between the insulators and contain semiconductor bodies that form memory cells. Vias connect the conductive lines to the columnar bodies. The conductive lines and columnar bodies are arranged in a specific order and are electrically connected to each other.

Abstract

A semiconductor storage device includes a stacked body in which conductive and insulating layers are alternately stacked in a first direction, conductive lines extending along a second direction intersecting the first direction and arranged along a third direction intersecting the first and second directions, insulators extending along the first and third directions in the body, arranged along the second direction, and dividing conductive layers, columnar bodies extending along the first direction and arranged along the second direction between insulators, each columnar body including a semiconductor body forming memory cells, and vias each connected between a conductive line and a corresponding columnar body. The conductive lines include first through fourth lines, and the columnar bodies include first through fourth bodies, arranged in this order. When viewed from the first direction, the first through fourth columnar bodies respectively overlap and are electrically connected to the first, third, second, and fourth lines.

SEMICONDUCTOR MEMORY DEVICE (17807195)

Inventor Toru OZAWA

Brief explanation

This abstract describes a semiconductor substrate that has three different circuit regions. These regions are connected by a wiring layer, which includes different groups of wiring. The first group is located at the boundary between the first and second circuit regions, the second group is at the boundary between the second and third circuit regions, and there is a passing wiring group between the two boundary regions. All of these wiring groups are in the same layer. Additionally, there is another wiring in the same layer as the passing wiring group, which is connected to the second circuit region and can be included in either the first or second wiring groups.

Abstract

A semiconductor substrate includes a first circuit region, a second circuit region, and a third circuit region. A wiring layer includes a first boundary region that includes a first boundary between the first and second circuit regions, a second boundary region that includes a second boundary between the second and the third circuit regions, and a passing wiring region between the first and second boundary regions. The first boundary region includes a first wiring group, the second boundary region includes a second wiring group, and the passing wiring region includes a passing wiring group. The first wiring group, the second wiring group, and the passing wiring group are disposed in a same layer. A wiring disposed in a same layer as the passing wiring group and electrically connected to the second circuit region is included in any one of the first and second wiring groups.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (17942005)

Inventor Akifumi GAWASE

Brief explanation

This abstract describes a semiconductor device that consists of multiple conductive layers. The first conductive layers have a certain width in one direction, while the second conductive layer is smaller in either the same direction or a different direction. The second width is larger than the first width. Additionally, there is a third conductive layer in contact with one end of the first conductive layers, and a fourth conductive layer in contact with one end of the second conductive layer. The first conductive layers and the second conductive layer contain a combination of two metals and oxygen. The concentration of the first metal in the first conductive layers is higher than the concentration of the first metal in the second conductive layer.

Abstract

A semiconductor device includes first conductive layers, a width in a first direction thereof being a first width, a second conductive layer arranged with first conductive layers, a smaller one of a width in the first direction thereof and a width in a second direction thereof being a second width that is larger than the first width, a third conductive layer in contact with one end portion of at least one of first conductive layers, and a fourth conductive layer in contact with one end portion of the second conductive layer. The at least one of first conductive layers and the second conductive layer contain a first metal, a second metal, and oxygen (O). A concentration of the first metal of the at least one of first conductive layers is higher than a concentration of the first metal of the second conductive layer.

SEMICONDUCTOR MEMORY DEVICE (17944830)

Inventor Tadayoshi WATANABE

Brief explanation

The abstract describes a semiconductor memory device that consists of multiple layers of memory cells arranged in a specific pattern. These memory layers include memory strings and common wiring connected to these memory strings. The device also includes signal amplifier circuits, additional wirings, and switch transistors for electrical connections. The memory device also has via-contact electrodes that connect to different wirings in different memory layers.

Abstract

A semiconductor memory device includes first memory layers and second memory layers arranged in alternation in a first direction. First memory layers and second memory layers include memory strings and first wirings connected to these memory strings in common. First memory layers and second memory layers include: signal amplifier circuits electrically connected to the first wirings; second wirings connected to the signal amplifier circuits; first switch transistors connected to the second wirings; third wirings electrically connected to the second wirings via the first switch transistors; and fourth wirings electrically connected to the second wirings without via the first switch transistors. The semiconductor memory device includes: first via-contact electrodes extending in the first direction and connected to the third wirings in first memory layers; and second via-contact electrodes extending in the first direction and connected to the fourth wirings in second memory layers.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (17901644)

Inventor Yasunori IWASHITA

Brief explanation

This abstract describes a method of manufacturing a semiconductor device. The method involves creating metal pads on two different substrates and then bonding the substrates together. To address any warpage that may occur on the first substrate, a correction is made during the formation of the metal pads on the second substrate. This correction involves adjusting the position of the metal pad pattern in each region of the second substrate to bring it closer to the center of the substrate in one direction and farther from the center in the other direction.

Abstract

A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.

SEMICONDUCTOR DEVICE (17901770)

Inventor Takuya INATSUKA

Brief explanation

The abstract describes a semiconductor device that has a substrate with a specific region. This region has a part that extends in one direction and several smaller parts that stick out from the larger part in a different direction. The device also has a plug that is placed on the larger part and extends in both the first and a third direction. Additionally, there are multiple gate electrodes that are positioned above the smaller parts and overlap with them in the third direction.

Abstract

A semiconductor device includes a substrate including an element region that includes a first extending portion extending in a first direction and a plurality of first protruding portions protruding from the first extending portion in a second direction intersecting the first direction. The device further includes a first plug provided on the first extending portion and extending in the first direction and in a third direction intersecting the first direction and the second direction. The device further includes a plurality of gate electrodes respectively provided above the plurality of first protruding portions so as to respectively overlap with the plurality of first protruding portions in the third direction.

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE (17890377)

Inventor Nobuhito Ichiki

Brief explanation

The abstract describes a semiconductor memory device that consists of several components. These components include a first wiring, a second wiring, a memory pillar, a semiconductor layer, and a contact plug. 

The second wiring is positioned above the first wiring in a specific direction. The memory pillar is a structure that goes through either a part of the first wiring or a part of the second wiring in that same direction.

Within the memory pillar, there is a semiconductor layer that extends in the same direction. The contact plug, which is made of metal, is located in the memory pillar and has a lower surface. This lower surface is in contact with the semiconductor layer, specifically below the upper surface of the second wiring.

Abstract

A semiconductor memory device includes a first wiring, a second wiring, a memory pillar, a semiconductor layer, and a contact plug. The second wiring is provided above the first wiring in a first direction. The memory pillar penetrating at least one of a portion of the first wiring or a portion of the second wiring in the first direction. The semiconductor layer extends in the first direction provided in the memory pillar. The contact plug contains a metal and has a lower surface provided in the memory pillar, and the lower surface is in contact with the semiconductor layer below an upper surface of the second wiring.

MEMORY DEVICE (17822248)

Inventor Ayako KAWANISHI

Brief explanation

The abstract describes two chips, one with a substrate and two electrodes, and the other with an interconnect layer, two electrodes, and two walls. The electrodes and walls are made of conductive material and surround a specific region. The electrodes and walls are connected in a specific way to the substrate and interconnect layer. The abstract also mentions two ratios: one for the area covered by the electrodes compared to the total region, and another for the area of the electrodes compared to the total region. Both ratios are between 3% and 40%.

Abstract

A first chip includes a substrate, and first and second electrodes in a second region surrounding a first region. A second chip includes an interconnect layer, third and fourth electrodes in the second region, and first and second walls. Each of the first and third electrodes and the first wall includes a conductor surrounding the first region. The first and second electrodes are respectively in contact with the third and fourth electrodes. The first and second walls are in contact with the interconnect layer and are electrically coupled to the substrate via the first and third electrodes and the second and fourth electrodes, respectively. Each of a first ratio of an area covered by the first and second electrodes to the second region and a second ratio of an area of the third and fourth electrodes to the second region is 3% or more and 40% or less.

SEMICONDUCTOR MEMORY DEVICE (17809945)

Inventor Masato SUZUKI

Brief explanation

This abstract describes a semiconductor memory device that consists of two wafers. Each wafer has memory regions and kerf regions. The first wafer has a semiconductor substrate and electrodes, but the electrodes are not present in the first region. The second wafer has layers with conductive layers, and these layers have a third portion in the second region that is farther from the first wafer than a fourth portion. The first and second regions do not overlap.

Abstract

A semiconductor memory device includes a first wafer and a second wafer. The first wafer and the second wafer include memory regions, and kerf regions including a first region and a second region. The first wafer includes a semiconductor substrate, and electrodes. The electrodes are not disposed in the first region, or the semiconductor substrate has a surface on a side of the second wafer including a first portion disposed in the first region and a second portion, and the first portion is farther from the second wafer than the second portion. The second wafer includes layers including conductive layers. At least parts of the layers each include a third portion disposed in the second region and a fourth portion. The third portion is farther than the first wafer than the fourth portion. The first region does not overlap with the second region.

SEMICONDUCTOR MEMORY DEVICE (17813812)

Inventor Nobuaki OKADA

Brief explanation

The abstract describes a semiconductor memory device that consists of two chips connected together using bonding electrodes. The first chip has a semiconductor substrate, while the second chip has multiple layers including conductive layers, semiconductor layers, and wiring layers. The wiring layers include bit lines, wirings, and bonding electrodes. The wirings are divided into two portions, one overlapping with the bit lines and the other overlapping with the bonding electrodes. Some of these wirings also have a third portion that connects the two end portions in a second direction.

Abstract

A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

SEMICONDUCTOR DEVICE, WAFER, AND WAFER MANUFACTURING METHOD (17901448)

Inventor Yasunori IWASHITA

Brief explanation

The abstract describes a semiconductor device that consists of two stacked bodies bonded together. The first stacked body has a pad on its bonding surface, and the second stacked body has a pad that is bonded to the first pad. The dimensions of these pads in different directions are defined as PX, PY, PX, and PY. The abstract states that the dimensions of the pads must satisfy certain equations.

Abstract

A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX and PX respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY and PY respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations () and () below.

SEMICONDUCTOR DEVICE (17930149)

Inventor Nobuaki OKADA

Brief explanation

This abstract describes a device that consists of two chips. The first chip has a via (a hole or channel) on its surface, while the second chip has a via on its surface that overlaps with the first chip in a direction perpendicular to the surface. The first via has two sides, one along a certain direction parallel to the surface and another along a different direction parallel to the surface. The second via also has two sides, one along the second direction and another along the third direction. The first side of the first via intersects with the third side of the second via. The dimensions of the sides vary, with the first side being larger than the second side, and the third side being larger than the fourth side.

Abstract

According to one embodiment, a device includes a first chip including a first via in a first surface; and a second chip including a second via in a second surface and overlapping the first chip in a direction perpendicular to the first surface. The first via includes a first side along a second direction parallel to the first surface, and a second side along a third direction parallel to the first surface, the second via includes a third side along the third direction and a fourth side along the second direction, a dimension of the first side is larger than a dimension of the second side, a dimension of the third side is larger than a dimension of the fourth side. The first via is in contact with the second via so that the first side intersects the third side.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD (17899260)

Inventor Satoshi HONGO

Brief explanation

This abstract describes a semiconductor device that consists of multiple chips stacked on a base substrate. Each chip is separated by a protective film and has a metal pad connected to an interconnection layer. The chips also have electrodes that make contact with each other.

Abstract

According to one embodiment, a semiconductor device includes a base substrate with an interconnection layer and a plurality of chips stacked on the base substrate. A protective film is between each adjacent pair of chips in the plurality of chips stacked on the base substrate and on side surfaces of at least each chip in the plurality other than an uppermost chip in the stacked plurality of chips. A lowermost chip in the stacked plurality of chips has a metal pad electrically connected to the interconnection layer. Each chip in an adjacent pair of chips in the plurality of chips stacked on the base substrate has an electrode contacting an electrode of the other chip in the adjacent pair.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (17940939)

Inventor Masayuki MIURA

Brief explanation

The abstract describes a semiconductor device that consists of a wiring substrate with a wiring layer. It also includes three semiconductor chips stacked on top of each other, with each chip having a pad on its surface. The first chip is closer to the wiring substrate, the second chip is on top of the first chip, and the third chip is on top of the second chip. The chips are connected using resin layers. The device also has two wires - one connecting the first and third pads, and another connecting the second pad and the wiring substrate.

Abstract

A semiconductor device includes: a wiring substrate in which a wiring layer is provided; a first semiconductor chip that is provided above the wiring substrate and on a surface of which a first pad is formed, the surface being on a side closer to the wiring substrate; a second semiconductor chip that is provided on the first semiconductor chip through a first resin layer and on a surface of which a second pad is formed, the surface being on a side opposite the wiring substrate; a third semiconductor chip that is provided on the second semiconductor chip through a second resin layer and on a surface of which a third pad is formed, the surface being on the side closer to the wiring substrate; and a first wire connecting the first pad and the third pad; and a second wire connecting the second pad and the wiring substrate.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD (17821632)

Inventor Soichi HOMMA

Brief explanation

This abstract describes a semiconductor device that includes a first semiconductor element sealed with a first insulating resin. The device also includes a wiring substrate with a pad, and a first wiring that extends from the first semiconductor element towards the wiring substrate. The first wiring has a head portion exposed on the surface of the insulating resin and a column portion connected to the semiconductor element. The device further includes a conductive bonding agent that electrically connects the head portion of the first wiring and the pad on the wiring substrate. The abstract states that the distance from the surface of the wiring substrate to the head portion of the first wiring is shorter than the distance from the surface of the wiring substrate to the insulating resin.

Abstract

A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME (18325769)

Inventor Takeori MAEDA

Brief explanation

This abstract describes a semiconductor device that consists of a support structure with a recess. Within the recess, multiple semiconductor chips are stacked on top of each other. Columnar electrodes extend from the chips towards an opening in the support. A wiring layer is placed over the opening. To protect the chips and electrodes, the recess is filled with an insulating material.

Abstract

According to one or more embodiments, a semiconductor device includes a support having a recess. A plurality of semiconductor chips are stacked on each other in the recess. A plurality of columnar electrodes in the recess extend from the semiconductor chips toward an opening of the support. A wiring layer is disposed over the opening. The recess is filled with an insulating material to cover the semiconductor chips and the columnar electrodes.

SEMICONDUCTOR MEMORY SYSTEM (18203693)

Inventor Hayato MASUBUCHI

Brief explanation

The abstract describes a semiconductor memory system that consists of a substrate, multiple elements, and an adhesive portion. The substrate has a layered structure with wiring patterns and is rectangular in shape. The elements are placed along one side of the substrate's surface layer. The adhesive is used to fill the gaps between the elements and between the elements and the substrate, ensuring that the surfaces of the elements are covered.

Abstract

According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.

SEMICONDUCTOR MEMORY DEVICE (18203952)

Inventor Hiroshi MAEJIMA

Brief explanation

This abstract describes a semiconductor memory device that includes various components such as a substrate, memory cells, bit lines, word lines, and transistors. The memory cells are located above the substrate and are connected to the bit lines and word lines. The transistors are also located on the substrate and are connected to the bit lines and word lines. Overall, this device is designed to store and retrieve data efficiently.

Abstract

A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE (17898224)

Inventor Takuya KIKUCHI

Brief explanation

The abstract describes a method for manufacturing a semiconductor device. It involves forming an electrode layer on a film containing indium and etching parts of the electrode layer that are exposed by a mask layer. A spacer film is then formed to cover the electrode layer and the exposed film. The spacer film on the upper surface of the electrode layer and the exposed film is removed, leaving the spacer film on the side surfaces of the electrode layer. The exposed film is then exposed to a reductive gas plasma to reduce certain parts of it. Finally, these reduced parts of the film are etched using a chemical solution.

Abstract

According to one embodiment, a method for manufacturing a semiconductor device includes forming an electrode layer on a film containing indium and etching portions of the electrode layer left exposed by a mask layer until at least a portion of the film is exposed. A spacer film is formed to cover an upper surface of the electrode layer, side surfaces of the electrode layer, and an exposed upper surface of the film. The spacer film on the upper surface of the electrode layer and the exposed upper surface of the film is removed while leaving the spacer film on the side surfaces of the electrode layer. The exposed upper surface of the film is exposed to a reductive gas plasma to reduce portions of the film. These reduced portions of the film are then etched with a chemical solution.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE (17898893)

Inventor Tomoyuki FUNABASAMA

Brief explanation

This abstract describes a semiconductor device that consists of a transistor. The transistor is made up of several components, including a gate insulating film that is placed on a semiconductor substrate. On top of the gate insulating film, there is a gate electrode that contains germanium, specifically in the upper part of the electrode. The semiconductor substrate also contains a source region and a drain region.

Abstract

A semiconductor device comprises a transistor. The transistor includes: a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film and containing germanium at least in an upper region of the electrode; a source region formed in the semiconductor substrate; and a drain region formed in the semiconductor substrate.

SEMICONDUCTOR INTEGRATED CIRCUIT, TRANSMISSION CIRCUIT, AND CALIBRATION METHOD (17807510)

Inventor Yoshitaka SAMPEI

Brief explanation

This abstract describes a semiconductor integrated circuit that generates an oscillation signal. The circuit includes two output nodes that produce complementary signals, a capacitance circuit, an inductor, two inverters, a bias circuit, and a control circuit. The capacitance circuit consists of two variable capacitance elements connected in series. The control circuit adjusts the bias voltage based on changes in the oscillation frequency when the voltage level of a reference voltage supplied to the capacitance circuit is altered in multiple ways.

Abstract

A semiconductor integrated circuit has a first output node and a second output node that complementarily outputs an oscillation signal, a capacitance circuit, an inductor, a first inverter and a second inverter connected in parallel and in opposite directions, a bias circuit that supplies a bias voltage to the capacitance circuit, and a control circuit that controls the bias circuit and supplies a reference voltage for controlling an oscillation frequency of the oscillation signal to the capacitance circuit. The capacitance circuit includes a first variable capacitance element and a second variable capacitance element connected in series, and the control circuit controls the bias voltage based on a change in an oscillation frequency of the oscillation signal when a voltage level of the reference voltage supplied to a connection node of the first variable capacitance element and the second variable capacitance element is changed in a plurality of ways.

INFORMATION STORAGE DEVICE AND INFORMATION STORAGE SYSTEM (17930198)

Inventor Takeshi ISHIHARA

Brief explanation

The abstract describes a system that generates encrypted data and then deforms the data using a specific key. The deformed data is then stored in a different storage location. This process is done to enhance the security and protection of the data.

Abstract

According to one embodiment, a distribution unit generates a set of first ciphertext fragments based on a first identifier specifying a storage destination of the first ciphertext and a constitution information specifying a constitution of the first ciphertext, generates a deformation command using a second key used for deforming the first ciphertext for at least one fragment belonging to the set of the first ciphertext fragments, and allocates the deformation command to at least one of storage units. A temporary storage unit deforms the first ciphertext fragment by using the second key based on the deformation command, and stores a second ciphertext fragment as a result of the deformation in a non-volatile storage unit instead of the first ciphertext fragment.

SEMICONDUCTOR INTEGRATED CIRCUIT AND SIGNAL PROCESSING DEVICE (17898914)

Inventor Mitsuyuki Ashida

Brief explanation

This abstract describes a semiconductor integrated circuit that includes a waveform shaping circuit. The waveform shaping circuit is designed to receive a signal and enhance either the rising or falling edges of the waveform during a specific period. This enhancement is achieved by operating the circuit with a larger inductance value during the first period. However, during a second period, the circuit operates with a smaller inductance value, and the edges of the waveform are not enhanced.

Abstract

A semiconductor integrated circuit including a waveform shaping circuit is provided. The waveform shaping circuit receives a signal. The waveform shaping circuit operates with a first inductance value in a first period. During the first period, a rising edge or a falling edge of a waveform of the signal is enhanced. The waveform shaping circuit operates with a second inductance value in a second period. During the second period, the rising or falling edges of the waveform is not enhanced. The first inductance value is larger than the second inductance value.

RECEPTION DEVICE AND RECEPTION METHOD (17840684)

Inventor Shinichi IKEDA

Brief explanation

The abstract describes a reception device that receives a data signal representing either a 0 or 1. The device includes an equalizer circuit and a control circuit. The equalizer circuit compares the voltage of the received data signal with a reference voltage at each clock timing. The control circuit is connected to the equalizer circuit and adjusts a tap coefficient, which affects the equalizer circuit's performance, before receiving the data signal. It does this by supplying a different voltage to the equalizer circuit. The control circuit detects the tap coefficient at the boundary where the output value of the equalizer circuit changes from 0 to 1 or vice versa. When the data signal is received, the control circuit sets the detected tap coefficient to the equalizer circuit.

Abstract

A reception device for receiving a data signal representing a data value 0 or 1. The reception device includes an equalizer circuit and a control circuit. The equalizer circuit outputs an output value representing a result obtained by comparing a voltage based on the received data signal and a first voltage as a reference, at each clock timing corresponding to the data signal. The control circuit is connected to the equalizer circuit. The control circuit changes, before the data signal is received, a tap coefficient related to a characteristic of the equalizer circuit in a state in which a second voltage different from the first voltage, instead of the voltage of the data signal, is supplied to the equalizer circuit, to detect an inverted tap coefficient that is the tap coefficient at a boundary where a data value of the output value is inverted. The control circuit sets the inverted tap coefficient to the equalizer circuit at a time of receiving the data signal.

ELECTRONIC DEVICE (17842709)

Inventor Satoru FUKUCHI

Brief explanation

The abstract describes an electronic device that consists of two substrates, conductors, and an electronic component. The first substrate has a connector portion, pad portions, and a transmission line. The second substrate has pad portions as well. The first conductor is connected to one of the pad portions on the first substrate and another pad portion on the second substrate. The second conductor is connected to a different pad portion on the second substrate. The electronic component is connected to the first conductor on one end and the second conductor on the other end.

Abstract

An electronic device according to an embodiment includes first and second substrates, first and second conductors, and an electronic component. The first substrate includes a first connector portion, first pad portions, and a first transmission line. The first pad portions include a second pad portion, the first transmission line coupling the second pad portion and the first connector portion. The second substrate includes third pad portions. The third pad portions include a fourth pad portion and a fifth pad portion. The first conductor is coupled to the fourth pad portion and to the second pad portion. The second conductor is coupled to the fifth pad portion. The first electronic component has one end coupled to the first conductor and other end coupled to the second conductor.

SUBSTRATE AND MEMORY SYSTEM (17898967)

Inventor Kazuyuki Niitsuma

Brief explanation

The abstract describes a substrate that has a connector for a host device. The connector has multiple terminals arranged in one direction. The substrate also has a surface with these terminals and extends in the same direction. The substrate has another surface perpendicular to the first one. On the first surface, there is a protrusion that sticks out in the same direction, and on the opposite surface, there is another protrusion that sticks out in the opposite direction.

Abstract

A substrate includes a first connector fittable to a connector of a host device. The first connector includes a plurality of connector terminals arranged in a first direction and a substrate portion including a surface S provided with the plurality of connector terminals and extending in the first direction. The substrate portion includes a surface S perpendicular to the surface S a first protrusion provided on the surface S and protruding in the first direction, a surface S located on an opposite side of the surface S and a second protrusion provided on the surface S and protruding in a direction opposite to the first direction.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE (17901772)

Inventor Mutsumi OKAJIMA

Brief explanation

This abstract describes a semiconductor device that includes several layers and films. The device consists of an oxide semiconductor layer, a gate electrode, a gate insulating film, a first conductive layer containing a conductive oxide, a second conductive layer containing a metal element, a first protective film in contact with the second conductive layer, and a second protective film in contact with the first conductive layer. The first and second protective films are made of a material with a lower oxygen diffusion coefficient than the second conductive layer.

Abstract

A semiconductor device includes: an oxide semiconductor layer extending in a first direction; a gate electrode overlapping the oxide semiconductor layer in a second direction intersecting the first direction; a gate insulating film provided between the gate electrode and the oxide semiconductor layer; a first conductive layer provided on the oxide semiconductor layer in the first direction and containing a conductive oxide; a second conductive layer provided on the first conductive layer in the first direction and containing a metal element; a first protective film in contact with a side surface of the second conductive layer; and a second protective film in contact with at least a part of a side surface or an upper surface of the first conductive layer. The first protective film and the second protective film each contain a material having an oxygen diffusion coefficient smaller than that of the second conductive layer.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (17844585)

Inventor Yuta KAMIYA

Brief explanation

The abstract describes a method of manufacturing a semiconductor device. The method involves several steps, including the formation of a first film containing oxygen and a second film containing nitrogen. The surfaces of these films are then etched using a substance that contains a halogen. Following this, a third film containing nitrogen is formed on the surfaces of the first and second films. This is achieved by alternating between processes that form the third film and processes that etch the third film using a substance containing a halogen.

Abstract

In one embodiment, a method of manufacturing a semiconductor device includes forming a first film including oxygen. The method further includes forming a second film including nitrogen. The method further includes etching surfaces of the first film and the second film using a substance including a halogen. The method further includes forming a third film including nitrogen on the surfaces of the first film and the second film. The third film is formed by alternately performing first processes and second processes, wherein each of the first processes forms a portion of the third film, and each of the second processes etches a portion of the third film using a substance including a halogen.

SEMICONDUCTOR MEMORY DEVICE (17883453)

Inventor Kojiro SHIMIZU

Brief explanation

The abstract describes a semiconductor memory device that has multiple layers of conductive material stacked on top of each other. There is a bit line located above these conductive layers. Between the conductive layers and the bit line, there is a second conductive layer and a first insulating layer. A pillar extends through the conductive layers and the second conductive layer. At the end of the pillar, there is a via contact that is connected to the bit line. The distance between the upper end of the first insulating layer and the upper surface of the second conductive layer is equal to or greater than the distance between the upper end of the via contact and the upper surface of the second conductive layer.

Abstract

A semiconductor memory device includes first conductive layers stacked in a first direction. A bit line is above the first conductive layers in the first direction. A second conductive layer and a first insulating layer are between the first conductive layers and the bit line. A first pillar extends through the first conductive layers and the second conductive layer. A first via contact connected to an end of the first pillar is on a bit line side. The distance between an upper end of the first insulating layer and an upper surface of the second conductive layer is greater than or equal to the distance between an upper end of the first via contact and the upper surface of the second conductive layer.

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE (17929428)

Inventor Yusuke MORIKAWA

Brief explanation

This abstract describes a semiconductor memory device that consists of a substrate, a layer stack, and a pillar. The layer stack is positioned above the substrate in a specific direction, and the pillar goes through the layer stack in the same direction. The layer stack comprises a first conductor and a first insulator on top of the first conductor in the same direction. The pillar includes a second insulator that extends along the pillar's direction. The second insulator is divided into two parts: a first part located in the same layer as the first conductor and a second part located in the same layer as the first insulator. The first part is thicker than the second part. Additionally, the diameter of the pillar in the layer with the first conductor is larger than the diameter of the pillar in the layer with the first insulator.

Abstract

A semiconductor memory device includes a substrate, a layer stack, and a pillar. The layer stack is in a first direction above the substrate. The pillar penetrates the layer stack in the first direction. The layer stack includes a first conductor and a first insulator on an upper surface of the first conductor along the first direction. The pillar includes a second insulator extending along an extending direction of the pillar. The second insulator includes a first part located in a first layer in which the first conductor is located and a second part located in a second layer in which the first insulator is located. The first part includes a portion thicker than the second part. A diameter of the pillar in the first layer is larger than a diameter of the pillar in the second layer.

SEMICONDUCTOR MEMORY DEVICE (17930236)

Inventor Masahiro KOIKE

Brief explanation

The abstract describes a semiconductor memory device that consists of conductive layers, a semiconductor layer, and a gate insulating film. The device has specific positions and lengths for the conductive layers and the semiconductor layer. The lengths of the semiconductor layer at certain positions are smaller than the lengths at other positions. Additionally, the third length is smaller than the first and second lengths.

Abstract

A semiconductor memory device includes conductive layers, a semiconductor layer opposed to the conductive layers, and a gate insulating film disposed therebetween. When positions corresponding to surfaces on one and the other sides of the first conductive layer and an intermediate position thereof are respectively assumed to be a first position to a third position, when positions corresponding to surfaces on one and the other sides of the second conductive layer and an intermediate position thereof are respectively assumed to be a fourth position to a sixth position, and when lengths of the semiconductor layer at the first position to the sixth position are respectively assumed to be a first length to a sixth length, the first length to the third length are smaller than the fourth length to the sixth length, and the third length is smaller than the first length and the second length.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE (17930889)

Inventor Yuta SAITO

Brief explanation

The abstract describes a semiconductor device that consists of several layers. The device includes a layer made of silicon, a first insulating layer in one direction, a second insulating layer made of silicon and oxygen, a third insulating layer made of a metal element and oxygen, and a conductive layer in another direction. The layers are arranged in a specific pattern and are separated from each other.

Abstract

A semiconductor device of embodiments includes: a semiconductor layer containing silicon (Si); a first insulating layer provided in a first direction of the semiconductor layer; a second insulating layer surrounded by the semiconductor layer in a first cross section perpendicular to the first direction and containing silicon (Si) and oxygen (O); a third insulating layer surrounded by the second insulating layer in the first cross section and containing a metal element and oxygen (O); and a conductive layer surrounded by the first insulating layer in a second cross section perpendicular to the first direction, provided in the first direction of the third insulating layer, and spaced from the semiconductor layer.

SEMICONDUCTOR MEMORY DEVICE (17939344)

Inventor Keiji HOSOTANI

Brief explanation

The abstract describes a semiconductor memory device that consists of a memory cell array and a peripheral circuit. The peripheral circuit includes several components such as first nodes, a charging circuit, a discharging circuit, an address select circuit, first transistors, and amplifier circuits. These components work together to charge and discharge the first nodes, select specific nodes based on an input address signal, and connect the nodes to the charging or discharging circuit. The first transistors are responsible for controlling the current flow between the nodes, and the amplifier circuits are connected to the nodes and via electrodes to amplify the signals.

Abstract

A semiconductor memory device includes a memory cell array and a peripheral circuit. The peripheral circuit includes a plurality of first nodes disposed corresponding to a plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address select circuit that electrically conducts one of the plurality of first nodes with the charging circuit or the discharging circuit in response to an input address signal, a plurality of first transistors each disposed in a current path between two of the plurality of first nodes, and a plurality of amplifier circuits that are disposed corresponding to the plurality of first via electrodes and include input terminals connected to any of the plurality of first nodes and output terminals connected to any of the plurality of first via electrodes.

SEMICONDUCTOR MEMORY DEVICE (18327973)

Inventor Kojiro SHIMIZU

Brief explanation

This abstract describes a semiconductor memory device that consists of different areas and layers. The device includes first and second areas, with the second area having a first contact area divided into three sub-areas. The device also includes multiple conductive layers, specifically first to fourth conductive layers. Each conductive layer has a terrace portion located in either the first or third sub-area of the second area. The purpose of this device is not explicitly stated in the abstract.

Abstract

According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.

MAGNETIC MEMORY (17898255)

Inventor Naoharu SHIMOMURA

Brief explanation

This abstract describes a magnetic memory system that consists of magnetic members and wirings. The magnetic members are arranged in a specific direction, with the wirings positioned on one end of the magnetic members. Some of the magnetic members are located between the wirings. Additionally, there is a second magnetic member that has two parts - one facing the first wiring and connected to a magnetic member, and the other part facing the first wiring but connected to a different magnetic member. A control circuit is used to send a current through one of the wirings when data is being written into the magnetic member located between the wirings.

Abstract

A magnetic memory includes first magnetic members extending along a first direction. First and second wirings are spaced apart from the first magnetic members on a second end side of the first magnetic members. At least one of the first magnetic members is between the first and second wirings in a plan view from the first direction. A second magnetic member has a first portion facing the first wiring and electrically connected to a first magnetic member on one side and a second portion facing the first wiring on an opposite side. The second portion is electrically connected to another first magnetic member. A control circuit causes a current to flow through one of the first wiring or the second wiring when data is written into the first magnetic member that is between the first wiring and the second wiring.

MAGNETIC MEMORY DEVICE (17942365)

Inventor Eiji KITAGAWA

Brief explanation

The abstract describes a magnetic memory device that uses a magnetoresistive effect element. This element consists of two ferromagnetic layers, a layer stack, and three non-magnetic layers. The layer stack is located on one side of the second ferromagnetic layer, opposite to the first ferromagnetic layer. The third non-magnetic layer, which contains a metallic oxide, is positioned on the other side of the layer stack, opposite to the second non-magnetic layer. The layer stack also includes a fourth non-magnetic layer that is in contact with the third non-magnetic layer and contains platinum (Pt).

Abstract

In general, according to one embodiment, a magnetic memory device includes a magnetoresistive effect element. The magnetoresistive effect element includes first to second ferromagnetic layer, a layer stack, and first to third non-magnetic layer. The layer stack is arranged on a side opposite to the first ferromagnetic layer with respect to the second ferromagnetic layer. The third non-magnetic layer is arranged on a side opposite to the second non-magnetic layer with respect to the layer stack and contains a metallic oxide. The layer stack includes a fourth non-magnetic layer being in contact with the third non-magnetic layer and containing platinum (Pt).

STORAGE DEVICE (17899914)

Inventor Kenji FUKUDA

Brief explanation

The abstract describes a storage device that uses a memory cell with a variable resistance element and a switching element. The switching element has snapback current-voltage characteristics, meaning it can handle high currents without damaging the device. The switching element consists of a first conductive layer, a second conductive layer, and a switching layer in between. The switching layer contains at least one switching member and a first insulating layer with high thermal conductivity. The size of the switching member is smaller at the connection surfaces with the first and second conductive layers compared to the connection surface with the variable resistance element.

Abstract

A storage device includes a memory cell including a variable resistance element and a switching element having snapback current-voltage characteristics. The switching element includes a first conductive layer in contact with the variable resistance element, a second conductive layer, and a switching layer provided between the first conductive layer and the second conductive layer. The switching layer includes at least one switching member and a first insulating layer having a thermal conductivity higher than 1.4 W/m/K. A cross-sectional area of the switching member at a connection surface between the switching layer and the first conductive layer and a cross-sectional area of the switching member at a connection surface between the switching layer and the second conductive layer are each smaller than a cross-sectional area at a connection surface between the first conductive layer and the variable resistance element.