Kioxia Corporation patent applications published on December 14th, 2023

Patent applications for Kioxia Corporation on December 14th, 2023

TEST SYSTEM, TEST METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM (18177809)

Main Inventor

Kazuhiko NAKAHARA

Brief explanation

The abstract describes a test system for a device under test (DUT) that includes a test board, a test executable integrated circuit, and a measuring apparatus. The test executable integrated circuit reads firmware stored in the DUT and performs tests on the DUT. The measuring apparatus instructs the test executable integrated circuit to start the test.

• The test system includes a test board, a test executable integrated circuit, and a measuring apparatus.
• The DUT is mounted on the test board.
• The test executable integrated circuit is mounted on the test board and reads firmware stored in the DUT.
• The test executable integrated circuit tests the DUT.
• The measuring apparatus instructs the test executable integrated circuit to start the test.

Potential applications of this technology:

• Electronics manufacturing industry
• Quality control processes
• Testing of various electronic devices

Problems solved by this technology:

• Reducing costs required for tests
• Shortening test time

Benefits of this technology:

• Cost savings in testing processes
• Increased efficiency in testing
• Faster turnaround time for testing electronic devices

Abstract

According to a certain embodiment, the test system includes a first test board, a test executable integrated circuit, and a first measuring apparatus. A device under test (DUT) is mounted on the first test board. The test executable integrated circuit is mounted on the first test board, and is configured to read firmware stored in the DUT in advance and to test the DUT. The first measuring apparatus instructs the test executable integrated circuit to start a test of the DUT. There are provided the test system, the test method, and the non-transitory computer readable medium, capable of reducing costs required for tests and also of shortening test time.

MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM (18457672)

Main Inventor

Yuki SASAKI

Brief explanation

The patent application describes a memory system that includes a non-volatile memory and a data map for managing data validity in the memory. The data map consists of multiple first fragment tables and a second fragment table.

• The memory system includes a non-volatile memory and a data map for managing data validity.
• The data map consists of multiple first fragment tables and a second fragment table.
• Each first fragment table manages the validity of data of a specific size written in a range of physical addresses in the non-volatile memory.
• The second fragment table is used to manage reference destination information for referencing the first fragment tables.

Potential applications of this technology:

• This memory system can be used in various electronic devices that require efficient management of data validity in non-volatile memory.
• It can be applied in storage devices, such as solid-state drives (SSDs), to enhance data management capabilities.

Problems solved by this technology:

• The memory system addresses the challenge of managing data validity in non-volatile memory efficiently.
• It provides a hierarchical approach to manage data validity, allowing for more efficient storage and retrieval of data.

Benefits of this technology:

• The use of multiple fragment tables allows for granular management of data validity, improving overall system performance.
• The hierarchical structure of the fragment tables enables efficient referencing and retrieval of data.
• This memory system enhances the reliability and durability of non-volatile memory by effectively managing data validity.

Abstract

According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.

CIRCUIT NOISE DETERMINATION SYSTEM, CIRCUIT NOISE DETERMINATION METHOD, AND CIRCUIT NOISE DETERMINATION PROGRAM (18178467)

Main Inventor

Hiroaki YAMAOKA

Brief explanation

The abstract describes a circuit noise determination system that analyzes the noise values of circuit elements in a target circuit and identifies elements exceeding a noise upper limit reference value. Here are the key points:

• The system includes a reading unit that reads a netlist representing the target circuit and analysis settings for noise analysis.
• A noise calculation unit calculates the noise values of circuit elements in the target circuit based on the netlist.
• A circuit classification unit identifies and classifies the circuit elements in the target circuit.
• A noise determination unit outputs a notification when elements exceed a noise upper limit reference value, which is set based on pre-defined noise determinations for each circuit classification.

Potential applications of this technology:

• Circuit design and optimization: The system can help circuit designers identify and address noise issues in their designs, leading to improved circuit performance.
• Quality control in manufacturing: By analyzing the noise values of circuit elements, the system can detect any deviations from the desired specifications, allowing for better quality control during the manufacturing process.

Problems solved by this technology:

• Noise analysis complexity: The system simplifies the process of analyzing noise values in a circuit by automating the calculations and providing pre-defined noise determinations.
• Identifying problematic elements: By setting a noise upper limit reference value, the system helps identify circuit elements that exceed acceptable noise levels, allowing for targeted troubleshooting and optimization.

Benefits of this technology:

• Improved circuit performance: By identifying and addressing noise issues, the system helps optimize circuit designs, leading to improved overall performance.
• Time and cost savings: The automated analysis and notification system reduces the time and effort required for manual noise analysis, resulting in cost savings for circuit designers and manufacturers.

Abstract

According to one embodiment, a circuit noise determination system includes a reading unit that reads a netlist representing a target circuit and analysis settings for noise analysis. A noise calculation unit is provided in the system to calculate noise values of circuit elements of in the target circuit according to the netlist along with a circuit classification unit that identifies and classifies circuit element in the target circuit. The system further includes a noise determination unit that outputs a notification regarding elements exceeding a noise upper limit reference value set based on a plurality of noise determinations prepared in advance for each circuit classification.

SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUIT (18239140)

Main Inventor

Hiroshi MAEJIMA

Brief explanation

The patent application describes a memory device with multiple memory cells and sense amplifiers arranged in a specific configuration. 

• The memory device includes multiple memory cells provided above a substrate.
• Each memory cell is connected to a corresponding bit line that extends in a first direction.
• Sense amplifiers are used to sense the voltage of each bit line.
• The sense amplifiers are arranged in groups, with the first and second sense amplifiers belonging to the first group and the third sense amplifier belonging to the second group.
• The first and second sense amplifiers are adjacent to each other and arranged in a second direction that intersects the first direction.
• The first and second sense amplifier groups are adjacent to each other and arranged in the first direction.

Potential applications of this technology:

• Memory devices used in various electronic devices such as computers, smartphones, and tablets.
• Data storage systems in cloud computing and data centers.
• Embedded memory in microcontrollers and other integrated circuits.

Problems solved by this technology:

• Efficient sensing of the voltage in multiple bit lines.
• Improved organization and arrangement of sense amplifiers for better performance and reliability.
• Reduction of signal interference and crosstalk between adjacent bit lines.

Benefits of this technology:

• Higher memory density and capacity.
• Faster and more reliable data access and retrieval.
• Improved overall performance and efficiency of memory devices.
• Enhanced signal integrity and reduced noise interference.

Abstract

A memory device includes a first memory cell provided above a substrate; a first bit line coupled to the first memory cell and extending in a first direction; a first sense amplifier configured to sense a voltage of the first bit line; a second memory cell provided above the substrate; a second bit line adjacent to the first bit line and extending in the first direction, the second bit line being coupled to the second memory cell; a second sense amplifier configured to sense a voltage of the second bit line; and a third memory cell provided above the substrate. A third bit line not adjacent to the second bit line extends in the first direction, and is coupled to the third memory cell; and a third sense amplifier is configured to sense a voltage of the third bit line. The first and second sense amplifiers belong to a first sense amplifier group, are adjacent to each other and are arranged in a second direction intersecting the first direction. The third sense amplifier belongs to a second sense amplifier group. The first and second sense amplifier groups are adjacent to each other and are arranged in the first direction.

MEMORY DEVICE (18061827)

Main Inventor

Masaharu Wada

Brief explanation

The abstract describes a patent application for a circuit configuration involving multiple transistors and inverters. Here is a simplified explanation of the abstract:

• The circuit includes two inverters, each consisting of two transistors.
• The third and fourth nodes are connected to the second and third transistors of the first and second inverters, respectively.
• A sixth transistor is placed between the gate of the fifth transistor and the third node.
• A seventh transistor is placed between the gate of the third transistor and the fourth node.
• An eighth transistor is placed between the gate of the third transistor and the third node.
• A ninth transistor is placed between the gate of the fifth transistor and the fourth node.
• The gates of the eighth and ninth transistors experience a decrease in voltage at a specific time.
• A state is formed with specific voltages applied to the first and second nodes of the first and second inverters at a different time.
• The voltage of the sixth and seventh transistors' gates increases between the first and second times.

Potential applications of this technology:

• Integrated circuits and semiconductor devices
• Digital logic circuits
• Power management systems
• Signal processing circuits

Problems solved by this technology:

• Efficient control of voltage levels in a circuit
• Improved performance and reliability of inverters
• Reduction of power consumption
• Enhanced signal processing capabilities

Benefits of this technology:

• Higher efficiency and reliability in circuit operation
• Lower power consumption and energy savings
• Improved signal processing accuracy and speed
• Increased flexibility in circuit design and integration

Abstract

A first inverter includes second and third transistors coupled at a third node. A second inverter includes fourth and fifth transistors coupled at a fourth node. A sixth transistor is between the fifth transistor's gate and the third node. A seventh transistor is between the third transistor's gate and the fourth node. An eighth transistor is between the third transistor's gate and the third node. A ninth transistor is between the fifth transistor's gate and the fourth node. A voltage of the eighth and ninth transistors' gates lowers at a first time. A state is formed with voltages applied to first and second nodes of the first and second inverters at a second time. A voltage of the sixth and seventh transistors' gates rises between the first and second times.

MEMORY SYSTEM HAVING A NON-VOLATILE MEMORY AND A CONTROLLER CONFIGURED TO SWITCH A MODE FOR CONTROLLING AN ACCESS OPERATION TO THE NON-VOLATILE MEMORY (18455575)

Main Inventor

Riki SUZUKI

Brief explanation

The patent application describes a memory system that includes a non-volatile memory and a controller. The controller can switch between two modes of operation based on a command from a host. The second mode improves data retention compared to the first mode.

• The memory system includes a non-volatile memory and a controller.
• The controller can switch between a first mode and a second mode.
• The switch in modes is triggered by a command from a host.
• The second mode improves data retention compared to the first mode.

Potential Applications

This technology can be applied in various fields where non-volatile memory is used, such as:

• Consumer electronics: Improved data retention in devices like smartphones, tablets, and cameras.
• Automotive: Enhanced memory performance for infotainment systems, navigation systems, and driver assistance systems.
• Industrial: Reliable storage for data logging, control systems, and automation equipment.
• Healthcare: Secure and long-lasting memory for medical devices and patient data.

Problems Solved

The memory system addresses the following problems:

• Data retention: The second mode of operation improves the ability to retain data in the non-volatile memory.
• Host control: The controller allows the host to switch between modes, providing flexibility and adaptability.
• Memory performance: The system ensures better performance and reliability in storing and accessing data.

Benefits

The technology offers several benefits:

• Improved data retention: The second mode enhances the ability to retain data over extended periods.
• Flexibility: The host can control the mode of operation, allowing for customization and optimization.
• Enhanced reliability: The memory system provides a more reliable and stable storage solution.
• Extended lifespan: The improved data retention helps prolong the lifespan of the non-volatile memory.

Abstract

A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.

MEMORY SYSTEM AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY (18177877)

Main Inventor

Masahiro SAITO

Brief explanation

The abstract describes a memory controller that receives data through different reads with varying voltages. The controller instructs the memory to perform additional reads based on the differences between the data values and an expected value. 

• The memory controller receives data through multiple reads with different voltages.
• The controller compares the differences between the data values and an expected value.
• Based on the comparison, the memory controller instructs the memory to perform additional reads with different voltages.

Potential Applications:

• This technology can be applied in various memory systems, such as computer RAM or storage devices.
• It can improve the efficiency and accuracy of data retrieval and storage processes.

Problems Solved:

• The technology addresses the issue of data inconsistency or errors in memory systems.
• It helps optimize the reading process by adjusting voltages based on data differences.

Benefits:

• Improved data accuracy and consistency in memory systems.
• Enhanced efficiency in data retrieval and storage operations.
• Potential for faster and more reliable memory performance.

Abstract

A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE (18173948)

Main Inventor

Tomoya OORI

Brief explanation

The abstract describes a method for manufacturing a semiconductor device. Here is a simplified explanation of the abstract:

• The method starts by forming a mask film that covers part of a first trench in the semiconductor device.
• This mask film divides the first trench into one or more second trenches in the longitudinal direction.
• Next, a first insulating film is filled into the second trenches.
• The mask film is then removed.
• Finally, a second insulating film is formed to cover the entire first trench.

Potential applications of this technology:

• Manufacturing of semiconductor devices such as integrated circuits, transistors, or memory chips.
• This method can be used in various industries that utilize semiconductor devices, including electronics, telecommunications, and computing.

Problems solved by this technology:

• The method provides a way to divide a trench in a semiconductor device using a mask film, allowing for more precise control and customization of the device's structure.
• It enables the formation of insulating films in specific areas of the device, which can improve its performance and functionality.

Benefits of this technology:

• The method allows for the creation of complex trench structures in semiconductor devices, enhancing their capabilities.
• It offers a more efficient and controlled manufacturing process, leading to higher quality and reliability of the devices.
• The use of insulating films can help reduce power consumption and improve insulation properties in the semiconductor device.

Abstract

A method for manufacturing a semiconductor device includes: forming a mask film such that it covers part of a first trench, thereby dividing the first trench in the longitudinal direction to form one or more second trenches; filling a first insulating film into the second trenches; removing the mask film; and forming a second insulating film such that it covers the entire first trench.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME (18182583)

Main Inventor

Shoichi Kabuyanagi

Brief explanation

The abstract describes a semiconductor device that includes various conductors and insulators. Here is a simplified explanation of the abstract:

• The device consists of a first conductor, a first oxide semiconductor, a first insulator, a second conductor, a third conductor, and a fourth conductor.
• The first oxide semiconductor is in contact with one end of the first conductor and extends in a direction perpendicular to the surface of the first conductor.
• The first insulator surrounds the side surface of the first oxide semiconductor.
• The second conductor and the first oxide semiconductor are separated by the first insulator.
• The third conductor is in contact with the other end of the first oxide semiconductor.
• The fourth conductor extends in a direction perpendicular to the first direction and is in contact with the second conductor on the side opposite to the first insulator.
• The second conductor has a higher work function than the fourth conductor.

Potential applications of this technology:

• Integrated circuits
• Transistors
• Memory devices
• Sensors
• Solar cells

Problems solved by this technology:

• Improved performance and efficiency of semiconductor devices
• Enhanced conductivity and functionality
• Reduction of power consumption
• Increased reliability and stability

Benefits of this technology:

• Higher performance and efficiency
• Improved conductivity and functionality
• Lower power consumption
• Enhanced reliability and stability

Abstract

A semiconductor device according to an embodiment includes a first conductor, a first oxide semiconductor, a first insulator, a second conductor, a third conductor, and a fourth conductor. The first oxide semiconductor contacts, at one end, the first conductor, and extends in a first direction intersecting a surface of the first conductor. The first insulator surrounds a side surface of the first oxide semiconductor. The second conductor and the first oxide semiconductor interpose the first insulator therebetween. The third conductor contacts another end of the first oxide semiconductor. The fourth conductor extends in a second direction intersecting the first direction, and contacts a second conductor on a side opposite to the first insulator. The second conductor is of a material with a higher work function than a material of the fourth conductor.

SEMICONDUCTOR DEVICE (18331519)

Main Inventor

Kotaro NODA

Brief explanation

The patent application describes a semiconductor device that includes a semiconductor substrate with two areas, a first area containing memory cells and a second area containing a mark and patterns on its side surfaces.

• The semiconductor device has a semiconductor substrate with two distinct areas.
• The first area of the substrate contains multiple memory cells.
• The second area of the substrate contains a mark with two side surfaces.
• The mark's first side surface intersects with the second side surface.
• The second area also includes patterns on both side surfaces of the mark.

Potential Applications:

• This semiconductor device can be used in various electronic devices such as smartphones, computers, and tablets.
• It can be utilized in memory-intensive applications like data storage devices and servers.
• The device can also find applications in automotive electronics, IoT devices, and other embedded systems.

Problems Solved:

• The inclusion of memory cells in the semiconductor device allows for efficient data storage and retrieval.
• The mark and patterns on the side surfaces provide additional functionality or features to the device.
• The design of the device allows for compact integration of memory cells and other components.

Benefits:

• The semiconductor device offers increased memory capacity and performance.
• The mark and patterns on the side surfaces provide additional functionality or features to the device.
• The compact integration of memory cells and other components saves space in electronic devices.

Abstract

A semiconductor device includes: a semiconductor substrate including a first area and a second area; a plurality of memory cells provided in the first area; a mark provided in the second area and having a first side surface and a second side surface that intersects with the first side surface; and a plurality of patterns provided in the second area and provided on the first side surface and the second side surface.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18330462)

Main Inventor

Haruo MIKI

Brief explanation

The abstract describes a semiconductor device that includes a substrate, two semiconductor chips, a bonding layer, and a member. The first semiconductor chip is placed on the substrate, and the second semiconductor chip is positioned above the first chip, covering it from a perpendicular direction. The bonding layer connects the second surface of the second chip to both the first surface of the substrate and the first chip. The member is located on the outer periphery of the bonding layer.

• The device includes a substrate, two semiconductor chips, a bonding layer, and a member.
• The first semiconductor chip is placed on the substrate.
• The second semiconductor chip is positioned above the first chip, covering it from a perpendicular direction.
• The bonding layer connects the second surface of the second chip to both the first surface of the substrate and the first chip.
• The member is located on the outer periphery of the bonding layer.

Potential Applications

• This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
• It can be utilized in power electronics, automotive applications, and industrial control systems.

Problems Solved

• The device provides a compact and efficient way to stack semiconductor chips, saving space and improving performance.
• It allows for better thermal management and heat dissipation, reducing the risk of overheating.

Benefits

• The compact design of the device allows for more functionality in smaller electronic devices.
• Improved thermal management ensures better reliability and longevity of the semiconductor chips.
• The device offers enhanced performance and efficiency due to the stacked chip configuration.

Abstract

A semiconductor device according to the present embodiment includes a substrate, a first semiconductor chip, a second semiconductor chip, a bonding layer, and a member. The substrate has a first surface. The first semiconductor chip is provided on the first surface. The second semiconductor chip is provided above the first semiconductor chip, has a second surface facing the first surface and the first semiconductor chip, and coats the first semiconductor chip as viewed from a direction substantially perpendicular to the first surface. The bonding layer is provided between the second surface and both the first surface and the first semiconductor chip. The member is provided on at least part of an outer periphery of the bonding layer as viewed from the direction substantially perpendicular to the first surface.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE (18052957)

Main Inventor

Ha HOANG

Brief explanation

The patent application describes a semiconductor device that includes conductors, a semiconductor, an insulator, and an insulation region. The semiconductor contains a metal oxide and is in contact with the conductors. The insulation region is surrounded by the semiconductor and is also in contact with one of the conductors. The concentration of a specific element in the metal oxide is higher in a certain portion of the semiconductor compared to another portion.

• The semiconductor device includes first to third conductors, a semiconductor, a first insulator, and an insulation region.
• The semiconductor contains a metal oxide and is in contact with the first and third conductors.
• The insulation region is surrounded by the semiconductor and is in contact with the first conductor.
• The semiconductor has a first portion, a second portion, and an insulation region in between.
• The concentration of a specific element in the metal oxide is higher in the second portion than in the first portion.

Potential applications of this technology:

• Semiconductor devices and integrated circuits
• Electronics and electrical systems
• Power electronics and energy conversion systems
• Communication systems and devices

Problems solved by this technology:

• Improved performance and efficiency of semiconductor devices
• Enhanced conductivity and functionality of the metal oxide semiconductor
• Better control over the concentration of specific elements in the semiconductor

Benefits of this technology:

• Higher performance and efficiency in semiconductor devices
• Improved conductivity and functionality of the metal oxide semiconductor
• Enhanced control over the concentration of specific elements in the semiconductor

Abstract

In general, according to one embodiment, a semiconductor device includes first to third conductors, a semiconductor, a first insulator, and an insulation region. The semiconductor includes a metal oxide and extends in the first direction to be in contact with the first conductor and the third conductor. The insulation region is surrounded by the semiconductor and extends in the first direction to be in contact with the first conductor. The semiconductor includes a first portion and a second portion defined between the first portion and the insulation region. A concentration of a first element contained in the metal oxide of the semiconductor is higher in the second portion than in the first portion.

SEMICONDUCTOR INTEGRATED CIRCUIT, PHASE LOCKED LOOP (PLL) CIRCUIT, AND SYSTEM (18176339)

Main Inventor

Masatomo EIMITSU

Brief explanation

The patent application describes a semiconductor integrated circuit that includes an oscillation circuit and two current control circuits. The oscillation circuit consists of two series circuits of inverters, each with a different inverter. An oscillation signal is generated from the first series circuit. The first current control circuit regulates the current from a source into the first series circuit based on a synchronized signal. The second current control circuit controls the current from the second series circuit to a reference voltage node based on another synchronized signal.

• The patent application describes a semiconductor integrated circuit with an oscillation circuit and two current control circuits.
• The oscillation circuit consists of two series circuits of inverters, each with a different inverter.
• An oscillation signal is output from the first series circuit.
• The first current control circuit regulates the current from a source into the first series circuit based on a synchronized signal.
• The second current control circuit controls the current from the second series circuit to a reference voltage node based on another synchronized signal.

Potential Applications

This technology could be applied in various electronic devices and systems that require precise control of oscillation signals, such as:

• Communication systems
• Timing circuits
• Microprocessors
• Oscillators

Problems Solved

The patent application addresses the following problems:

• Precise control of current in oscillation circuits
• Synchronization of current control with clock signals
• Efficient utilization of current sources

Benefits

The technology described in the patent application offers several benefits:

• Improved accuracy and stability of oscillation signals
• Enhanced control over current flow in the circuit
• Efficient utilization of current sources
• Synchronization with clock signals for precise timing

Abstract

A semiconductor integrated circuit includes an oscillation circuit and first and second current control circuits. The oscillation circuit includes a first series circuit having inverters, including a first inverter, connected in series and a second series circuit having inverters, including a second inverter, connected in series. An oscillation signal is output from the first series circuit. The first current control circuit is connected between a current source and an output terminal of the first inverter and configured to control a current from the current source into the first series circuit in accordance with a first signal synchronized with a clock signal. The second current control circuit is connected between an output terminal of the second inverter and a reference voltage node and configured to control a current from the second series circuit to the reference voltage node in accordance with a second signal synchronized with the clock signal.

DICTIONARY COMPRESSOR, DATA COMPRESSION DEVICE, AND MEMORY SYSTEM (18118732)

Main Inventor

Keiri NAKANISHI

Brief explanation

The abstract of the patent application describes a dictionary compressor that is used to compress input data. The compressor includes a buffer and a search unit, where the buffer stores the data input to the compressor before processing it.

• The patent application describes a dictionary compressor for compressing input data.
• The compressor includes a buffer and a search unit.
• The buffer is used to store the data input to the compressor prior to processing.
• The search unit is responsible for searching and compressing the input data.
• The invention aims to improve the efficiency of data compression.
• The dictionary compressor can be used in various applications that require data compression.
• The technology solves the problem of efficiently compressing large amounts of data.
• The compressor offers benefits such as improved storage efficiency and faster data transmission.
• The technology can be applied in fields like data storage, communication systems, and data compression algorithms.

Potential Applications

The potential applications of this technology include:

• Data storage systems
• Communication systems
• Data compression algorithms

Problems Solved

This technology solves the following problems:

• Efficient compression of large amounts of data
• Improving storage efficiency
• Faster data transmission

Benefits

The benefits of this technology are:

• Improved storage efficiency
• Faster data transmission
• Enhanced data compression capabilities

Abstract

According to one embodiment, a dictionary compressor for compressing input first data includes a buffer and a search unit. The buffer stores data input to the dictionary compressor prior to the first data.

SEMICONDUCTOR MEMORY DEVICE (18177063)

Main Inventor

Takehiro NAKAI

Brief explanation

The abstract describes a semiconductor memory device that includes various components such as a circuit region, a guard ring line, an element isolation region, and a dummy transistor. 

• The semiconductor memory device is built on a semiconductor substrate with a surface extending in the X and Y directions.
• The circuit region is formed on the semiconductor substrate and has at least one side extending in the Y direction.
• A guard ring line is present, extending along the Y direction and opposing one side of the circuit region in the X direction.
• An element isolation region is formed between the one side of the circuit region and the guard ring line, extending along the Y direction.
• A dummy transistor is placed on the upper surface of the element isolation region.
• The dummy transistor consists of a main interconnection that extends in the Y direction and a branch interconnection that extends from the main interconnection in the X direction.

Potential applications of this technology:

• Semiconductor memory devices are widely used in various electronic devices such as computers, smartphones, and tablets.
• This innovation can improve the performance and efficiency of semiconductor memory devices, leading to better overall performance in electronic devices.

Problems solved by this technology:

• The presence of the guard ring line and element isolation region helps in isolating and protecting the circuit region from external interference or noise.
• The dummy transistor can assist in optimizing the layout and design of the semiconductor memory device, improving its overall functionality.

Benefits of this technology:

• The guard ring line and element isolation region enhance the reliability and stability of the circuit region, reducing the chances of errors or malfunctions.
• The dummy transistor aids in improving the performance and efficiency of the semiconductor memory device, resulting in faster data access and processing speeds.

Abstract

A semiconductor memory device includes: a semiconductor substrate having a surface extending in an X direction and a Y direction; a circuit region formed on the semiconductor substrate and having at least one side extending in the Y direction; a guard ring line extending along the Y direction and opposed to the one side of the circuit region in the X direction; an element isolation region extending along the Y direction and formed between the one side of the circuit region and the guard ring line; and a dummy transistor disposed on an upper surface of the element isolation region. The dummy transistor includes: a main interconnection extending in the Y direction; and a branch interconnection extending from the main interconnection in the X direction.

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE (18456927)

Main Inventor

Shinya ARAI

Brief explanation

The patent application describes a semiconductor memory device that includes a substrate, insulating layer, conductive layer, stacked body, columnar section, and a source layer. 

• The semiconductor memory device includes a substrate, insulating layer, conductive layer, stacked body, columnar section, and a source layer.
• The stacked body consists of multiple electrode layers and insulating layers.
• The columnar section extends through the stacked body and reaches the conductive layer.
• The columnar section includes a channel body and a charge storage film between the channel body and the electrode layers.
• The conductive layer includes a first film with electric conductivity and is in contact with the lower end of the channel body.
• An air gap is provided and covered by the first film.

Potential applications of this technology:

• Memory devices in electronic devices such as smartphones, tablets, and computers.
• Data storage in cloud computing and data centers.
• High-speed data processing in artificial intelligence and machine learning systems.

Problems solved by this technology:

• Improved performance and reliability of semiconductor memory devices.
• Enhanced data storage capacity and speed.
• Reduction in power consumption and heat generation.

Benefits of this technology:

• Increased memory density and storage capacity.
• Faster data access and processing.
• Lower power consumption and improved energy efficiency.

Abstract

According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

SEMICONDUCTOR MEMORY DEVICE (18330515)

Main Inventor

Ryouji MASUDA

Brief explanation

The patent application describes a semiconductor memory device that includes various components such as wirings, a resistance change film, an electrode, and a first film. These components work together to enable the functioning of the memory device.

• The device has a first wiring that extends in one direction and a second wiring that extends in a different direction, intersecting with the first wiring.
• A resistance change film is placed between the first and second wirings. This film contains at least one element from a group including germanium, antimony, and tellurium.
• An electrode is positioned between the resistance change film and the first wiring.
• A first film is selectively placed between the electrode and the first wiring, ensuring contact between the electrode and both the first wiring and the first film.

Potential applications of this technology:

• Memory devices: This semiconductor memory device can be used in various memory applications, such as computer systems, smartphones, and other electronic devices that require data storage.
• Data storage and retrieval: The device enables efficient storage and retrieval of data, allowing for faster and more reliable access to information.

Problems solved by this technology:

• Improved memory performance: The use of the resistance change film and electrode in this device helps enhance the performance of semiconductor memory, enabling faster read and write operations.
• Increased data storage capacity: The design and structure of this memory device allow for higher data storage capacity, addressing the growing need for larger memory capacities in modern electronic devices.

Benefits of this technology:

• Faster data access: The device's design and components enable faster read and write operations, resulting in quicker data access and processing.
• Enhanced memory efficiency: The use of the resistance change film and electrode improves the efficiency of the memory device, allowing for more efficient data storage and retrieval.
• Increased data storage capacity: The design of this memory device enables higher data storage capacity, accommodating the growing demand for larger memory capacities in electronic devices.

Abstract

A semiconductor memory device includes: a first wiring extending in a first direction; a second wiring extending in a second direction that intersects with the first direction; a resistance change film provided between the first wiring and the second wiring and including at least one element selected from a group consisting of germanium, antimony, and tellurium; an electrode provided between the resistance change film and the first wiring; and a first film selectively provided between the electrode and the first wiring, in which the electrode includes a surface in contact with both of the first wiring and the first film.