Kioxia Corporation patent applications on September 26th, 2024
Patent Applications by Kioxia Corporation on September 26th, 2024
Kioxia Corporation: 87 patent applications
Kioxia Corporation has applied for patents in the areas of H10B43/27 (18), G11C16/04 (10), H10B12/00 (9), H01L25/065 (9), H01L23/00 (9) H10B43/27 (12), H10B12/33 (3), H01L25/0657 (2), G06F3/0659 (2), G11C16/0483 (2)
With keywords such as: layer, memory, direction, semiconductor, portion, data, insulating, region, third, and stacked in patent application abstracts.
Patent Applications by Kioxia Corporation
Inventor(s): Sachiko KOBAYASHI of Ota Tokyo (JP) for kioxia corporation, Kazuhiro TAKAHATA of Yokohama Kanagawa (JP) for kioxia corporation, Satoshi MITSUGI of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): B41C1/10, G03F7/00, G06F30/392
CPC Code(s): B41C1/10
Abstract: a pattern design method according to an embodiment is a method to design a pattern of a template used for an imprint process. the imprint process serves to form a predetermined pattern by pressing a shot surface of the template against a surface of a processed layer. the method includes setting an outer edge coverage range corresponding to an outer edge region located a predetermined distance inside an edge of the shot surface of the template. the outer edge coverage range is set to be different from an inner coverage range corresponding to an inner region inside the outer edge region. the method includes designing a pattern in the outer edge region to have a coverage falling within the outer edge coverage range. the method includes designing a pattern in the inner region to have a coverage falling within the inner coverage range.
20240318344. ANODIZATION APPARATUS_simplified_abstract_(kioxia corporation)
Inventor(s): Ryosuke NIWA of Mie Mie (JP) for kioxia corporation, Hisashi OKUCHI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): C25D11/02
CPC Code(s): C25D11/022
Abstract: according to one embodiment, a anodization apparatus includes: a first process tank used for an anodization process on a first portion of a substrate; a second process tank provided inside of the first process tank and used for the anodization process on a second portion of the substrate; a first electrolyte supply unit configured to supply a first electrolyte to the first process tank; a second electrolyte supply unit configured to supply a second electrolyte to the second process tank; a retainer configured to retain the substrate; a first electrode provided above the first process tank and/or the second process tank; and a second electrode provided below the first process tank and the second process tank.
Inventor(s): Yuki OTSUKA of Yokkaichi Mie (JP) for kioxia corporation, Ken HOSHINO of Yokkaichi Mie (JP) for kioxia corporation, Haruko AKUTSU of Yokosuka Kanagawa (JP) for kioxia corporation
IPC Code(s): G01N23/203, G01N23/20025, G01N23/2055, G01N33/204
CPC Code(s): G01N23/203
Abstract: an electron microscope includes an electron beam irradiation unit, a subject holding unit that has a subject installation surface, and a second detection unit that detects an ebsd image. in addition, the electron microscope includes an sem control unit that controls an operation of the subject holding unit, and an ebsd analysis unit that analyzes a crystal structure of a subject based on the ebsd image. the subject holding unit is rotatable around an axis parallel to a direction of irradiation with an electron beam, and is configured such that the subject installation surface is inclinable with respect to a plane perpendicular to the direction of irradiation with the electron beam. the ebsd analysis unit has an mad value calculation unit that calculates a degree of similarity between the ebsd image and a reflector, and the sem control unit controls a rotation operation or an inclination operation of the subject holding unit based on the degree of similarity.
Inventor(s): Yukichi KAMITA of Yokkaichi Mie (JP) for kioxia corporation, Takahiro IWASAKI of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): G03F7/00
CPC Code(s): G03F7/0002
Abstract: an imprint method includes dividing an outer peripheral portion of a patterned surface including a device pattern into a plurality of regions along a circumferential direction. the imprint method includes disposing a dummy pattern in the outer peripheral portion, causing a pattern density of each of the plurality of regions to fall within a first range based on information regarding the device pattern.
20240319587. IMPRINT METHOD AND TEMPLATE FOR IMPRINTING_simplified_abstract_(kioxia corporation)
Inventor(s): Yukichi KAMITA of Yokkaichi Mie (JP) for kioxia corporation, Daisuke KOMATSU of Yokkaichi Mie (JP) for kioxia corporation, Akihiko ANDO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): G03F7/00, G03F7/20
CPC Code(s): G03F7/0002
Abstract: an imprint method forms a pattern by pressing a template including a pattern surface having an uneven portion against an imprinting region of a photocurable imprint material provided on a substrate. the imprint method includes preparing a template having an adjacent light transmission restricting film on a pattern surface, preparing the substrate including the imprint material, and pressing the pattern surface against the imprint material and irradiating the imprint material with light. in irradiating the imprint material with light, the imprint material in the imprinting region and the imprint material raised at an end edge of the pattern surface adjacent to the imprinting region are exposed, the imprint material in the imprinting region is cured and the imprint material is cured while maintaining a height and a shape of the imprint material that is raised at the adjacent position.
Inventor(s): Hirohito TANINO of Suzuka Mie (JP) for kioxia corporation
IPC Code(s): G03F7/16, H01L21/027
CPC Code(s): G03F7/162
Abstract: a hydrophobic treatment device includes a placing table configured to place a substrate; a lid facing the placing table; a first supply port provided in the lid, and configured to discharge a hydrophobic gas with respect to the substrate; a second supply port provided in the lid, and configured to discharge an inert gas with respect to an outer periphery of the substrate; and a first adjustment mechanism configured to adjust a position of the second supply port with respect to the substrate by moving the lid in a radial direction of the substrate.
Inventor(s): Ofir KANTER of Haifa (IL) for kioxia corporation, Avi STEINER of Haifa (IL) for kioxia corporation
IPC Code(s): G06F3/06, G06F11/10, G11C11/56, G11C16/04, G11C16/26
CPC Code(s): G06F3/061
Abstract: disclosed herein are related to a system and a method for adjusting a read voltage threshold to read data from a plurality of memory dies of a nonvolatile memory device. each of the plurality of memory dies comprises a plurality of blocks. a controller in communication with the plurality of memory dies may read, from a first block of the plurality of blocks, data corresponding to a read command received from a host. the controller may determine a bit error rate for the first block based on the data. the controller may update the read voltage threshold for the first block when the bit error rate for the first block exceeds a first error threshold. the read voltage threshold may be stored in the controller.
20240319891. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Shohei ONISHI of Kawasaki (JP) for kioxia corporation, Yohei HASEGAWA of Tokyo (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: according to one embodiment, a memory system includes a first memory region, a second memory region, and a controller. the controller is configured to control coupling between the first memory region and the second memory region at one end and a host device at another, generate first interleave setting information corresponding to the first memory region, select the first memory region based on the first interleave setting information when an access request is received from the host device, and update the first interleave setting information to second interleave setting information corresponding to the second memory region and not corresponding to the first memory region based on an amount of accumulated wear in the first memory region.
Inventor(s): Katsuyuki SHIMADA of Ota Tokyo (JP) for kioxia corporation, Yuki KOMATSU of Yokohama Kanagawa (JP) for kioxia corporation, Yasuyuki USHIJIMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a memory system includes a nonvolatile memory including a plurality of memory cells, and a controller. the controller is configured to perform a read operation to determine a value of multi-bit data stored in each of the memory cells by using a first plurality of read voltages, and perform an estimation of optimum values of the read voltages. the estimation is performed by applying a second plurality of read voltages to the memory cells and obtaining a first string of bit counts. the estimation is performed further by obtaining a second string of differential bit counts, each of which indicates a difference between adjacent bit counts in the first string of bit counts, extracting a part of the differential bit counts from the second string, and estimating the optimum values of the read voltages using the extracted differential bit counts.
Inventor(s): Yousuke KINO of Yokohama Kanagawa (JP) for kioxia corporation, Ryo NOGAMI of Sagamihara Kanagawa (JP) for kioxia corporation, Atsushi TAKAYAMA of Yokohama Kanagawa (JP) for kioxia corporation, Kenji SAKURADA of Yamato Kanagawa (JP) for kioxia corporation, Naoto KUMANO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06, G06F7/58
CPC Code(s): G06F3/0655
Abstract: a memory circuit includes a plurality of storage areas each designated by one of a plurality of addresses. the control circuit stores a plurality of values, all of which are different from each other, in the plurality of storage areas, generates a first random number, obtains a first address that is one of the plurality of addresses using the first random number, reads a first value stored in a first storage area designated by the first address, and reads a second value stored in a second storage area designated by a second address. the second address is an address having the largest value among a range of addresses from which the first address can be obtained. the control circuit writes the second value into the first storage area after reading the first value therefrom. the control circuit outputs the first value as one value of an output random number.
20240319917. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Kiyotaro ITAGAKI of Ota Tokyo (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0658
Abstract: according to one embodiment, a memory system includes semiconductor storage devices and a controller device. each semiconductor storage device includes: first and second signal pads through which command data and address data for instructing one of the semiconductor storage devices to perform a read operation are transmitted; and a status register. a controller device is configured to instruct the one of the semiconductor storage devices to provide a status of the read operation. the one of the semiconductor storage devices is configured to, upon receiving the instruction to provide the status of the read operation, output a ready/busy state stored in the status register through the first signal pad while allowing an input of another command data and another address data through the second signal pad.
Inventor(s): Yongbum PARK of Minato Tokyo (JP) for kioxia corporation, Shinichi MATSUKAWA of Shinagawa Tokyo (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a memory system includes a non-volatile memory with a plurality of pages; and a memory controller configured to write a plurality of data portions into the non-volatile memory, wherein the data portions are specified based on a plurality of write commands received from a host, respectively. the host assigns same setting information to the plurality of write commands. the memory controller is configured to write the plurality of data portions to a plurality of pages, respectively, wherein the plurality of pages correspond to a plurality of continuous addresses among the plurality of pages based on the same setting information.
20240319924. MEMORY SYSTEM AND CONTROL METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Shinichi KANNO of Ota (JP) for kioxia corporation
IPC Code(s): G06F3/06, G06F11/07
CPC Code(s): G06F3/0659
Abstract: according to one embodiment, a memory system is connectable to a host. the memory system includes a nonvolatile memory and a controller. the nonvolatile memory includes a plurality of blocks. the controller is electrically coupled to the nonvolatile memory. the controller controls the nonvolatile memory. when receiving, from the host, a first command for changing a state of an allocated block to a reallocatable state in a case where a second command that is yet to be executed or being executed involving read of data from the allocated block has been received from the host, the controller changes the state of the allocated block to the reallocatable state after the second command is finished.
20240320076. MEMORY SYSTEM AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Hirokazu NAGASHIMA of Fujisawa Kanagawa (JP) for kioxia corporation, Hiroki KOBAYASHI of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F11/07
CPC Code(s): G06F11/076
Abstract: a controller of a memory system executes a first operation on storage regions. the first operation includes (i) acquiring first data based on comparison between a determination voltage and a threshold voltage of each memory cell in a first storage region; (ii) calculating a first fail-bit count of the first data; and (iii) executing or skipping a second operation based on the calculated first fail-bit count. the second operation includes (i) acquiring the second data based on comparison between the determination voltage and the threshold voltage of each memory cell in the first storage region; (ii) calculating a second fail-bit count of the second data; and (iii) updating the determination voltage based on the second fail-bit count.
20240320089. MEMORY SYSTEM AND NONVOLATILE MEMORY_simplified_abstract_(kioxia corporation)
Inventor(s): Daisuke ARIZONO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1044
Abstract: according to one embodiment, a memory system includes a nonvolatile memory that includes memory cells. the nonvolatile memory outputs, to a memory controller, first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data related to the first bit, the second bit, and the third bit, in response to a first command set. the nonvolatile memory outputs, to the memory controller, the first hard bit data, the second hard bit data, the third hard bit data, first soft bit data related to the first bit, second soft bit data related to the second bit, and third soft bit data related to the third bit, in response to a second command set.
20240320091. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Ryo YAMAKI of Yokohama (JP) for kioxia corporation, Masanobu SHIRAKAWA of Chigasaki (JP) for kioxia corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1068
Abstract: a memory system includes a memory and a memory controller. the memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. the first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. the first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. the first bit strings each include a plurality of bits respectively associated with a plurality of rows. the memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.
20240320097. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Riki SUZUKI of Yokohama Kanagawa (JP) for kioxia corporation, Toshikatsu HIDA of Yokohama Kanagawa (JP) for kioxia corporation, Yoshihisa KOJIMA of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F11/14, G06F11/10
CPC Code(s): G06F11/141
Abstract: a memory system includes a nonvolatile memory; and a controller configured to (i) select one of a plurality of read retry processes having different average required times, respectively, based on reliability of a target area of the nonvolatile memory on which a read process is to be executed and (ii) execute the selected read retry process.
Inventor(s): Yoshihiko SHINDO of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F11/16, G06F11/07, G06F11/10
CPC Code(s): G06F11/1658
Abstract: a semiconductor memory device having first and second physical planes each including a plurality of physical blocks of memory cells, includes a first register in which a first address is to be stored, a second register in which a second address associated with the first address is to be stored, a third register in which third addresses are to be stored, and an address registration unit including a first circuit configured to compare the first address stored in the first register with the third addresses and store the first address in the second register as the second address if the first address does not match any of the third addresses, and a second circuit configured to convert the first address into another address that is stored in the second register as the second address when the first address matches one of the third addresses.
Inventor(s): Michiko EMARU of Tokyo (JP) for kioxia corporation, Koji MARUYA of Yokohama (JP) for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: according to one embodiment, a controller, when a first possible storage period corresponding to a first data portion among one or more data portions is equal to or more than a first threshold in one or more possible storage periods, writes the first data portion to one or more second blocks different from one or more first blocks and invalidate the first data portion stored in the one or more first block. when the first possible storage period is less than the first threshold and a period for which the first data portion is stored in the one or more first blocks has reached the first possible storage period, invalidates the first data portion stored in the one or more first blocks.
Inventor(s): Mitsuyo ASANO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F30/20, G06T7/00, G06T7/60, G06T7/73
CPC Code(s): G06F30/20
Abstract: according to one embodiment, there is provided an inspection method. the method includes: extracting a skeleton in a plurality of patterns using data including the plurality of patterns; and inspecting whether a pattern width of the plurality of patterns or an inter-pattern distance between the plurality of patterns, satisfies a criterion based on the extracted skeleton.
20240320762. MANAGEMENT METHOD FOR MANUFACTURING LINE_simplified_abstract_(kioxia corporation)
Inventor(s): Teruhiko TENNOJI of Yokkaichi (JP) for kioxia corporation
IPC Code(s): G06Q50/04, G06Q10/087
CPC Code(s): G06Q50/04
Abstract: according to an embodiment, there is provided a management method for a manufacturing line. the management method includes obtaining a fluctuation characteristic including at least one of an arrival fluctuation characteristic of a lot to a process area, a capability fluctuation characteristic of the process area, or a stay fluctuation characteristic of the lot in the process area in a manufacturing line in which multiple process areas including the process area are arranged, the multiple process areas each including multiple resources. the management method includes obtaining inventory information regarding an inventory to be provided in the process area depending on the fluctuation characteristic.
20240321323. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takeshi SUGIMOTO of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C5/10, G11C11/4076, G11C11/4091, G11C11/4096
CPC Code(s): G11C5/10
Abstract: a memory device includes memory cells for each of layers arranged in a first direction, the memory cells of each layer including groups of memory cells, the memory cells of each group being arranged in a second direction intersecting the first direction, the groups being arranged in a third direction intersecting the first and second directions, first wirings arranged in the third direction in each layer and respectively connected to the groups in each layer, first transistors each connected to a corresponding first wiring, second wirings each connected to the first transistors of a corresponding layer, third wirings each extending in the first direction and connected to a memory cell in each layer, and fourth wirings each extending in the first direction and connected to a gate of a corresponding first transistor in each layer.
20240321326. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Koji TABATA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C7/08, G11C7/10
CPC Code(s): G11C7/08
Abstract: a semiconductor memory device includes a sense amplifier provided between a memory cell array and an input/output circuit. the sense amplifier has a data latch circuit operating at a first operating voltage and having first and second nodes, a multiplexer operating at a second operating voltage, and a sense amplifier unit. the first node is connected to the multiplexer and latches a first voltage supplied from the multiplexer in accordance with data to be latched. the second node is connected to the sense amplifier unit and latches a second voltage having a voltage level that is inverted from that of the first voltage. a high-level of the first voltage latched in the first node is at a voltage level of the second operating voltage at a time the first voltage is supplied from the multiplexer and transitions to a voltage level of the first operating voltage thereafter.
Inventor(s): Kosuke HATSUDA of Bunkyo Tokyo (JP) for kioxia corporation
IPC Code(s): G11C11/16, G11C29/12
CPC Code(s): G11C11/1653
Abstract: according to one embodiment, there is provided a storage device comprising a first memory chip that includes a plurality of first memory cells and that includes a first circuit configured to perform address conversion by using a conversion function; and a second circuit that is connected to the first memory chip and that is configured to set a first parameter for the first memory chip, wherein when a first address is transmitted to the first memory chip from the second circuit, the first address is converted into a second address by the conversion function using the first parameter, and then one of the plurality of first memory cells that corresponds to the second address in the first memory chip is accessed.
20240321335. MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kuniaki SUGIURA of Seoul (KR) for kioxia corporation, Yosuke KOBAYASHI of Seoul (KR) for kioxia corporation, Naoki MATSUSHITA of Seoul (KR) for kioxia corporation, Masayoshi IWAYAMA of Seoul (KR) for kioxia corporation
IPC Code(s): G11C11/16, H10B61/00
CPC Code(s): G11C11/1673
Abstract: a magnetic memory device according to an embodiment includes a magnetic memory device includes first and second interconnect, a memory cell, a transistor, first and second sense amplifiers, and a control circuit. the memory cell includes a magnetoresistive effect element and a selector element. the magnetoresistive effect element and the selector element are coupled in series between the first and second interconnect. in a read operation, the control circuit is further configured to: charge the first interconnect to a first voltage; and discharge the first interconnect via the transistor by applying a second voltage to a gate end of the transistor.
20240321341. STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Katsuaki SAKURAI of Yokohama Kanagawa (JP) for kioxia corporation, Daisuke ARIZONO of Yokohama Kanagawa (JP) for kioxia corporation, Mitsuhiro ABE of Kawasaki Kanagawa (JP) for kioxia corporation, Yasuhiro HIRASHIMA of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C11/4096, G11C11/4074, G11C11/4091
CPC Code(s): G11C11/4096
Abstract: a storage device includes a memory cell array, an input/output circuit, and a logic circuit. the input/output circuit including an input/output signal line through which data to be written into the memory cell array is received and data read from the memory cell array is transmitted. the logic circuit is configured to output a first signal to the input/output circuit. the first signal at an active level enables at least a part of the input/output circuit. the logic circuit includes a latch circuit configured to output a second signal at a level corresponding to a value of latched data. the logic circuit receives third, fourth, and fifth signals from an outside of the storage device via the input/output circuit. the logic circuit outputs a negative logical product of the third signal and a logical sum of at least the second, fourth, and fifth signals as the first signal.
20240321348. MEMORY SYSTEM AND MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Naomi TAKEDA of Yokohama (JP) for kioxia corporation, Masanobu SHIRAKAWA of Chigasaki (JP) for kioxia corporation, Akio SUGAHARA of Yokohama (JP) for kioxia corporation
IPC Code(s): G11C11/56, G06F12/02, G11C16/04, G11C16/08, G11C16/10, G11C16/26
CPC Code(s): G11C11/5628
Abstract: according to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. the controller is configured to write a first portion of each of first data to n-th data from among n�j data with consecutive logical addresses to the n memory cells one by one. the first data has a lowest logical address among the n�j pieces of data. the first data to the n-th data have ascending consecutive logical addresses. the controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
20240321352. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Ryu OGIWARA of Yokohama Kanagawa (JP) for kioxia corporation, Hidehiro SHIGA of Yokohama Kanagawa (JP) for kioxia corporation, Daisaburo TAKASHIMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C13/00
CPC Code(s): G11C13/004
Abstract: according to one embodiment, a device includes: a memory cell coupled to a bit line and configured to store first data including first, second, and third bits; and a sense amplification circuit configured to perform a first comparison between a bit line voltage and a first reference voltage, and a second comparison between the bit line voltage and a second reference voltage lower than the first reference voltage, and to read the first data from the memory cell based on results of the first and second comparisons. the sense amplification circuit is configured to retain second data having a first code in response to the bit line voltage becoming equal to or lower than the first reference voltage during a first period from a start of operation to a first time point, and retain the first data after the first period.
20240321358. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Shigehiro YAMAKITA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): G11C16/04, G11C5/06, G11C16/08, G11C16/10, G11C16/26, H10B41/20, H10B41/35, H10B41/41
CPC Code(s): G11C16/0483
Abstract: a semiconductor device includes a first semiconductor layer, a plurality of first transistors provided on the first semiconductor layer, an insulating layer provided on the first semiconductor layer and covering the plurality of first transistors, a second semiconductor layer provided in the insulating layer, a plurality of second transistors provided on the second semiconductor layer, and a separation layer that extends through the second semiconductor layer between the plurality of second transistors to separate the plurality of second transistors from each other.
20240321359. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yoichi MINEMURA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): G11C16/04, G11C16/10, H10B43/27
CPC Code(s): G11C16/0483
Abstract: a semiconductor memory device includes a stacked body in which conductive layers are stacked with an insulating layer interposed therebetween, a semiconductor film to provide a channel for a plurality of memory cell transistors having gates electrically connected to the conductive layers of the stacked body, respectively, an insulating film extending in the stacking direction between the conductive layers and the semiconductor film, and a control circuit configured to control a program voltage to be applied to a conductive layer electrically connected to a memory cell transistor that is a target of a write operation, and a transfer voltage to be applied to conductive layers electrically connected to other memory cell transistors that are not the target of the write operation, wherein the control circuit is configured to vary the transfer voltage to be applied depending on a number of bits that are being written in the write operation.
20240321360. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Yasuhiro HIRASHIMA of Kawasaki Kanagawa (JP) for kioxia corporation, Masaru KOYANAGI of Tokyo (JP) for kioxia corporation
IPC Code(s): G11C16/10, G11C16/04, G11C16/26
CPC Code(s): G11C16/10
Abstract: according to one embodiment, a semiconductor memory device includes a nonvolatile memory cell, a detection circuit which detects a first voltage and selects one of a first mode and a second mode based on the first voltage, and a transmitting unit which outputs a first signal corresponding to the one of the first mode and the second mode. the detection circuit selects the first mode when the first voltage is equal to or greater than a determination value, and selects the second mode when the first voltage is less than the determination value. the transmitting unit outputs the first signal of a first amplitude in the first mode, and outputs the first signal of a second amplitude that is smaller than the first amplitude in the second mode.
20240321362. MEMORY DEVICE AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Hideki IGARASHI of Yokohama Kanagawa (JP) for kioxia corporation, Takaya IZUMI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/10, G11C16/04, G11C16/34
CPC Code(s): G11C16/102
Abstract: a memory device includes first and second strings including transistors, a first wiring connected to the first string, a second wiring connected to the second string, a third wiring connected to both strings, and a circuit for executing a write operation on a first transistor of the first string and a second transistor of the second string. the operation includes a first operation by which a first voltage is applied to the wirings and a second operation by which a second voltage is applied to gates of the first and second transistors. when a current flows between the first and third wirings but does not flow between the second and third wirings in the first operation, the circuit causes a third voltage to be applied to the first wiring, and causes a fourth voltage higher than the third voltage to be applied to the second wiring in the second operation.
20240321363. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kiichi TACHI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): G11C16/26, G11C5/06, G11C16/04, H01L25/065, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35, H10B80/00
CPC Code(s): G11C16/26
Abstract: a semiconductor memory device includes conductive layers stacked in a stacking direction and extending in a first direction intersecting the stacking direction, semiconductor columns extending in the stacking direction and facing the conductive layers, charge storage films provided between the conductive layers and the semiconductor columns, first and second wirings provided on one side in the stacking direction with respect to the conductive layers, arranged in the first direction, and electrically connected to the semiconductor columns, sense amplifier units electrically connected to the first wirings, and a node electrically and commonly connected to the second wirings. one of the sense amplifier units is electrically connected to k1 number of first wirings (where k1 is an integer of 1 or more). the node is electrically connected to k number of second wirings (where k2 is an integer of 2 or more and is greater than k1).
20240321367. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yoshikazu HARADA of Kawasaki (JP) for kioxia corporation
IPC Code(s): G11C16/34, G11C16/16
CPC Code(s): G11C16/3445
Abstract: according to one embodiment, a semiconductor memory device includes a memory cell including a transistor, an interconnect, and a first circuit. the first circuit performs an erase operation including an erase voltage applying operation of applying an erase voltage between a gate of the transistor and a channel of the transistor via the interconnect, and an erase verify operation of determining a threshold voltage of the memory cell. the first circuit performs a first suspension processing of suspending the erase operation upon receiving a first command during the erase operation. the first circuit performs the erase voltage applying operation or the erase verify operation at the time of resuming the erase operation suspended by the first suspension processing, based on a voltage value of the interconnect at the time of receiving the first command.
20240321374. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Manabu SATO of Chigasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C29/02, G11C16/04, G11C16/08
CPC Code(s): G11C29/024
Abstract: a memory device includes a memory cell array including a block including a first transistor connected to a first select gate line, a second transistor connected to a second select gate line, and a plurality of memory cells connected in series between the first and second transistors and each connected to one corresponding word line of a plurality of word lines, and a row control circuit that outputs a control signal for setting the block to be in a selected state or an unselected state based on a result of decoding an address, stores information indicating whether the block is a non-defective block, and controls an electrical state of the second select gate line independently of the first select gate line based on the control signal and the information.
20240321382. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Junji YAMADA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C29/52, G11C7/10
CPC Code(s): G11C29/52
Abstract: a semiconductor memory device includes a memory cell array configured to store data, and a control circuit configured to control a write operation of writing data into the memory cell array. in the write operation, the control circuit is configured to receive first data and second data including a parity bit, generate a parity bit for the first data, check whether the parity bit and the parity bit match with each other, and write the first data into the memory cell array.
20240321566. MASS SPECTROMETER_simplified_abstract_(kioxia corporation)
Inventor(s): Jun ASAKAWA of Yokkaichi Mie (JP) for kioxia corporation, Haruko AKUTSU of Yokosuka Kanagawa (JP) for kioxia corporation, Yuki OTSUKA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01J49/42, H01J49/00, H01J49/16
CPC Code(s): H01J49/426
Abstract: a mass spectrometer includes a beam irradiator configured to emit an ion beam with pulses to irradiate a beam irradiation region along a surface of a sample; a laser irradiator configured to emit laser light with pulses to irradiate a laser irradiation region above the sample; a mass spectrometry unit configured to detects a mass of ion particles released from the sample by the ion beam and ionized by the laser light; and a controller. the controller is configured to: adjust a position of the laser irradiation region; and adjust the position of the laser irradiation region for each irradiation interval of the laser light.
Inventor(s): Ayata HARAYAMA of Nagoya Aichi (JP) for kioxia corporation, Tsubasa IMAMURA of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H01L21/02, H01L21/311
CPC Code(s): H01L21/02211
Abstract: according to one embodiment, an etching method includes forming a first film on the inner wall surface of the recess by supplying a precursor including silicon to the recess. the etching method includes oxidizing an upper region of the first film on the inner wall surface by an oxidation process, thereby forming an oxidized portion in the upper region. the etching method includes silylating the oxidized portion by supplying a silylating agent to the recess and etching the recess after supplying the silylating agent to increase the depth of the recess.
Inventor(s): Sho KAWADAHARA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/67, H01L21/66, H01L21/687
CPC Code(s): H01L21/67092
Abstract: a semiconductor manufacturing device includes a substrate supporting unit configured to place a bonded substrate including two substrates bonded to each other; an arm portion disposed next to the substrate supporting unit and configured to move toward and from a bonded portion of the bonded substrate; and a separating member provided on an end of the arm portion and configured to separate the two substrates by the arm portion entering the bonded portion, wherein the separating member includes a first inclined face and a second inclined face that extend toward the bonded portion and are respectively extended from end portions of first and second faces of the separating member. the separating member further includes an aperture portion configured to discharge a fluid toward the bonded portion.
Inventor(s): Keisuke ISHIZUKA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L23/528, H10B41/10, H10B41/27, H10B41/40, H10B43/10, H10B43/27, H10B43/40
CPC Code(s): H01L23/5283
Abstract: a semiconductor storage device includes a first stacked body in which first conductive layers and first insulating layers are alternately stacked in a stacking direction, a second stacked body above the first stacked body and in which second conductive layers and second insulating layers are alternately stacked in the stacking direction, a contact that extends in the first and second stacked bodies in the stacking direction and is connected to a first conductive layer. the contact has a first portion that extends in the first stacked body and is connected at a lower end portion thereof to the first conductive layer, a second portion that extends in the second stacked body and is connected to an upper end portion of the first portion, the second portion having a cross-section at a lower end portion thereof that is smaller than a cross-section at the upper end portion of the first portion.
Inventor(s): Miki TOSHIMA of Nagoya Aichi (JP) for kioxia corporation, Sadatoshi MURAKAMI of Yokkaichi Mie (JP) for kioxia corporation, Atsushi OGA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L23/00, H10B80/00
CPC Code(s): H01L24/80
Abstract: according to one embodiment, a method for manufacturing a semiconductor device includes: preparing a first substrate provided with a first film; forming a second film on or above a second substrate; forming a third film on or above the second film; forming a fourth film on or above the third film; forming a stacked body by bonding a main surface of the first film and a main surface of the fourth film; performing irradiation with a laser beam from a side of the second substrate of the stacked body; and separating the second substrate in a state of including at least portion of the second film. the second film and the fourth film each includes a first material. the third film includes a second material different from the first material. the second film and the third film have different composition. the fourth film and the third film have different composition.
Inventor(s): Nobuyuki MOMO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L25/065, H01L23/00, H10B41/10, H10B41/35, H10B43/10, H10B43/35
CPC Code(s): H01L25/0657
Abstract: a semiconductor storage device includes first and second chips. the first chip includes a semiconductor substrate having first and second surfaces intersecting a first direction, and a plurality of transistors provided on the first surface of the semiconductor substrate. the plurality of transistors include first and second transistors adjacent to each other in a second direction intersecting the first direction. the semiconductor substrate includes a first insulating member provided between the first transistor and the second transistor and extending in the first direction from the first surface of the semiconductor substrate to a first position between the first surface and the second surface of the semiconductor substrate, and a second insulating member provided at a position overlapping the first insulating member when viewed in the first direction and extending in the first direction from the second surface of the semiconductor substrate to the first position of the semiconductor substrate.
Inventor(s): Hayato FURUICHI of Yokkaichi Mie (JP) for kioxia corporation, Yuusuke TAKANO of Yokkaichi Mie (JP) for kioxia corporation, Tatsuo MIGITA of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H01L25/065, H01L21/56, H01L21/78, H01L23/00, H01L23/31, H01L23/544
CPC Code(s): H01L25/0657
Abstract: a manufacturing method of a semiconductor device, includes mounting on a first substrate a plurality of second substrates at a predetermined interval, the first substrate including a wiring layer, each of the second substrates including a plurality of semiconductor cells separated from each other by a boundary portion, forming a first recess on the first substrate between two of the second substrates that are adjacent to each other, cutting each of the second substrates along the boundary portion thereof to form a gap and a second recess on the first substrate through the gap, forming a sealing member on the first substrate, and cutting the first substrate together with the sealing member along lines extending along and inside the first and second recesses to individualize the semiconductor cells.
20240321852. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Ryosuke MATSUO of Yokkaichi Mie (JP) for kioxia corporation, Kohei YOSHIMI of Yokkaichi Mie (JP) for kioxia corporation, Hiroomi NAKAJIMA of Setagaya Tokyo (JP) for kioxia corporation
IPC Code(s): H01L25/18, H01L23/00, H01L23/498, H10B80/00
CPC Code(s): H01L25/18
Abstract: a semiconductor storage device according to an embodiment includes a first chip with memory cells, and a second chip that controls operations performed on the memory cells. the first chip includes a stacked body including a plurality of conductive layers stacked in a first direction, a plurality of pillar structures, a plurality of partitions extending within the stacked body in the first direction and a second direction intersecting the first direction, a pad portion, and a connection structure that electrically connects the pad portion and a circuit provided in the second chip, and includes a plate-shaped part extending in the first direction and one of the second direction and a third direction intersecting the first and second directions.
20240321865. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Syunsuke SASAKI of Kamakura Kanagawa (JP) for kioxia corporation, Shouichi OZAKI of Komae Tokyo (JP) for kioxia corporation, Kenichi SUGAWARA of Yokohama Kanagawa (JP) for kioxia corporation, Hiroaki NAKASA of Yokohama Kanagawa (JP) for kioxia corporation, Takeshi MIYABA of Yokohama Kanagawa (JP) for kioxia corporation, Maya OHSAKA of Yokohama Kanagawa (JP) for kioxia corporation, Shoki ITO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L27/02, H01L27/092, H01L29/06, H10B43/35, H10B43/40
CPC Code(s): H01L27/0266
Abstract: a semiconductor device includes a first pad to which a high voltage is to be input, a second pad to which a low voltage is to be input, a third pad to which a ground voltage is to be input, and a protection circuit provided between the first pad and the third pad. the protection circuit includes a first protection element group including a plurality of first transistors arranged in a first direction, a second protection element group including a plurality of second transistors arranged in the first direction and disposed apart from the first protection element group in a second direction orthogonal to the first direction, a guard ring provided around the first and second protection element groups, and an intermediate guard ring provided between the first protection element group and the second protection element group and connected to the third pad via a resistance element.
Inventor(s): Masaya TODA of Yokkaichi Mie (JP) for kioxia corporation, Kazuhiro MATSUO of Kuwana Mie (JP) for kioxia corporation, Kota TAKAHASHI of Yokkaichi Mie (JP) for kioxia corporation, Kenichiro TORATANI of Fujisawa Kanagawa (JP) for kioxia corporation, Shosuke FUJII of Kuwana Mie (JP) for kioxia corporation, Shoichi KABUYANAGI of Yokkaichi Mie (JP) for kioxia corporation, Masayuki TANAKA of Yokohama Kanagawa (JP) for kioxia corporation, Wakako MORIYAMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L29/49, H01L29/66, H01L29/775, H01L29/786, H10B12/00
CPC Code(s): H01L29/4908
Abstract: a semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and including a first region, a second region, and a third region between the first region and the second region; a gate electrode facing the third region; a first insulating layer facing the first region; a second insulating layer facing the second region; and a gate insulating layer between the gate electrode and the oxide semiconductor layer, containing oxygen (o) and at least one metal element selected from a group consisting of al, hf, zr, la, y, zn, in, sn, and ga, and having a chemical composition different from that of the oxide semiconductor layer.
Inventor(s): Takanori AKITA of Yokkaichi Mie (JP) for kioxia corporation, Kotaro NODA of Yokkaichi Mie (JP) for kioxia corporation, Takahiro FUJII of Nagoya Aichi (JP) for kioxia corporation, Kasumi OKABE of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H01L29/786, H10B12/00
CPC Code(s): H01L29/7869
Abstract: a semiconductor device includes a first insulating layer; an oxide semiconductor formed in the first insulating layer, extending in a first direction, and having a first end and a second end; a first electrode including a first metal film that includes a first metal atom, and a first conductive film that is formed between the first metal film and the first end of the oxide semiconductor and includes metal oxide; a second electrode in contact with the second end of the oxide semiconductor; at least a pair of gate electrodes that face each other via an insulating film, and are interposed between the first end and the second end of the oxide semiconductor; and a first structure that is separated from the first electrode in a second direction intersecting the first direction, includes at least the first metal atom, and does not include the metal oxide.
20240322826. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yasuhiro HIRASHIMA of Kawasaki Kanagawa (JP) for kioxia corporation, Masaru KOYANAGI of Ota Tokyo (JP) for kioxia corporation, Yutaka TAKAYAMA of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H03K19/0175, H01L23/538
CPC Code(s): H03K19/017509
Abstract: a semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.
Inventor(s): Mai ARAKI of Kawasaki Kanagawa (JP) for kioxia corporation, Fumihiko TACHIBANA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H03M1/12, H04B1/16
CPC Code(s): H03M1/12
Abstract: according to one embodiment, a receiver device includes: a plurality of converters each configured to sample a digital value from an analog signal, each digital value being sampled at different timing; and a digital signal processor configured to calibrate offsets of the digital values. the plurality of converters include a first converter and a second converter. the digital signal processor is configured to: calibrate a first offset caused in the first converter and a second offset caused in the second converter, in a first operation using a first analog signal; and calibrate a third offset that is caused commonly in the first converter for which the first offset is calibrated and the second converter for which the second offset is calibrated, in a second operation using a second analog signal.
Inventor(s): Riki SUZUKI of Yokohama (JP) for kioxia corporation, Toshikatsu HIDA of Yokohama (JP) for kioxia corporation, Osamu TORII of Setagaya (JP) for kioxia corporation, Hiroshi YAO of Yokohama (JP) for kioxia corporation, Kiyotaka IWASAKI of Kawasaki (JP) for kioxia corporation
IPC Code(s): H03M13/35, G06F3/06, G06F11/10, G11B20/18, G11C7/10, G11C29/04, G11C29/52, H03M13/29
CPC Code(s): H03M13/35
Abstract: according to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. the error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. the controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. the size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
20240323007. MEMORY SYSTEM AND DATA ENCRYPTING METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Tadashi NAGAHARA of Minato Tokyo (JP) for kioxia corporation
IPC Code(s): H04L9/08
CPC Code(s): H04L9/0866
Abstract: a memory system includes a nonvolatile memory and a controller. the controller is configured to generate an encryption key using health data indicating a deterioration state of the nonvolatile memory and time data, encrypt data with the generated encryption key, and write the encrypted data into the nonvolatile memory. the health data may include a total size of data that has been written into the nonvolatile memory or a total size of data that has been read from the nonvolatile memory.
Inventor(s): Hirotaka HIGASHI of Kawasaki (JP) for kioxia corporation, Manabu WATANABE of Kawasaki (JP) for kioxia corporation, Junji WADATSUMI of Tokyo (JP) for kioxia corporation
IPC Code(s): H04L12/40, H04L1/00
CPC Code(s): H04L12/4013
Abstract: according to one embodiment, a communication system includes a host controller, communication devices, and a communication path which couples the host controller and the communication devices in a ring shape and configured to transfer a communication frame. the communication frame includes containers. each of the communication devices includes a first circuit configured to insert and extract first data into and from at least one of the containers, a bus connected to the first circuit, and a second circuit coupled to the bus and configured to transmit and receive second data corresponding to the first data to and from the first circuit. the first data has a first data length which is a fixed length, and the second data has a second data length which is a unit of transfer of the second data and which is a variable length.
20240323066. RECEIVER CIRCUIT AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Takaya YAMAMOTO of Taito Tokyo (JP) for kioxia corporation, Shinsuke FUJII of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): H04L27/01
CPC Code(s): H04L27/01
Abstract: a receiver circuit includes an equalizer configured to process a received signal; a first offset circuit configured to apply a first offset voltage to the processed signal, the first offset voltage having a first polarity; a second offset circuit configured to apply a second offset voltage to the processed signal, the second offset voltage having a second polarity opposite to the first polarity; a first amplification circuit configured to amplify a first output signal provided by the first offset circuit; a second amplification circuit configured to amplify a second output signal provided by the second offset circuit; and a third amplification circuit configured to amplify the processed signal.
20240324112. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takuya OKISHIMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H05K5/00, H01L25/065
CPC Code(s): H05K5/0026
Abstract: a semiconductor storage device includes a circuit board having a first surface and a second surface opposite to each other; an electronic component disposed on the first surface of the circuit board; a plurality of conductive members disposed on the second surface of the circuit board and electrically coupled to the circuit board, wherein the conductive members each include a conductive material; and an information display region provided on the second surface of the circuit board. the information display region has an information display pattern formed of a coating material or the conductive material of the conductive members.
Inventor(s): Hiroto TAKAHASHI of Yokohama Kanagawa (JP) for kioxia corporation, Koichi SATO of Yokohama Kanagawa (JP) for kioxia corporation, Takeaki SERIZAWA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20272
Abstract: a cooling method includes placing a container having thermal conductivity in a cooling tank configured to accommodate liquid refrigerant, accommodating an electronic device to be cooled in the container, and immersion cooling the container using the liquid refrigerant in a state where the electronic device remains separate from the liquid refrigerant.
Inventor(s): Takayuki TSUKAGOSHI of Kawasaki Kanagawa (JP) for kioxia corporation, Daichi SUGAWARA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B10/00, H01L29/786
CPC Code(s): H10B10/125
Abstract: a semiconductor device includes an insulating layer, an oxide semiconductor therein and extending in a first direction, a first electrode on an upper end of the semiconductor, a second electrode on a lower end thereof, and a gate electrode in the insulating layer and surrounding the oxide semiconductor. the semiconductor includes a first portion including the upper end, a second portion between the first portion and the lower end, and a first boundary portion between the first and second portions. an upper end of the first portion has a first diameter, a lower end of the first portion has a second diameter equal to or smaller than the first diameter, a lower end of the first boundary portion has a third diameter smaller than the second diameter, and a lower end of the second portion has a fourth diameter equal to or smaller than the third diameter.
20240324169. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Reiko SUMI of Tokyo (JP) for kioxia corporation, Takashi INUKAI of Yokohama (JP) for kioxia corporation, Tsuneo INABA of Kamakura (JP) for kioxia corporation, Takayuki MIYAZAKI of Tokyo (JP) for kioxia corporation
IPC Code(s): H10B12/00, H01L23/482, H01L23/538
CPC Code(s): H10B12/0335
Abstract: according to one embodiment, a memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.
20240324170. SEMICONDUCTOR DEVICE MANUFACTURING METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Masaya TODA of Yokkaichi Mie (JP) for kioxia corporation, Kazuhiro MATSUO of Kuwana Mie (JP) for kioxia corporation, Ha HOANG of Kuwana Mie (JP) for kioxia corporation, Kota TAKAHASHI of Latham NY (US) for kioxia corporation, Kenichiro TORATANI of Fujisawa Kanagawa (JP) for kioxia corporation, Wakako MORIYAMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/05
Abstract: a semiconductor device manufacturing method includes transferring a substrate including a structure that has a first surface at which indium is exposed, and a second surface at which a metal is exposed, to a chamber of a film forming device, supplying an indium reducing gas to the chamber at a first temperature at which indium is able to transition to a gaseous state, and supplying a film forming gas to the chamber at a second temperature higher than the first temperature to form a first film on the first surface and the second surface, after supplying the reducing gas.
Inventor(s): Tsuyoshi SUGISAKI of Yokkaichi Mie (JP) for kioxia corporation, Takeru MAEDA of Yokkaichi Mie (JP) for kioxia corporation, Kotaro NODA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/05
Abstract: a semiconductor device includes: a first electrode, a first insulating layer, a second insulating layer, and a second electrode arranged in a stacking direction; a gate electrode interposed between the first and second insulating layers in the stacking direction, and extending in a first direction; and a channel layer penetrating the gate electrode and coupled to the first electrode and the second electrode. the channel layer has a first cross-sectional area at a height position of the first insulating layer and a second cross-sectional area at a height position of the gate electrode, the first cross-sectional area is larger than the second cross-sectional area. the gate electrode has a wider width at a penetrating portion of the channel layer than any other portions in a second direction intersecting the stacking direction and the first direction.
20240324174. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takafumi MASUDA of Kawasaki Kanagawa (JP) for kioxia corporation, Mutsumi OKAJIMA of Yokkaichi Mie (JP) for kioxia corporation, Nobuyoshi SAITO of Ota Tokyo (JP) for kioxia corporation, Keiji IKEDA of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/30
Abstract: a semiconductor memory device includes memory layers arranged in a first direction and a via-wiring extending in the first direction. the plurality of memory layers each include a semiconductor layer electrically connected to the via-wiring, a gate electrode opposed to surfaces of the semiconductor layer in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, a wiring disposed on the other side in the second direction with respect to the semiconductor layer, and a connection wiring connected to the gate electrode and the wiring. the connection wiring includes a first part extending in the second direction along a side surface of the gate electrode in the third direction and a second part continuous with the first part, extending in the third direction along a side surface of the wiring in the second direction.
Inventor(s): Kasumi OKABE of Nagoya Aichi (JP) for kioxia corporation, Akifumi GAWASE of Kuwana Mie (JP) for kioxia corporation, Kazuhiro KATONO of Mie Mie (JP) for kioxia corporation, Kotaro NODA of Yokkaichi Mie (JP) for kioxia corporation, Takanori AKITA of Yokkaichi Mie (JP) for kioxia corporation, Takahiro FUJII of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: a semiconductor device includes a first electrode, an oxide semiconductor layer electrically connected to the first electrode and disposed above the first electrode, a gate electrode facing the oxide semiconductor layer with an insulating film interposed therebetween, and a second electrode including a first conductive layer electrically connected to the oxide semiconductor layer and disposed above the oxide semiconductor layer, the first conductive layer containing oxygen, indium, and tin. the second electrode further includes a second conductive layer in contact with the first conductive layer and containing oxygen and a first metal and a third conductive layer in contact with the second conductive layer and containing the first metal.
Inventor(s): Yusuke MUTO of Yokkaichi Mie (JP) for kioxia corporation, Masaya TODA of Yokkaichi Mie (JP) for kioxia corporation, Yuta SAITO of Yokkaichi Mie (JP) for kioxia corporation, Kazuhiro KATONO of Mie Mie (JP) for kioxia corporation, Akifumi GAWASE of Kuwana Mie (JP) for kioxia corporation, Kota TAKAHASHI of Yokkaichi Mie (JP) for kioxia corporation, Kazuhiro MATSUO of Kuwana Mie (JP) for kioxia corporation, Masaya NAKATA of Yokkaichi Mie (JP) for kioxia corporation, Takuma DOI of Yokkaichi Mie (JP) for kioxia corporation, Kenichiro TORATANI of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: the semiconductor device includes a substrate, an oxide semiconductor layer spaced from the substrate in a first direction intersecting with a surface of the substrate, a first wiring opposed to a part of the oxide semiconductor layer, a gate insulating film disposed between the oxide semiconductor layer and the first wiring, a second wiring electrically connected to one end in the first direction of the oxide semiconductor layer, and a first insulating layer disposed on a surface on one side and a surface on the other side in a second direction intersecting with the first direction of the second wiring. the second wiring contains a first metallic element, and the first insulating layer contains the first metallic element and oxygen (o).
Inventor(s): Ken SHIMOMORI of Yokkaichi (JP) for kioxia corporation, Takuya KIKUCHI of Yokkaichi (JP) for kioxia corporation, Ryosuke YAMAMOTO of Nagoya (JP) for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: a semiconductor device of embodiments includes: a first electrode; a second electrode; an oxide semiconductor layer between the electrodes; a gate electrode surrounding the oxide semiconductor layer; a gate insulating layer between the gate electrode and the oxide semiconductor layer and spaced from the first electrode; a first insulating layer between the first electrode and the gate electrode, the gate insulating layer between the first insulating layer and the oxide semiconductor layer; and an intermediate layer between the first electrode and the first insulating layer, including a first region and a second region between the first region and the first insulating layer. the first region contains a first metal element and oxygen, the second region contains a second metal element, and an oxygen concentration in the second region is lower than that in the first region.
20240324195. SEMICONDUCTOR DEVICE MANUFACTURING METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Hakuba KITAGAWA of Yokkaichi (JP) for kioxia corporation, Mariko SUMIYA of Yokkaichi (JP) for kioxia corporation, Kohei NAKAMURA of Yokkaichi (JP) for kioxia corporation, Hiroaki ASHIDATE of Mie (JP) for kioxia corporation, Jun TAKAGI of Yokkaichi (JP) for kioxia corporation, Masayuki FUKUMOTO of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B41/35, H10B41/10, H10B41/20
CPC Code(s): H10B41/35
Abstract: a semiconductor device manufacturing method of embodiments includes: forming an insulating film on an outer peripheral portion of a surface of a first substrate; after forming the insulating film, forming a silicon layer in contact with the surface inside the insulating film; and forming a porous silicon layer by making the silicon layer inside the insulating film porous using an anodization method.
20240324198. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hanae ISHIHARA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/10, H10B41/10, H10B41/27, H10B43/27
CPC Code(s): H10B43/10
Abstract: a device includes a first region including first semiconductor pillars extending through first conductive layers; a second region including second semiconductor pillars extending through second conductive layers; and a third region disposed between the first region and the second region and including insulator columns extending through third conductive layers. the third region includes a fourth region and a fifth region. in the fourth region, one third conductive layer electrically connects one first conductive layer and one second conductive layer to each other, and in the fifth region, one third conductive layer is connected to a contact plug. a first diameter of a first subset of the insulator columns provided in the fourth region is smaller than a second diameter of a second subset of the insulator columns provided in the fifth region.
Inventor(s): Takuya YAMADA of Yokkaichi Mie (JP) for kioxia corporation, Osamu ARISUMI of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L23/00, H01L25/065, H01L25/18, H10B80/00
CPC Code(s): H10B43/27
Abstract: a semiconductor storage device includes a first conductive layer. a stacked body includes a plurality of electrode films and a plurality of first insulating films alternately stacked in a first direction of the first conductive layer, in the first direction. a columnar body includes a semiconductor layer penetrating the stacked body in the first direction. a second insulating film is provided on an inner wall of a slit penetrating the stacked body in the first direction. wiring is provided at an inside of the second insulating film in the slit, is electrically separated from the plurality of electrode films by the second insulating film, and is electrically connected to the first conductive layer. a third insulating film extends in a first surface intersecting the first direction in the first conductive layer. the third insulating film protrudes from the inner wall of the slit toward the wiring.
Inventor(s): Daichi KAWASAKI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a semiconductor storage device includes a stacked body including conductive layers and insulating layers alternately stacked; a first region extending in a first lateral direction and has a width in a second lateral direction; first pillars disposed in a second region on a first side of the first region, and each extending in the stacked body; second pillars disposed in a third region on a second side of the first region, and each extending in the stacked body; a plate-shaped portion disposed in the first region, extending in the first lateral direction, and dividing the stacked body in the second lateral direction; and a semiconductor layer disposed in the first region adjacent to the plate-shaped portion in the second lateral direction, wherein the semiconductor layer has an upper end portion around upper end portions of the first and second pillars, and a lower end portion above an uppermost conductive layer.
Inventor(s): Akihito IKEDO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B43/35
CPC Code(s): H10B43/27
Abstract: a semiconductor storage device includes: a first semiconductor layer; a second semiconductor layer disposed over the first semiconductor layer; a third semiconductor layer disposed over the second semiconductor layer; a stacked body disposed over the first to third semiconductor layers; a pillar penetrating through the stacked body and including a fourth semiconductor layer having a side surface in contact with the second semiconductor layer; and a dividing structure penetrating through the stacked body to reach the first semiconductor layer and separating the stacked body. the dividing structure includes a first portion and a second portion above the first portion, the first portion having a lower portion in contact with the first semiconductor layer and an upper portion located above an upper surface of the second semiconductor layer. a width of the upper portion of the first portion is greater than a width of the lower portion of the first portion.
Inventor(s): Takuya SUZUKI of Kuwana Mie (JP) for kioxia corporation, Soh KOIKE of Tachikawa Tokyo (JP) for kioxia corporation
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a semiconductor memory includes a first stacked body, a first separation portion, a second stacked body, a third stacked body, and a bit line. the first stacked body is configured such that a plurality of first insulating films and a plurality of first conductive films are alternately stacked in a first direction. the first separation portion is adjacent to the first stacked body in a second direction intersecting the first direction. the second stacked body is adjacent to the first separation portion in the second direction. the second stacked body is configured such that a plurality of second insulating films and a plurality of second conductive films are alternately stacked in the first direction. the third stacked body is adjacent to the second stacked body in the second direction. the third stacked body is configured such that the plurality of second insulating films and a plurality of third insulating films are alternately stacked in the first direction. at least one layer of a third conductive film among the plurality of second conductive films has a first portion and a second portion. the second portion is located below the first portion in the first direction and is configured to protrude more into the third stacked body than the first portion in the second direction.
20240324211. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yuto ARINAGA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a semiconductor storage device includes a multiple multilayer films multiple insulating films that each penetrate the multilayer films, multiple memory pillars provided between the insulating films and that respective penetrate a multilayer film, multiple columnar portions with respective cross-sectional areas larger than that of respective memory pillars at certain surfaces.
Inventor(s): Katsuyuki KITAMOTO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B41/40, H10B43/10, H10B43/40
CPC Code(s): H10B43/27
Abstract: a semiconductor storage device includes: a stacked body that has a plurality of conductive layers and a plurality of first insulating layers stacked alternately and includes a first region and a second region; one or more first pillars extending in a stacking direction of the stacked body within the first region of the stacked body; and a second pillar extending in the stacking direction within the second region of the stacked body, in which each of the first and second pillars include a semiconductor layer, a second insulating layer, a third insulating layer, and a fourth insulating layer interposed between the second and third insulating layers, the second insulating layer covers a sidewall of the semiconductor layer, the fourth insulating layer covers a sidewall of the second insulating layer and contains a different material from the second and third insulating layers, the third insulating layer covers a sidewall of the fourth insulating layer, an intersection of at least one of the plurality of conductive layers and the first pillar functions as a memory cell, and the third insulating layer of the second pillar is thicker than the third insulating layer of the first pillar in a plane perpendicular to the stacking direction.
20240324213. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takuya KONNO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B41/27, H10B41/35, H10B43/35
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes a stacked body including a plurality of conductive layers stacked in a first direction, a pillar structure array including a plurality of pillar structures each extending in the first direction in the stacked body and arranged in a second direction and a third direction, the plurality of pillar structures including a plurality of first pillar structures, each of which is a part of a string of memory cell transistors, a first plate-shaped structure extending in the first and second directions in the stacked body, a second plate-shaped structure extending in the first and third directions in the stacked body and disposed along an end portion of the pillar structure array in the second direction, and a support structure extending in the first direction in the stacked body and disposed where the first plate-shaped structure and the second plate-shaped structure intersect.
20240324214. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kenta SHIMOMURA of Kuwana Mie (JP) for kioxia corporation, Karin TAKAYAMA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes a first conductive film, a semiconductor layer on the first conductive film, a stacked body having a plurality of conductive layers insulated from each other and stacked above the semiconductor layer in a stacking direction, a semiconductor film extending through the stacked body and the first conductive film in the stacking direction, an insulating film extending in the stacking direction between the plurality of conductive layers in the stacked body and the semiconductor film, and a second conductive film containing carbon, that is in direct contact with the first conductive film and with one end or a side surface of the semiconductor film.
20240324215. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takashi KURUSU of Yokkaichi Mie (JP) for kioxia corporation, Koji SHIRAI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B43/35
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes a stacked body in which conductive layers and insulating layers are alternately stacked in a first direction, a columnar body in the stacked body and extending in the first direction, and a source line layer. the columnar body includes a core insulating layer, a semiconductor layer surrounding the core insulating layer, and a memory layer surrounding the semiconductor layer. a portion of the source line layer extends in the first direction to be provided in the stacked body, has a side surface in contact with the semiconductor layer and an end face in contact with the core insulating layer, and includes a pointed portion on the end face at an interface of the portion, the core insulating layer, and the semiconductor layer, wherein the end face and the side surface of the semiconductor layer form an acute angle at the pointed portion.
20240324216. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroyuki YAMASAKI of Nagoya Aichi (JP) for kioxia corporation, Masayoshi TAGAMI of Kuwana Mie (JP) for kioxia corporation, Katsuaki ISOBE of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L25/065, H10B43/10, H10B43/35, H10B43/40
CPC Code(s): H10B43/27
Abstract: according to one embodiment, in a semiconductor memory device including a first chip and a second chip. the first chip includes a first stacked body, a first semiconductor film, a second stacked body, a second semiconductor film, a contact plug and a first planar wiring line. the contact plug extends in the third direction between the first stacked body and the second stacked body. the first planar wiring line is disposed on a side opposite to the second chip with respect to the first stacked body, the contact plug, and the second stacked body, the first planar wiring line extending in the first direction and the second direction, covering at least the contact plug, and being connected to the contact plug.
20240324217. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Genki KAWAGUCHI of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L21/768, H01L23/00, H01L23/522, H01L25/18, H10B43/10, H10B80/00
CPC Code(s): H10B43/27
Abstract: a memory device according to an embodiment includes a substrate, first conductive layers, an insulating layer, pillars, and contacts. the first conductive layers are provided above the substrate. the insulating layer is provided above the first conductive layers. the pillars have portions facing the first conductive layers functioning as memory cells. the contacts are connected to the first conductive layers, respectively. each of the first conductive layers has, between itself and the substrate, a terrace portion not overlapping with another first conductive layer. each of the contacts penetrates the insulating layer and is, in a bottom portion thereof, connected to the terrace portion of one first conductive layer among the first conductive layers.
Inventor(s): Yoshikazu HOSOMURA of Kamakura (JP) for kioxia corporation, Go OIKE of Kuwana (JP) for kioxia corporation, Yutaka SHIMIZU of Yokohama (JP) for kioxia corporation, Masaki NAKAMURA of Fujisawa (JP) for kioxia corporation, Hironobu HAMANAKA of Yokkaichi (JP) for kioxia corporation, Hideo WADA of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L23/00, H01L25/065, H01L25/18, H10B80/00
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device comprises: a substrate; a first wiring layer; a second wiring layer provided between the substrate and the first wiring layer; and a memory cell array layer provided between the substrate and the second wiring layer. the memory cell array layer comprises a contact extending in a first direction intersecting with a surface of the substrate. the first wiring layer has a second conductive layer that includes a connecting portion, a pad electrode portion, and a peripheral edge portion. the connecting portion is connected to one end in the first direction of the contact. the second wiring layer has: a first opening which is provided in a region including the connecting portion and the pad electrode portion of the second conductive layer; and a ring-shaped first slit which surrounds the peripheral edge portion of the second conductive layer.
20240324226. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Shoichi MIYAZAKI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/35, G11C16/04, H01L23/528, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27
CPC Code(s): H10B43/35
Abstract: a memory device includes a stacked body including electrode layers and insulating layers; columnar bodies extending through the stacked body; and a contact coupled to a first electrode layer and passing through one or more second electrode layers, the first electrode layer including a first surface and a second surface, the first surface disposed farther away from the second electrode layers than the second surface. the contact includes a first insulating film, a second insulating film, and a metal film. a first end portion of the first insulating film protrudes into the first electrode layer through the second surface. a second end portion of the second insulating film is in contact with a portion of the second surface. a distance t between the first end portion and the first surface is shorter than a distance t between the second end portion and the first surface.
Inventor(s): Hiroyuki YAMASHITA of Yokkaichi Mie (JP) for kioxia corporation, Tatsunori ISOGAI of Yokkaichi Mie (JP) for kioxia corporation, Masaki NOGUCHI of Yokkaichi Mie (JP) for kioxia corporation, Junichi KANEYAMA of Yokkaichi Mie (JP) for kioxia corporation, Shin ISHIMATSU of Yokkaichi Mie (JP) for kioxia corporation, Daisuke NISHIDA of Mie Mie (JP) for kioxia corporation, Tomoyuki TAKEMOTO of Nagoya Aichi (JP) for kioxia corporation, Wataru MATSUURA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/35, H10B43/27
CPC Code(s): H10B43/35
Abstract: a semiconductor device includes a stack including a conductor layer and an insulator layer, a block insulating layer, a channel layer, a charge storage layer provided between the block insulating layer and the channel layer, and a tunnel layer provided between the charge storage layer and the channel layer, where the charge storage layer includes a first charge storage layer containing si, n and at least one of al, mo, nb, hf, zr, ti, b, or p, a second charge storage layer containing si and n, in which si is contained at a second concentration higher than a first concentration that is a concentration of si in the first charge storage layer, and provided between the first charge storage layer and the tunnel layer, and a dielectric layer containing at least one of silicon oxynitride (sion), silicon oxycarbonitride (siocn), or aluminum oxide (alox), and provided between the first charge storage layer and the second charge storage layer.
20240324238. STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Reika TANAKA of Yokohama Kanagawa (JP) for kioxia corporation, Kunifumi SUZUKI of Yokkaichi Mie (JP) for kioxia corporation, Kiwamu SAKUMA of Yokkaichi Mie (JP) for kioxia corporation, Yoko YOSHIMURA of Yokkaichi Mie (JP) for kioxia corporation, Takamasa HAMAI of Nagoya Aichi (JP) for kioxia corporation, Kensuke OTA of Yokohama Kanagawa (JP) for kioxia corporation, Yusuke HIGASHI of Zushi Kanagawa (JP) for kioxia corporation, Yoshiaki ASAO of Kawasaki Kanagawa (JP) for kioxia corporation, Masamichi SUZUKI of Koto Tokyo (JP) for kioxia corporation
IPC Code(s): H10B53/30
CPC Code(s): H10B53/30
Abstract: a storage device includes a first electrode, a second electrode, a first dielectric layer between the first and second electrodes and including oxygen and at least one of hafnium and zirconium, a second dielectric layer between the first electrode and the first dielectric layer, and an intermediate region between the first and second dielectric layers and in which a plurality of metallic portions are provided.
20240324241. MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Masatoshi YOSHIKAWA of Setagaya Tokyo (JP) for kioxia corporation, Tian LI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B61/00, H10N50/01, H10N50/20
CPC Code(s): H10B61/00
Abstract: according to one embodiment, there is provided a magnetic memory device including a first conductive layer; and a first magnetoresistive effect element and a second magnetoresistive effect element that each extends in a first direction, are provided apart from each other in a second direction crossing the first direction, and are each in contact with the first conductive layer, wherein the first conductive layer includes a first portion that does not overlap with any of the first magnetoresistive effect element and the second magnetoresistive effect element when viewed in the first direction, a second portion that overlaps with a central region of the first magnetoresistive effect element when viewed in the first direction, and a third portion that overlaps with an edge region of the first magnetoresistive effect element when viewed in the first direction.
20240324242. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kazuya SAWADA of Seoul (KR) for kioxia corporation, Toshihiko NAGASE of Seoul (KR) for kioxia corporation, Kenichi YOSHINO of Seongnam-si Gyeonggi-do (KR) for kioxia corporation, Hyungjun CHO of Seoul (KR) for kioxia corporation, Naoki AKIYAMA of Seoul (KR) for kioxia corporation, Takuya SHIMANO of Seoul (KR) for kioxia corporation
IPC Code(s): H10B61/00, H10N50/10, H10N50/80
CPC Code(s): H10B61/10
Abstract: according to one embodiment, a memory device includes a first wiring line extending along a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending along a second direction intersecting the first direction, and a memory cell provided between the first wiring line and the second wiring line, and including a magnetoresistance effect element, a switching element, a middle electrode provided between the magnetoresistance effect element and the switching element, and a resistive layer provided between the magnetoresistance effect element and the second wiring line. a resistance of the resistive layer is higher than a resistance of the middle electrode.
20240324249. STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kouji MATSUO of Ama Aichi (JP) for kioxia corporation
IPC Code(s): H10B80/00, H01L23/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: a plurality of memory cell regions includes a semiconductor layer extending in a first direction and a pillar having a side surface in contact with the semiconductor layer and extending in a second direction. a first conductor includes a first portion extending in the first direction and a plurality of second portions extending in a third direction and connected to the first portion. one of the second portions is in contact with the semiconductor layer. each of a plurality of contact regions includes a plurality of contacts extending in the second direction. a plurality of groups is arranged in the first direction when viewed in the second direction, each of the groups including one of the plurality of memory cell regions, one of the plurality of second portions, and one of the plurality of contact regions, which are arranged in the first direction when viewed in the second direction.
20240324250. SEMICONDUCTOR MEMORY_simplified_abstract_(kioxia corporation)
Inventor(s): Kosuke YANAGIDAIRA of Fujisawa Kanagawa (JP) for kioxia corporation, Yoshikazu HOSOMURA of Kamakura Kanagawa (JP) for kioxia corporation, Shouichi OZAKI of Komae Tokyo (JP) for kioxia corporation
IPC Code(s): H10B80/00, G11C16/04, G11C16/10, G11C16/16, G11C16/26, G11C16/34, H01L23/00, H01L23/522, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: according to one embodiment, a semiconductor memory includes a first chip including a substrate and a second chip bonded to the first chip. the second chip includes a first region including the memory cell array and the first shield line, and a second region including a second shield line. the first shield line is provided between the first chip and a memory cell array. the second shield line is provided in a same layer as the first shield line, and is not electrically coupled to the first shield line.
Inventor(s): Sota MATSUMOTO of Yokkaichi (JP) for kioxia corporation, Takahito NISHIMURA of Kuwana (JP) for kioxia corporation
IPC Code(s): H10B99/00, H01L21/308, H01L21/822, H01L27/06, H10B41/20, H10B41/35, H10B41/40
CPC Code(s): H10B99/00
Abstract: a semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. a first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.
20240324470. MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Naoki AKIYAMA of Seoul (KR) for kioxia corporation, Kenichi YOSHINO of Seongnam-si Gyeonggi-do (KR) for kioxia corporation, Kazuya SAWADA of Seoul (KR) for kioxia corporation, Takuya SHIMANO of Seoul (KR) for kioxia corporation, Hyungjun CHO of Seoul (KR) for kioxia corporation
IPC Code(s): H10N50/80, H10B61/00, H10N50/01, H10N50/10
CPC Code(s): H10N50/80
Abstract: according to one embodiment, a magnetic memory device includes a lower structure, a bottom electrode provided on the lower structure and formed of a conductive material, a top electrode provided above the bottom electrode, a magnetoresistance effect element provided between the bottom electrode and the top electrode, and an oxide insulating layer including a first portion provided on a side surface of the bottom electrode and a second portion provided on a side surface of the magnetoresistance effect element, and formed of an oxide of the conductive material.
Inventor(s): Soichiro ONO of Seongnam-si Gyeonggi-do (KR) for kioxia corporation, Hiroyuki KANAYA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/841
Abstract: a storage device includes a memory cell that includes a variable resistance storage element and a switching element connected in series thereto and stacked therewith in a first direction, the switching element including a first electrode, a second electrode that includes a first part formed of a first material to which a first element is added, and a switching material layer that is between the first electrode and the first part of the second electrode and formed of a first insulating material to which the first element is added. the storage device further includes a first insulating layer that surrounds the switching material layer and formed of the first insulating material to which the first element is not added. an outer periphery of the first part of the second electrode and an outer periphery of the switching material layer are aligned in the first direction.
Kioxia Corporation patent applications on September 26th, 2024
- Kioxia Corporation
- B41C1/10
- G03F7/00
- G06F30/392
- CPC B41C1/10
- Kioxia corporation
- C25D11/02
- CPC C25D11/022
- G01N23/203
- G01N23/20025
- G01N23/2055
- G01N33/204
- CPC G01N23/203
- CPC G03F7/0002
- G03F7/20
- G03F7/16
- H01L21/027
- CPC G03F7/162
- G06F3/06
- G06F11/10
- G11C11/56
- G11C16/04
- G11C16/26
- CPC G06F3/061
- CPC G06F3/0619
- CPC G06F3/0655
- G06F7/58
- CPC G06F3/0658
- CPC G06F3/0659
- G06F11/07
- CPC G06F11/076
- CPC G06F11/1044
- CPC G06F11/1068
- G06F11/14
- CPC G06F11/141
- G06F11/16
- CPC G06F11/1658
- G06F12/02
- CPC G06F12/0246
- G06F30/20
- G06T7/00
- G06T7/60
- G06T7/73
- CPC G06F30/20
- G06Q50/04
- G06Q10/087
- CPC G06Q50/04
- G11C5/10
- G11C11/4076
- G11C11/4091
- G11C11/4096
- CPC G11C5/10
- G11C7/08
- G11C7/10
- CPC G11C7/08
- G11C11/16
- G11C29/12
- CPC G11C11/1653
- H10B61/00
- CPC G11C11/1673
- G11C11/4074
- CPC G11C11/4096
- G11C16/08
- G11C16/10
- CPC G11C11/5628
- G11C13/00
- CPC G11C13/004
- G11C5/06
- H10B41/20
- H10B41/35
- H10B41/41
- CPC G11C16/0483
- H10B43/27
- CPC G11C16/10
- G11C16/34
- CPC G11C16/102
- H01L25/065
- H10B41/10
- H10B41/27
- H10B43/10
- H10B43/35
- H10B80/00
- CPC G11C16/26
- G11C16/16
- CPC G11C16/3445
- G11C29/02
- CPC G11C29/024
- G11C29/52
- CPC G11C29/52
- H01J49/42
- H01J49/00
- H01J49/16
- CPC H01J49/426
- H01L21/02
- H01L21/311
- CPC H01L21/02211
- H01L21/67
- H01L21/66
- H01L21/687
- CPC H01L21/67092
- H01L23/528
- H10B41/40
- H10B43/40
- CPC H01L23/5283
- H01L23/00
- CPC H01L24/80
- CPC H01L25/0657
- H01L21/56
- H01L21/78
- H01L23/31
- H01L23/544
- H01L25/18
- H01L23/498
- CPC H01L25/18
- H01L27/02
- H01L27/092
- H01L29/06
- CPC H01L27/0266
- H01L29/49
- H01L29/66
- H01L29/775
- H01L29/786
- H10B12/00
- CPC H01L29/4908
- CPC H01L29/7869
- H03K19/0175
- H01L23/538
- CPC H03K19/017509
- H03M1/12
- H04B1/16
- CPC H03M1/12
- H03M13/35
- G11B20/18
- G11C29/04
- H03M13/29
- CPC H03M13/35
- H04L9/08
- CPC H04L9/0866
- H04L12/40
- H04L1/00
- CPC H04L12/4013
- H04L27/01
- CPC H04L27/01
- H05K5/00
- CPC H05K5/0026
- H05K7/20
- CPC H05K7/20272
- H10B10/00
- CPC H10B10/125
- H01L23/482
- CPC H10B12/0335
- CPC H10B12/05
- CPC H10B12/30
- CPC H10B12/33
- CPC H10B41/35
- CPC H10B43/10
- CPC H10B43/27
- H01L21/768
- H01L23/522
- CPC H10B43/35
- H10B53/30
- CPC H10B53/30
- H10N50/01
- H10N50/20
- CPC H10B61/00
- H10N50/10
- H10N50/80
- CPC H10B61/10
- CPC H10B80/00
- H10B99/00
- H01L21/308
- H01L21/822
- H01L27/06
- CPC H10B99/00
- CPC H10N50/80
- H10N70/00
- H10B63/00
- CPC H10N70/841
