Kioxia Corporation patent applications on September 19th, 2024
Patent Applications by Kioxia Corporation on September 19th, 2024
Kioxia Corporation: 56 patent applications
Kioxia Corporation has applied for patents in the areas of H10B43/27 (6), G11C16/04 (6), H01L21/67 (6), G06F3/06 (6), H01L23/00 (5) G06F12/0246 (3), G11C16/32 (2), H10B41/27 (2), G06F3/0659 (2), H10B43/35 (2)
With keywords such as: memory, layer, semiconductor, data, direction, connected, third, configured, conductive, and device in patent application abstracts.
Patent Applications by Kioxia Corporation
Inventor(s): Jiahong WU of Yokkaichi (JP) for kioxia corporation
IPC Code(s): B08B3/14, B08B1/00, B08B1/04, B08B3/02
CPC Code(s): B08B3/14
Abstract: an impurity recovery device according to the present embodiment may recover impurities present on a surface of a substrate. the substrate may be placed on a stage. a sprayer may spray a recovery liquid toward the substrate along a direction from a side of a central part of the substrate to a side of the end part of the substrate. a recovery portion may recover the recovery liquid from the end part of the substrate.
Inventor(s): Takeshi ARAKAWA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): B24B57/02, B24B7/04, B24B41/00, B24B49/14
CPC Code(s): B24B57/02
Abstract: a polishing apparatus according to the present embodiment includes a head, a polishing table, a rotation table, a particle supplier, and one chamber. the head holds an object. the polishing table polishes a polishing target surface of the polishing target object. the rotation table is capable of contacting the polishing target surface. the particle supplier supplies slurry containing particles onto the rotation table so that the particles are fixed onto at least part of the polishing target surface, while the polishing target surface is contacting the rotation table. the one chamber houses the polishing table and the rotation table.
Inventor(s): Kazuki HAGIHARA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G01B15/04, G06T7/00, G06T7/543, H10B80/00
CPC Code(s): G01B15/04
Abstract: a pattern shape measurement method includes acquiring image data of a target pattern obtained by irradiating an observation region of a sample with a charged particle or an electromagnetic wave, generating first contour point group data in which location information of a contour point of the target pattern extracted based on the image data and an index related to an orientation angle of a line connecting a center of the target pattern and the contour point from a reference line passing through the center of the target pattern are associated with each other, and generating, based on a weighting table in which the index and weight determined based on a standard deviation of location information of the contour point of the target pattern present in a direction of the orientation angle are associated with each other and stored, and the first contour point group data, second contour point group data according to the weight.
20240311003. MEMORY SYSTEM AND METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Kohei OIKAWA of Kawasaki (JP) for kioxia corporation, Youhei FUKAZAWA of Kawasaki (JP) for kioxia corporation, Keiri NAKANISHI of Kawasaki (JP) for kioxia corporation, Sho Kodama of Kamakura (JP) for kioxia corporation, Takashi TAKEMOTO of Yokohama (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0608
Abstract: according to one embodiment, a memory controller includes a parameter table having entries which respectively correspond to superblock address ranges. the memory controller translates a logical address of data to be written to the memory into a superblock address, calculates compression parameters which correspond to items of data to be written to superblock addresses, writes the compression parameters to the parameter table, and compress data using the parameter table.
20240311010. MEMORY CARD AND HOST DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Akihisa FUJIMOTO of Sagamihara (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/061
Abstract: according to one embodiment, a memory card includes a nonvolatile memory and a controller. the controller performs initialization of an interface, determines a maximum performance that can be supported from among a plurality of performance predetermined for stream recording, based on a bus configuration of the interface determined at the interface initialization and a maximum allowable power consumption set during the interface initialization, and generates a data set stored in a power state register specified by an nvme™ standard, which is a power state set in which each of all performance smaller than the determined maximum performance among the plurality of performance corresponds to a power state, to indicate a list of the performance which can be supported for a host.
20240311039. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Haruka MORI of Kawasaki Kanagawa (JP) for kioxia corporation, Mitsunori TADOKORO of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a memory system includes a plurality of memory chips, a memory, and a controller. the memory chips are capable of operating in parallel. the memory includes a physical channel region and a plurality of virtual channel regions, each corresponding to one of a plurality of processes executed on the memory chips according to the requests. the controller stores the requests issued from the host in the physical channel region in order of acquisition from the host, and an entry for each of the requests in one of the virtual channel regions. when a required degree of parallelism of the processes is less than a threshold, the controller selects a next request to be executed using the physical channel region. when the required degree of parallelism is greater than or equal to the threshold, the controller selects a next request to be executed using one of the virtual channel regions.
20240311047. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Shinya KOIZUMI of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0658
Abstract: a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. the controller is configured to: after transmitting a write command and an address to the nonvolatile memory via a first signal line, transmit dummy data to the nonvolatile memory via the first signal line during at least a portion of a period that is between when the address is transmitted via the first signal line and when write data of the write command is transmitted via the first signal line, and after transmitting the dummy data via the first signal line, transmit a data strobe signal to the nonvolatile memory via a second signal line and transmit the write data of the write command to the nonvolatile memory via the first signal line in synchronization with the data strobe signal.
Inventor(s): Goichi OOTOMO of Kawasaki Kanagawa (JP) for kioxia corporation, Tomoaki SUZUKI of Chigasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a semiconductor device includes a first interface with a first channel at a first data transfer rate, a second interface with a second channel at a second data transfer rate slower than the first data transfer rate, a transfer circuit, and a processor. the processor is configured to, upon the first interface receiving a first data output command from a memory controller via the first channel, issue the first data output command via the second channel, in response to which a first memory chip connected to the second interface reads first data corresponding to the first data output command, and after a first predetermined amount of time has elapsed from the issuance of the first data output command, issue a first transfer start command via the second channel, in response to which the first data is transferred to the transfer circuit via the second channel.
20240311052. MEMORY SYSTEM AND CONTROL METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Shinnichirou NAKAZUMI of Kawasaki Kanagawa (JP) for kioxia corporation, Takashi KONDO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: a memory system includes: a nonvolatile memory including a cache buffer that can receive second data for a next program operation during execution of a program operation for writing first data to a memory cell array; and a controller. the controller measures an elapsed time from start of the program operation. the controller starts an operation of transferring the second data to the nonvolatile memory according to elapse of a first time from the start of the program operation.
20240311232. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Yuko NODA of Kawasaki Kanagawa (JP) for kioxia corporation, Kiwamu WATANABE of Kawasaki Kanagawa (JP) for kioxia corporation, Masahiro SAITO of Suginami Tokyo (JP) for kioxia corporation, Yoshiki TAKAI of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1016
Abstract: a memory system includes a nonvolatile memory including a memory cell, and a controller. the controller is configured to write multi-bit data into the memory cell through a first write operation of writing a first part, and not a second part, of the multi-bit data and then a second write operation of writing the first and second parts. the controller is configured to, during writing of the multi-bit data, determine an amount of time that has passed since the first write operation, perform the second write operation in a first manner by inputting the second part, and not the first part, from the controller, when the determined amount is less than a threshold amount, and perform the second write operation in a second manner by inputting the first and second parts from the controller, when the determined amount is greater than the threshold amount.
Inventor(s): Ofir Kanter of Haifa (IL) for kioxia corporation, Avi Steiner of Kiriat Motzkin (IL) for kioxia corporation
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1068
Abstract: aspects can include selecting memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second plurality of pages including corresponding second pluralities of bits, obtaining, based on the second pluralities of bits, extrinsic page information for a proposed error solution including a third plurality of bits indicating a reliability of respective bits of the first plurality of bits, and rejecting, in response to a determination that the proposed error solution indicates a modification to a reliable bit among the first plurality of bits, the proposed error solution to eliminate a false correction of the first plurality of bits.
Inventor(s): Atsushi KAWASUMI of Fujisawa Kanagawa (JP) for kioxia corporation, Takashi MAEDA of Kamakura Kanagawa (JP) for kioxia corporation, Hidehiro SHIGA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F12/02, G11C16/04, G11C16/26
CPC Code(s): G06F12/02
Abstract: an information processing apparatus that detects whether the corresponding first element and second element among the multiple first elements and the plurality of second elements are matched or are similar, has one or multiple strings connected to a first wiring and connected to multiple second wirings, wherein the string includes multiple transistor pairs connected in series along a current path having one end connected to the first wiring, each of the multiple transistor pairs includes a first transistor and a second transistor connected in series along the current path, the second wirings are connected to gates of the first transistor and the second transistor in each of the multiple transistor pairs, the first transistor is set to a first threshold depending on first data, the second transistor is set to a second threshold depending on second data that is complement data of the first data.
Inventor(s): Shinichi KANNO of Ota (JP) for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: according to one embodiment, a memory system includes a nonvolatile memory, a first write buffer, a second write buffer having a capacity smaller than that of the first write buffer and a bandwidth larger than that of the first write buffer, and a controller. when the write speed of the first group is less than a first value, the controller loads unloaded data among first data into the first write buffer, and after an amount of the first data reaches or exceeds a minimum write size, writes the first data to a first write destination block. when the write speed of the second group is greater than or equal to the first value, the controller loads second data having the minimum write size into the second write buffer and writes the second data to the second write destination block.
20240311292. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Daisuke UCHIDA of Fujisawa (JP) for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: according to one embodiment, a host interface circuit includes a physical layer that performs communication with a host, and a protocol control circuit that determines a transfer rate between the physical layer and the host. when a temperature detected by a temperature sensor becomes equal to or higher than a first temperature, the protocol control circuit changes the transfer rate from a first transfer rate to a second transfer rate. the protocol control circuit transitions to a first mode in which a change of the transfer rate based on a first request from the host is prohibited.
20240311294. MEMORY SYSTEM AND NON-VOLATILE MEMORY_simplified_abstract_(kioxia corporation)
Inventor(s): Keisuke AZUMA of Tokyo (JP) for kioxia corporation, Mitsuaki HONMA of Fujisawa (JP) for kioxia corporation, Daisuke ARIZONO of Yokohama (JP) for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: according to an embodiment, a memory system includes a non-volatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit, and a memory controller configured to control the non-volatile memory. the non-volatile memory is configured to output first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data for the first bit, the second bit, and the third bit to the memory controller. the memory controller is configured to execute error correction processing using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data.
Inventor(s): Daiki WATANABE of Kawasaki Kanagawa (JP) for kioxia corporation, Takeshi ISHIHARA of Yokohama Kanagawa (JP) for kioxia corporation, Kenji SHIRAKAWA of Machida Tokyo (JP) for kioxia corporation
IPC Code(s): G06F16/2452, G06F11/34, G06F16/2453
CPC Code(s): G06F16/24526
Abstract: a method for executing query processing includes, in response to a query from a host, generating a task graph indicating a plurality of task sequences, each of the task sequences capable f performing query processing corresponding to the query. the sequences includes a first sequence that outputs data in a first compression state to a one of output targets, and a second sequence of tasks that outputs the data in a second compression state different from the first compression state to the one of the output targets. the method further includes determining a processing cost for each of the task sequences, selecting one of the task sequences in accordance with the determined processing cost, and performing the query processing corresponding to the query in accordance with the selected task sequence.
Inventor(s): Shuhei IIJIMA of Yokohama (JP) for kioxia corporation, Osamu YAMANE of Ebina (JP) for kioxia corporation, Youyang NG of Kamakura (JP) for kioxia corporation, Yuchieh LIN of Yokohama (JP) for kioxia corporation, Takuji OHASHI of Yokohama (JP) for kioxia corporation, Takeshi FUJIWARA of Yokohama (JP) for kioxia corporation
IPC Code(s): G06T7/00, G06T5/50, G06T7/194, G06V10/44, G06V10/764, G06V20/70
CPC Code(s): G06T7/0008
Abstract: a semiconductor image processing apparatus including a processing circuitry, the processing circuitry configured to identify a label corresponding to a feature amount included in an input image by using an identifier, learn a model for inferring the feature amount included in the input image and learns the identifier, and perform additional learning of the model based on the input image and the learned identifier.
20240312505. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Naoki MATSUSHITA of Seoul (KR) for kioxia corporation
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1673
Abstract: according to one embodiment, a memory device includes a first memory cell, a second memory cell, a first interconnect connected to the first memory cell and the second memory cell, a second interconnect connected to the second memory cell, and a third circuit. the third circuit includes a first circuit connectable to the first interconnect and the second interconnect and a second circuit connectable to the first interconnect and the second interconnect. during a write operation or a read operation for the first memory cell, the first circuit outputs a first current to be supplied to the first memory cell, the second circuit outputs a third current based on a second current which flows through the second interconnect, and the third circuit supplies a sum of the first current and the third current to the first interconnect.
20240312506. MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Akira KATAYAMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1673
Abstract: a memory cell includes first and second ends. a first interconnect is coupled to the first end. a first switch is coupled between the first interconnect and a first node that receives a first voltage. a second interconnect is coupled to the second end. a second switch includes a third end coupled to the second interconnect and a fourth end. a third interconnect is coupled to the fourth end. a third switch is coupled between the third interconnect and a second node that receives a second voltage different from the first voltage. a third voltage between the second and first voltages is applied to the first and second interconnects. the third and second switches are respectively turned off and on after the third switch is turned on and after the application of the third voltage. the first switch is turned off after the application of the third voltage.
Inventor(s): Megumi SHIBATANI of Ota Tokyo (JP) for kioxia corporation, Takashi OOSHIMA of Chiba Chiba (JP) for kioxia corporation, Nobuyuki SUZUKI of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C11/4074, G11C11/4072, G11C11/4096
CPC Code(s): G11C11/4074
Abstract: a memory system includes: a first nonvolatile memory; a second volatile memory; a controller; a power control circuit configured to perform control such that a first voltage is applied to the first memory, the second memory, and the controller based on first power supplied from an external power supply; and a power storage device configured to supply second power to the power control circuit while the first power from the external power supply is interrupted. while the first power supplied from outside is interrupted, the power control circuit applies a second voltage based on the second power supplied from the power storage device to the first memory, the second memory, and the controller. the power control circuit stops the application of the second voltage to the second memory after the data is read from the second memory and before the data is written into the first memory.
20240312513. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Tomohiko ITO of Kawasaki Kanagawa (JP) for kioxia corporation, Hiroshi YOSHIHARA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C11/4096, G11C11/4074, G11C11/408
CPC Code(s): G11C11/4096
Abstract: according to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor; a second memory string including a second memory cell transistor; a first word line commonly coupled to a gate of each of the first memory cell transistor and the second memory cell transistor; and a control circuit, wherein during a first read operation of reading data from the first memory string, a threshold voltage of the first memory cell transistor is less than a first voltage, a threshold voltage of the second memory cell transistor is equal to or greater than the first voltage, and the control circuit is configured to supply a voltage equal to or less than the first voltage to the first word line.
Inventor(s): Tomonori TAKAHASHI of Yokohama (JP) for kioxia corporation, Masanobu SHIRAKAWA of Chigasaki (JP) for kioxia corporation, Osamu TORII of Tokyo (JP) for kioxia corporation, Marie TAKADA of Yokohama (JP) for kioxia corporation
IPC Code(s): G11C11/56, G11C16/04, G11C16/08, G11C16/26
CPC Code(s): G11C11/5671
Abstract: according to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. a first bit of the 5-bit data is established by reading operations using first to sixth voltages. a second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. a third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. a fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. a fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.
Inventor(s): Eyal Nitzan of Haifa (IL) for kioxia corporation, Avi Steiner of Haifa (IL) for kioxia corporation, Hanan Weingarten of Haifa (IL) for kioxia corporation
IPC Code(s): G11C16/26, G11C11/54, G11C16/34
CPC Code(s): G11C16/26
Abstract: a method for reading data from a solid-state drive (ssd) configured to store data in a plurality of memory cells arranged in memory blocks comprising rows, the method performed by a controller in communication with the plurality of memory cells. the method comprises retrieving data from a target row of memory cells of the plurality of memory cells associated with a read request received from a host using initial threshold voltages. the method also includes decoding the data using a hard decision stage. additionally the method comprises estimating read threshold voltages of the target row of memory cells based on a transformation of a distribution of threshold voltages of cells in a memory block containing the target row when the hard decision decoding stage fails. the method further includes retrieving data from the target row using the estimated read threshold voltages.
20240312532. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Junya MATSUNO of Yokohama Kanagawa (JP) for kioxia corporation, Kenro KUBOTA of Fujisawa Kanagawa (JP) for kioxia corporation, Masato DOME of Yokohama Kanagawa (JP) for kioxia corporation, Kensuke YAMAMOTO of Yokohama Kanagawa (JP) for kioxia corporation, Kei SHIRAISHI of Kawasaki Kanagawa (JP) for kioxia corporation, Kazuhiko SATOU of Yokohama Kanagawa (JP) for kioxia corporation, Ryo FUKUDA of Yokohama Kanagawa (JP) for kioxia corporation, Masaru KOYANAGI of Tokyo (JP) for kioxia corporation
IPC Code(s): G11C16/32, G11C16/04, G11C16/08, G11C16/26, H10B69/00
CPC Code(s): G11C16/32
Abstract: a semiconductor memory device includes a memory cell array having a memory cell; a data signal terminal configured to receive data to be written into the memory cell from an exterior of the semiconductor memory device and to output data read from the memory cell to the exterior of the semiconductor memory, and a timing signal terminal configured to receive a timing control signal. an interface circuit includes a first comparator having a first input terminal connected to the data signal terminal, a second input terminal connected to a reference voltage, and an output terminal. a plurality of first inverters are connected in series, an input terminal of a first stage one of the first inverters being connected to the output terminal first of the first comparator. a first switch circuit has a first terminal connected to an output terminal of a final stage one of the first inverters and a second terminal; a second inverter having an input terminal connected to the second terminal of the first switch and an output terminal connected to the second terminal of the first switch; and a first latch circuit connected to the second terminal of the first switch.
Inventor(s): Yoshihisa KOJIMA of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/32, G11C7/04, G11C11/56, G11C16/04, G11C16/08, G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G11C16/32
Abstract: a memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. the memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
20240312542. SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Masato ENDO of Yokohama Kanagawa (JP) for kioxia corporation, Haruo MIKI of Yokohama Kanagawa (JP) for kioxia corporation, Daiki SUGAWARA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/34, G11C16/04, G11C16/20
CPC Code(s): G11C16/3495
Abstract: a semiconductor storage device includes a thermal history monitor and a determination circuit. the thermal history monitor outputs a thermal history based on a characteristic variation of a memory cell when a reliability detection command is input from a controller or a host device. the determination circuit determines package reliability based on the thermal history output from the thermal history monitor.
Inventor(s): Avi Steiner of Kiriat (IL) for kioxia corporation, Ofir Kanter of Haifa (IL) for kioxia corporation, Yasuhiko Kurosawa of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C29/52, G11C29/02
CPC Code(s): G11C29/52
Abstract: aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (llr), and decoding, based on the llr corresponding to the voltage range, the first plurality of bits.
20240312761. DRAWING DEVICE AND DRAWING METHOD_simplified_abstract_(kioxia corporation)
Inventor(s): Yoshinori KAGAWA of Shinagawa Tokyo (JP) for kioxia corporation
IPC Code(s): H01J37/302, G03F1/78, H01J37/20, H01J37/317
CPC Code(s): H01J37/3026
Abstract: a drawing device includes a device configured to generate a beam of charged particles, a group of optical elements disposed in a path of the beam, the group of optical elements being controlled so that the beam irradiates each of a plurality of divided regions of a target drawing region on which a pattern is to be drawn with the beam, and a control computer configured to divide the target drawing region into the divided regions based on a density of the pattern, and to execute first to n-th irradiations (n is an integer of 2 or more) selectively on the divided regions so that a total irradiation amount of the beam on each of the divided regions reaches a required irradiation amount therefor.
Inventor(s): Hakuba KITAGAWA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/67, C25B1/02, C25D17/00, H01L21/687
CPC Code(s): H01L21/67023
Abstract: a substrate processing apparatus includes a processing tank configured to accommodate a substrate processing liquid; a holder configured to place a first substrate in the processing tank; an anode and a cathode configured to form a porous layer on a first surface of the first substrate; and a bubble supplier configured to supply a first bubble to the first surface of the first substrate.
Inventor(s): Shohei ARAKAWA of Mie Mie (JP) for kioxia corporation
IPC Code(s): H01L21/67, H01J37/32, H01L21/306, H01L21/3065
CPC Code(s): H01L21/67069
Abstract: a semiconductor manufacturing apparatus includes a bevel processing chamber, a stage on which a first surface of a substrate is to be placed, a first gas supply pipe configured to supply first gas to a first surface side of the substrate, a first ring surrounding the stage and having an outer diameter smaller than a diameter of the substrate, a top plate facing a second surface of the substrate, a second gas supply pipe configured to supply second gas to a second surface side of the substrate, a second ring surrounding the top plate and having an outer diameter smaller than the diameter of the substrate, a first electrode surrounding the first ring, a second electrode surrounding the second ring, a third gas supply pipe configured to supply process gas, and a control circuit that controls plasma processing of a bevel of the substrate using the process gas.
Inventor(s): Yosuke MARUYAMA of Yokkaichi Mie (JP) for kioxia corporation, Takahiro KAWATA of Yokkaichi Mie (JP) for kioxia corporation, Satoshi NAKAOKA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/67, H01L21/311, H01L21/687
CPC Code(s): H01L21/67086
Abstract: a substrate processing apparatus includes: a processing tank configured to store a solution capable of processing a substrate; a supply configured to supply the solution to the processing tank; a holding member having an openable and closable support portion capable of sandwiching the substrate, the holding member configured to hold the substrate in the processing tank; a first drive mechanism configured to move the holding member in a first direction along a substrate surface; and a guide disposed between the support portion and the supply in the processing tank and configured to guide a rotational movement of the substrate in the first direction.
20240312803. SUBSTRATE PROCESSING DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Shusaku MATSUMOTO of Saitama Saitama (JP) for kioxia corporation, Shiguma KATO of Mie Mie (JP) for kioxia corporation, Koichiro KAWANO of Kamakura Kanagawa (JP) for kioxia corporation, Tomoya IWASAKI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/67, H01L21/311, H01L21/687
CPC Code(s): H01L21/67086
Abstract: a substrate processing device includes a processing tank including a first region, a second region, and a third region, wherein a plurality of substrates are housed in the first region and arranged in a first direction with their faces oriented in an approximately horizontal direction such that a processing of the substrates using a processing solution is carried out, the second region is provided in a vicinity of the first region, and the third region is provided such that the processing solution can move between the first region and the second region; a moving body disposed in the second region of the processing tank and configured to move such that a flow of the processing solution occurs; and a movement mechanism configured to move the moving body.
20240312809. SEMICONDUCTOR MANUFACTURING APPARATUS_simplified_abstract_(kioxia corporation)
Inventor(s): Takashi OHASHI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/67, H01L21/677
CPC Code(s): H01L21/67167
Abstract: a semiconductor manufacturing apparatus includes a front end module with a load port to which a conveyance container is connected on an upper surface; and a plurality of processing units configured to process a semiconductor substrate, disposed around the front end module in a plan view from a normal direction of the upper surface of the front end module, and each connected to the front end module from at least two directions in the plan view. the semiconductor substrate is conveyed between the conveyance container and the processing units via the front end module.
Inventor(s): Yoshio MIZUTA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L21/68, G03F7/00, H01L21/66, H01L21/67, H01L23/00, H01L21/311, H01L21/683
CPC Code(s): H01L21/68
Abstract: according to embodiments, a semiconductor manufacturing apparatus includes a control circuit configured to acquire, for a pair of substrates including a first substrate and a second substrate, a warp amount of the first substrate, the warp amount of the first substrate including an amount of protrusion of a portion of the first substrate relative to an edge of the first substrate; determine a desired size for a gap between the first and second substrates based on the acquired warp amount; and control a chuck movement device to move one of the first and second substrates to adjust the gap to the determined size before the first and second substrates are bonded.
20240312911. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Takafumi MASUDA of Kawasaki (JP) for kioxia corporation, Mutsumi OKAJIMA of Yokkaichi (JP) for kioxia corporation, Nobuyoshi SAITO of Tokyo (JP) for kioxia corporation, Keiji IKEDA of Kawasaki (JP) for kioxia corporation
IPC Code(s): H01L23/528, H01L23/522, H10B12/00
CPC Code(s): H01L23/5283
Abstract: a semiconductor memory device includes a memory layer and a via-wiring extending in a first direction. the memory layer includes a semiconductor layer electrically connected to the via-wiring, a gate electrode including parts opposed to surfaces of the semiconductor layer on one side and the other side in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, and a wiring disposed on the other side in the second direction with respect to the semiconductor layer. in a cross-sectional surface perpendicular to the first direction and including one of the parts of the gate electrode, the via-wiring includes a surface opposed to the gate electrode and a surface not opposed to the gate electrode. a part of the gate electrode is disposed on a memory portion side with respect to the via-wiring in the second direction.
20240312958. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Toshimitsu ARAI of Chigasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L25/065, H01L23/00
CPC Code(s): H01L25/0657
Abstract: according to one embodiment, a semiconductor device comprises: a first semiconductor chip on which a first adhesive is attached to a rear surface thereof; and a second semiconductor chip on which a second adhesive is attached to a rear surface thereof, wherein the second semiconductor chip is attached to a front surface of the first semiconductor chip via the second adhesive, the second semiconductor chip has an overhang region that does not overlap the first semiconductor chip when viewed in a first direction, and the first adhesive includes a base portion and also includes an extension portion that extends in a second direction from the base portion of the first adhesive to beyond an edge of the first semiconductor chip, at least a part of the extension portion of the first adhesive overlapping the overhang region of the second semiconductor chip when viewed in the first direction.
Inventor(s): Keiichi NIWA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L25/00, H01L21/56, H01L23/00, H01L23/31, H01L25/18, H10B80/00
CPC Code(s): H01L25/50
Abstract: a semiconductor device includes a wiring board including first and second surfaces opposite to each other, a first semiconductor element on the first surface side of the wiring board, a second semiconductor element adjacent to the first semiconductor element on the first surface side of the wiring board, a first resin composition on the first surface side of the wiring board, and a second resin composition that covers the first and second semiconductor elements and the first resin composition. the first resin composition includes a first part between the first surface of the wiring board and a surface of the first semiconductor element facing the first surface, and a second part contacting a first side surface of the second semiconductor element facing the first semiconductor element.
20240313527. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Shigefumi ISHIGURO of Yokohama Kanagawa (JP) for kioxia corporation, Yasuhiro SUEMATSU of Yokohama Kanagawa (JP) for kioxia corporation, Masaru KOYANAGI of Ota Tokyo (JP) for kioxia corporation, Maya INAGAKI of Yokohama Kanagawa (JP) for kioxia corporation, Kentaro WATANABE of Yokohama Kanagawa (JP) for kioxia corporation, Shoki ITO of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H02H9/04
CPC Code(s): H02H9/046
Abstract: a semiconductor device includes a protection circuit electrically connected to a first interconnection and a second interconnection, a first voltage and a second voltage supplied to the first interconnection and the second interconnection, respectively. the protection circuit includes: a first resistor connected between the first interconnection and a first node; a first capacitor connected between the second interconnection and the first node; a second resistor connected between the second interconnection and a second node located; a second capacitor connected between the second interconnection and the second node, and connected in parallel to the second resistor; a third resistor connected between the first interconnection and a third node; and a third capacitor connected between the second interconnection and the third node.
Inventor(s): Huy Cu NGO of Isehara (JP) for kioxia corporation
IPC Code(s): H03K17/687, H03K5/01
CPC Code(s): H03K17/6871
Abstract: a semiconductor integrated circuit includes a first input terminal inputting a first signal, a second input terminal supplied to a first voltage, an output terminal outputting a second signal. the circuit includes: a first transistor having first, second, control terminals respectively connected to a first node, the output terminal and first input terminals; a second transistor having first, second, control terminals respectively connected to the first and second nodes, the output terminal; a third transistor having a first terminal supplied to a second voltage, second and control terminals respectively connected to the first node and the second input terminal; a fourth transistor having first and control terminals respectively connected to the output terminal and the second node, a second terminal supplied to a third voltage; and a fifth transistor having first and control terminals connected to the second node, and a second terminal supplied to the third voltage.
Inventor(s): Fumiya WATANABE of Chigasaki Kanagawa (JP) for kioxia corporation, Kazuhiko SATOU of Yokohama Kanagawa (JP) for kioxia corporation, Kenro KUBOTA of Fujisawa Kanagawa (JP) for kioxia corporation, Atsuko SAEKI of Yokohama Kanagawa (JP) for kioxia corporation, Ryota TSUCHIYA of Kamakura Kanagawa (JP) for kioxia corporation, Harumi ABE of Kawasaki Kanagawa (JP) for kioxia corporation, Kanta NAGUMO of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): H03K19/00, H03K19/003, H03K19/0185
CPC Code(s): H03K19/0005
Abstract: a semiconductor device includes a first circuit, a first pad, a first comparator, a second comparator, and a control circuit. the first circuit is configured to pull up a voltage of a first node, and includes a plurality of first transistors connected in parallel to the first node. the first pad is connected to the first node. the first comparator is configured to compare a voltage of the first node with a first reference voltage. the second comparator is configured to compare the voltage of the first node with a second reference voltage. the control circuit is configured to control the plurality of first transistors based on an output of the first comparator and an output of the second comparator.
Inventor(s): Avi Steiner of Kiriat Motzkin (IL) for kioxia corporation, Ofir Kanter of Haifa (IL) for kioxia corporation, Hanan Weingarten of Herzliya (IL) for kioxia corporation, Assaf Sella of Tel Aviv (IL) for kioxia corporation, Nimrod Bregman of Tel Aviv (IL) for kioxia corporation, Yasuhiko Kurosawa of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): H03M13/29, H03M13/11
CPC Code(s): H03M13/2909
Abstract: systems, methods, non-transitory computer-readable media configured to perform operations associated with a storage medium. one system includes the storage medium and an encoding/decoding (ed) system, the ed system being configured to receive a set of input log-likelihood ratios (llrs) of a component of the plurality of components, determine an extrinsic estimation function based on a set of features of the set of input llrs, analyze the extrinsic estimation function to obtain a plurality of extrinsic llr values, map the plurality of extrinsic llr values to an input llr of the set of input llrs, and output, for each component, a plurality of updated llr values based on the mapping.
20240314929. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kiyokazu ISHIZAKI of Nishitokyo, Tokyo (JP) for kioxia corporation
IPC Code(s): H05K1/11, H01L23/31, H01L23/498, H01L25/065, H05K1/18
CPC Code(s): H05K1/117
Abstract: a semiconductor storage device includes a wiring pattern on an insulating base material; an insulating film covering partially the wiring pattern; and an electronic component. the wiring pattern includes a first pad having an edge in an arc shape, and a first wire. the insulating film has a first opening larger than the first pad. the first wire has a first portion, a second portion, and a third portion. the first portion is connected to the first pad inside the first opening extends in a first direction. the second portion is connected to the first pad inside the first opening and extends in a second direction. the third portion is connected to the first portion and the second portion. the first wire is connected with the first pad in an angular range of not more than 90 degrees in a circumferential direction of the first pad.
20240315007. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kotaro NODA of Yokkaichi Mie (JP) for kioxia corporation, Takahiro FUJII of Nagoya Aichi (JP) for kioxia corporation, Takanori AKITA of Yokkaichi Mie (JP) for kioxia corporation, Mutsumi OKAJIMA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: a semiconductor device includes a first oxide semiconductor layer extending in a first direction, a first wiring extending in a second direction that intersects the first direction and surrounding the first oxide semiconductor layer, a first insulating film provided between the first wiring and the first oxide semiconductor layer, a first conductor provided on the first oxide semiconductor layer, a second wiring provided on the first conductor and extending in a third direction that intersects each of the first direction and the second direction, a first insulating layer in contact with a side surface of the second wiring, and a second insulating layer provided on the first insulating layer and having oxygen permeability lower than oxygen permeability of the first insulating layer.
Inventor(s): Masashi ARINO of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B41/27, H10B41/10, H10B43/10, H10B43/27
CPC Code(s): H10B41/27
Abstract: a semiconductor memory device includes: a stacked body including conductive layers and insulating layers alternately stacked on top of one another in a vertical direction; a first pillar including a semiconductor layer extending within the stacked body; and a separation layer penetrating through an uppermost one of the conductive layers, or the uppermost conductive layer and an another conductive layer coupled to the uppermost conductive layer in the vertical direction, extending within the stacked body in a first direction that intersects the vertical direction, and separating one or more conductive layers including the uppermost conductive layer in a second direction that intersects the vertical direction and the first direction. the separation layer includes at least a portion extending into the stacked body that is overlapped with the first pillar in the vertical direction, and having a lower end in contact with an upper surface of the first pillar.
Inventor(s): Seungkeun BAEK of Yokkaichi Mie (JP) for kioxia corporation, Teruhisa SONOHARA of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B41/27, H01L23/00, H01L25/18, H10B43/27, H10B80/00
CPC Code(s): H10B41/27
Abstract: a semiconductor device includes a stacked film, a plurality of plugs, and a columnar portion. the stacked film includes a plurality of electrodes, which includes a first electrode, and a plurality of first insulating films alternately stacked in a first direction. the plurality of plugs extends through the stacked film in the first direction. the plurality of plugs includes a first plug electrically connected to the first electrode. the columnar portion extends through the stacked film in the first direction. the columnar portion includes a charge storage layer and a semiconductor layer. the first electrode includes a metal layer and the first plug includes a metal layer that is integrally formed with the metal layer of the first electrode and formed of a same material as a material of the metal layer of the first electrode.
20240315019. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hideto TAKEKIDA of Nagoya Aichi (JP) for kioxia corporation, Yosuke MURAKAMI of Mie Mie (JP) for kioxia corporation, Keisuke NAKATSUKA of Kobe Hyogo (JP) for kioxia corporation, Yefei HAN of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/10, H10B43/20, H10B43/50
CPC Code(s): H10B43/10
Abstract: a semiconductor storage device of an embodiment includes a first conductive layer, a second conductive layer, a first conductive pillar, a first semiconductor layer, and a first storage layer. the first conductive layer extends in a first direction. the second conductive layer is along the first conductive layer in a third direction intersecting the first direction. the second conductive layer extends in the first direction. the first conductive pillar penetrates the first conductive layer and the second conductive layer in the third direction. the first semiconductor layer is in contact with the first conductive layer and the second conductive layer. the first semiconductor layer faces the first conductive pillar in the first direction. the first storage layer is between the first semiconductor layer and the first conductive pillar.
Inventor(s): Kazushi HARA of Inabe (JP) for kioxia corporation, Yefei HAN of Yokkaichi (JP) for kioxia corporation, Keisuke NAKATSUKA of Kobe (JP) for kioxia corporation, Koichi SAKATA of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L25/00, H01L25/065, H10B43/35
CPC Code(s): H10B43/27
Abstract: in one embodiment, a semiconductor device includes a stacked film including electrode layers and first insulators alternately in a first direction, a top layer of the stacked film being a second insulator that is one of the first insulators. the device further includes a columnar portion including a third insulator, a charge storage layer, a fourth insulator and a first semiconductor layer that are sequentially provided in the stacked film. the device further includes a metal layer provided on the stacked film and the columnar portion, electrically connected to the first semiconductor layer, and including one or more layers. an upper end of the columnar portion is provided at a height between upper and lower faces of the second insulator. a lower end of a highest layer among the one or more layers is provided at a position lower than the upper face of the second insulator.
20240315026. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Ayumi WATARAI of Ama (JP) for kioxia corporation, Kenji TASHIRO of Kuwana (JP) for kioxia corporation, Kosei NODA of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: according to one embodiment, in a semiconductor storage device, a plurality of second pillars each includes a first sub-pillar that is a single substance of a first insulating layer extending in the stacking direction in a lower layer side of a stacked body and a second sub-pillar arranged at a height position in an upper layer side of the stacked body to correspond to the first sub-pillar. the second sub-pillar includes a semiconductor layer extending in the stacking direction at the height position in the upper layer side of the stacked body, a second insulating layer covering a sidewall of the semiconductor layer, a third insulating layer covering a sidewall of the second insulating layer, and a fourth insulating layer that includes a different material from the second and third insulating layers and is interposed between the second and third insulating layers.
Inventor(s): Shin ISHIMATSU of Nagoya Aichi (JP) for kioxia corporation, Tatsunori ISOGAI of Yokkaichi Mie (JP) for kioxia corporation, Masaki NOGUCHI of Yokkaichi Mie (JP) for kioxia corporation, Hiroyuki YAMASHITA of Yokkaichi Mie (JP) for kioxia corporation, Wataru MATSUURA of Yokkaichi Mie (JP) for kioxia corporation, Daisuke NISHIDA of Mie Mie (JP) for kioxia corporation, Junichi KANEYAMA of Yokkaichi Mie (JP) for kioxia corporation, Tomoyuki TAKEMOTO of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H10B43/35, G11C16/04, H10B41/27, H10B41/35, H10B43/27
CPC Code(s): H10B43/35
Abstract: according to one embodiment, a semiconductor memory device includes a stacked film in which a plurality of silicon oxide layers, one of which having a film density of 2.3 g/cmor more, and a plurality of conductive layers, are alternately stacked in a first direction, and a memory pillar that penetrates the stacked film in the first direction, wherein a plurality of memory cells is provided in the memory pillar.
Inventor(s): Keita HASEGAWA of Yokkaichi (JP) for kioxia corporation, Keisuke NAKATSUKA of Kobe (JP) for kioxia corporation, Koichi SAKATA of Yokkaichi (JP) for kioxia corporation
IPC Code(s): H10B43/35, H01L23/522, H01L23/528, H01L25/065, H10B41/10, H10B41/27, H10B41/35, H10B41/41, H10B41/50, H10B43/10, H10B43/27, H10B43/40, H10B43/50
CPC Code(s): H10B43/35
Abstract: a semiconductor device includes a first chip including a peripheral circuit, and a second chip bonded to the first chip. the second chip includes a stacked body, a contact, a first column-shaped part, a second conductive layer, and a second column-shaped part. the contact is connected to a staircase part of the stacked body. the first column-shaped part is formed to extend through a memory part of the stacked body in a first direction and forms a memory cell transistor at an intersection part with a first conductive layer. the second conductive layer is formed above the stacked body and connected to an upper end part of the first column-shaped part. the second column-shaped part is formed to extend through the staircase part in the first direction. the second column-shaped part is electrically insulated from the second conductive layer.
Inventor(s): Kiwamu SAKUMA of Yokkaichi Mie (JP) for kioxia corporation, Takamasa HAMAI of Nagoya Aichi (JP) for kioxia corporation, Yuuichi KAMIMUTA of Seoul (KR) for kioxia corporation, Kunifumi SUZUKI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B51/20, H10B51/30
CPC Code(s): H10B51/20
Abstract: a semiconductor memory device has a stacked body in which a plurality of electrode layers and a plurality of insulating layers are alternately stacked in a first direction, an electrode film that extends in the stacked body in the first direction, and a plurality of ferroelectric films. each of the ferroelectric films is disposed between and in contact with one of the electrode layers and the electrode film, and has a thickness in the first direction that is greater than the electrode layer that is in contact therewith.
Inventor(s): Shosuke FUJII of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H10B51/30
CPC Code(s): H10B51/30
Abstract: a semiconductor memory device includes a ferroelectric memory transistor. the ferroelectric memory transistor includes a first conductive layer extending in a first direction and having a cylindrical shape and an upper surface that has a diameter r1, a first semiconductor layer extending in the first direction and having a cylindrical base portion in contact with the upper surface of the first conductive layer, the cylindrical base portion extending further in a radial direction than the upper surface of the first conductive layer such that a diameter r2 thereof is greater than the diameter r1, a ferroelectric layer extending in the first direction and surrounded by the first semiconductor layer, a second conductive layer extending in the first direction and surrounded by the ferroelectric layer, and a third conductive layer in contact with an outer periphery of the first semiconductor layer.
Inventor(s): Takuya SHIMANO of Seoul (KR) for kioxia corporation, Kenichi YOSHINO of Seongnam-si Gyeonggi-do (KR) for kioxia corporation, Kazuya SAWADA of Seoul (KR) for kioxia corporation, Naoki AKIYAMA of Seoul (KR) for kioxia corporation, Hyungjun CHO of Seoul (KR) for kioxia corporation
IPC Code(s): H10B61/00, H10N50/01, H10N50/20, H10N50/85
CPC Code(s): H10B61/10
Abstract: according to one embodiment, a magnetic memory device includes a switching element; a magnetoresistive effect element; and an electrode provided between the switching element and the magnetoresistive effect element, wherein the electrode includes a first sub-electrode in contact with the switching element, a second sub-electrode in contact with the magnetoresistive effect element, and a third sub-electrode provided between the first sub-electrode and the second sub-electrode, wherein the first sub-electrode and the second sub-electrode includes at least one of c and cn, and wherein the third sub-electrode includes at least one of a high melting point metal element and a compound of the high melting point metal element.
20240315052. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Daisaburo TAKASHIMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B63/00, H10B63/10
CPC Code(s): H10B63/845
Abstract: a semiconductor storage device includes a stacked body having a plurality of conductive layers stacked in a stacking direction with an insulating layer interposed therebetween, and a columnar structure that extends in the stacking direction in the stacked body. the columnar structure has a variable-resistance film, a semiconductor film, an insulating film, and a resistor film, all of which extend in the stacking direction in the stacked body. the semiconductor film is between the variable-resistance film and the conductive layer. the insulating film is between the semiconductor film and the conductive layer. the resistor film is between the variable-resistance film and the semiconductor film. memory cells are formed at locations where the conductive layers, the variable-resistance film, and the semiconductor film intersect. in each of the memory cells, the thickness of the resistor film is greater than the thickness of the variable-resistance film.
20240315058. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Go OIKE of Kuwana Mie (JP) for kioxia corporation, Kazuharu YAMABE of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B80/00, H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H10B80/00
Abstract: a semiconductor memory device includes a first cell chip and a second cell chip. the first cell chip includes a first stack, a first conductive layer that is used as a first source line, a second conductive layer that is electrically connected to the first conductive layer, and a plurality of first bonding pads. the second cell chip includes a second stack, a third conductive layer that is used as a second source line, a plurality of second bonding pads that are joined to the plurality of first bonding pads, respectively, and a fourth conductive layer that electrically couples the plurality of second bonding pads and is electrically connected to the third conductive layer. the second conductive layer and the fourth conductive layer are electrically connected.
20240315143. MAGNETIC MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hyung-Woo AHN of Seongnam-si Gyeonggi-do (KR) for kioxia corporation, Tadaaki OIKAWA of Seoul (KR) for kioxia corporation, Taiga ISODA of Tokyo (JP) for kioxia corporation, Kenji FUKUDA of Seoul (KR) for kioxia corporation, Ku Youl JUNG of Icheon-si (KR) for kioxia corporation
IPC Code(s): H10N50/10, G11C11/16, H10B61/00, H10N50/85
CPC Code(s): H10N50/10
Abstract: according to one embodiment, a magnetic memory device includes a memory cell. the memory cell includes a switching element, a magnetoresistance effect element, and an electrode that electrically couples the switching element to the magnetoresistance effect element. the electrode includes: a first non-magnetic layer being in contact with the switching element; and a second non-magnetic layer provided on a side opposite to a side on which the switching element is provided with respect to the first non-magnetic layer. the second non-magnetic layer has an amorphous structure and contains a metal oxide or a metal nitride.
Kioxia Corporation patent applications on September 19th, 2024
- Kioxia Corporation
- B08B3/14
- B08B1/00
- B08B1/04
- B08B3/02
- CPC B08B3/14
- Kioxia corporation
- B24B57/02
- B24B7/04
- B24B41/00
- B24B49/14
- CPC B24B57/02
- G01B15/04
- G06T7/00
- G06T7/543
- H10B80/00
- CPC G01B15/04
- G06F3/06
- CPC G06F3/0608
- CPC G06F3/061
- CPC G06F3/0655
- CPC G06F3/0658
- CPC G06F3/0659
- G06F11/10
- G06F11/07
- CPC G06F11/1016
- CPC G06F11/1068
- G06F12/02
- G11C16/04
- G11C16/26
- CPC G06F12/02
- CPC G06F12/0246
- G06F16/2452
- G06F11/34
- G06F16/2453
- CPC G06F16/24526
- G06T5/50
- G06T7/194
- G06V10/44
- G06V10/764
- G06V20/70
- CPC G06T7/0008
- G11C11/16
- CPC G11C11/1673
- G11C11/4074
- G11C11/4072
- G11C11/4096
- CPC G11C11/4074
- G11C11/408
- CPC G11C11/4096
- G11C11/56
- G11C16/08
- CPC G11C11/5671
- G11C11/54
- G11C16/34
- CPC G11C16/26
- G11C16/32
- H10B69/00
- CPC G11C16/32
- G11C7/04
- G11C16/10
- G11C16/20
- CPC G11C16/3495
- G11C29/52
- G11C29/02
- CPC G11C29/52
- H01J37/302
- G03F1/78
- H01J37/20
- H01J37/317
- CPC H01J37/3026
- H01L21/67
- C25B1/02
- C25D17/00
- H01L21/687
- CPC H01L21/67023
- H01J37/32
- H01L21/306
- H01L21/3065
- CPC H01L21/67069
- H01L21/311
- CPC H01L21/67086
- H01L21/677
- CPC H01L21/67167
- H01L21/68
- G03F7/00
- H01L21/66
- H01L23/00
- H01L21/683
- CPC H01L21/68
- H01L23/528
- H01L23/522
- H10B12/00
- CPC H01L23/5283
- H01L25/065
- CPC H01L25/0657
- H01L25/00
- H01L21/56
- H01L23/31
- H01L25/18
- CPC H01L25/50
- H02H9/04
- CPC H02H9/046
- H03K17/687
- H03K5/01
- CPC H03K17/6871
- H03K19/00
- H03K19/003
- H03K19/0185
- CPC H03K19/0005
- H03M13/29
- H03M13/11
- CPC H03M13/2909
- H05K1/11
- H01L23/498
- H05K1/18
- CPC H05K1/117
- CPC H10B12/33
- H10B41/27
- H10B41/10
- H10B43/10
- H10B43/27
- CPC H10B41/27
- H10B43/20
- H10B43/50
- CPC H10B43/10
- H10B43/35
- CPC H10B43/27
- H10B41/35
- CPC H10B43/35
- H10B41/41
- H10B41/50
- H10B43/40
- H10B51/20
- H10B51/30
- CPC H10B51/20
- CPC H10B51/30
- H10B61/00
- H10N50/01
- H10N50/20
- H10N50/85
- CPC H10B61/10
- H10B63/00
- H10B63/10
- CPC H10B63/845
- CPC H10B80/00
- H10N50/10
- CPC H10N50/10
