Kioxia Corporation patent applications on September 12th, 2024
Patent Applications by Kioxia Corporation on September 12th, 2024
Kioxia Corporation: 23 patent applications
Kioxia Corporation has applied for patents in the areas of G06F3/06 (5), H10B41/27 (5), H10B43/27 (5), H01L23/00 (4), G06F12/02 (4) G06F12/0246 (4), H10B43/27 (3), G06F3/0604 (1), H01L23/5283 (1), H10B12/33 (1)
With keywords such as: memory, layer, data, semiconductor, write, voltage, between, direction, line, and wiring in patent application abstracts.
Patent Applications by Kioxia Corporation
Inventor(s): Shizuka Sekigawa of Tokyo (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0604
Abstract: a memory system includes a non-volatile memory and a controller. the non-volatile memory includes at least one memory chip. the controller is electrically coupled to the non-volatile memory. the controller transmits a first instruction to the non-volatile memory, and transmits a second instruction to the non-volatile memory after transmitting the first instruction. the first instruction and the second instruction form a series of sequences. in a case where the non-volatile memory satisfies a condition, the second instruction is transmitted to the non-volatile memory after a first period following transmission of the first instruction elapses. in a case where the non-volatile memory does not satisfy the condition, the second instruction is transmitted to the non-volatile memory after a second period following transmission of the first instruction elapses. the second period is different from the first period.
Inventor(s): Mariko MATSUMOTO of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0607
Abstract: a memory system is connectable to a host. the memory system comprises a semiconductor memory and a memory controller electrically connected to the semiconductor memory. the memory controller, upon receiving a command from the host, the command instructing to update one or more of the plurality of firmwares stored in the first block, change at least one of a plurality of firmwares stored in any one of a plurality of slots of a first block, and change an active slot information stored in a first area of the first block.
20240302994. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Kenji SAKAUE of Yokohama Kanagawa (JP) for kioxia corporation, Yasuhiko KUROSAWA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: a memory system includes a nonvolatile memory, a memory controller, and a control circuit including a buffer and configured to store a first address transmitted by the memory controller in the buffer, generate a second address based on the first address stored in the buffer, and transmit the generated second address to the nonvolatile memory.
Inventor(s): Konosuke WATANABE of Kawasaki (JP) for kioxia corporation, Shinji YONEZAWA of Machida (JP) for kioxia corporation, Eiji SUKIGARA of Kawaguchi (JP) for kioxia corporation, Mitsusato HARA of Sagamihara (JP) for kioxia corporation, Haruka MORI of Kawasaki (JP) for kioxia corporation, Hajime YAMAZAKI of Kawasaki (JP) for kioxia corporation
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: according to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. the controller manages whether each of the nonvolatile memory chips is in a busy state or not. when one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. the controller executes a process in accordance with the identified first request.
20240303186. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Masayuki AKOU of Yokohama (JP) for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a semiconductor storage device according to an embodiment includes a first word line connected to a gate of a first memory cell transistor, a second word line connected to a gate of a second memory cell transistor, a first word line selection transistor capable of supplying a voltage from a voltage supply circuit to the first word line, a second word line selection transistor capable of supplying the voltage from the voltage supply circuit to the second word line, an insulating film provided between the first word line selection transistor and the second word line selection transistor, and a first wiring having at least a part provided on the insulating film and extending in a first direction, in which the voltage supply circuit is capable of supplying a first voltage lower than a ground voltage to the first wiring.
20240303188. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Takashi TAKEMOTO of Yokohama Kanagawa (JP) for kioxia corporation, Kensaku YAMAGUCHI of Kawasaki Kanagawa (JP) for kioxia corporation, Keiri NAKANISHI of Kawasaki Kanagawa (JP) for kioxia corporation, Kohei OIKAWA of Kawasaki Kanagawa (JP) for kioxia corporation, Sho KODAMA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: a memory system includes a nonvolatile memory and a controller. the controller is configured to maintain an address mapping table including first mapping information indicating correspondence between logical addresses and physical addresses of the nonvolatile memory in units of physical regions each having a predetermined size. the controller, during a write operation compresses write data of the predetermined size into a compressed write data, determines a physical address range in which the compressed write data is to be written, writes the compressed write data into the physical address range and also second mapping information into an area in one or more physical regions spanned by the physical address range, and updates the address mapping table. the second mapping information indicates a logical address of the write data, an information capable of specifying an offset, and a size of the compressed write data.
20240303189. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Koichi NAGAI of Ota Tokyo (JP) for kioxia corporation
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0246
Abstract: according to one embodiment, a controller, in response to receiving, from a host, a first command requesting secure erase of secure erase target data associated with a first logical area identifier, stores a copy of first mapping information that corresponds to the first logical area identifier, among mapping information that is included in a first table. the controller executes at least a data erase operation for one or more first blocks storing the secure erase target data. in a first mode, the controller, in response to receiving, from the host, a read command that specifies the first logical area identifier, reads data from a storage location corresponding to a first physical address that is mapped to the first logical area identifier in the copy of the first mapping information.
Inventor(s): Daisuke HASHIMOTO of Cupertino CA (US) for kioxia corporation
IPC Code(s): G06F12/02, G06F3/06, G06F11/14
CPC Code(s): G06F12/0246
Abstract: a storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. the processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. the controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. the processor is further configured to generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.
20240304229. MEMORY SYSTEM_simplified_abstract_(kioxia corporation)
Inventor(s): Takaya YASUDA of Kawasaki Kanagawa (JP) for kioxia corporation, Kosuke HATSUDA of Bunkyo Tokyo (JP) for kioxia corporation
IPC Code(s): G11C11/16
CPC Code(s): G11C11/1675
Abstract: a memory system includes a first wiring, a second wiring, a memory cell between the first and second wirings, a first power supply line configured to supply a first voltage, a first transistor between the first power supply line and the first wiring, and configured to supply a current necessary to perform a write operation to the memory cell, a second transistor arranged between the first power supply line and the first wiring, and connected in parallel with the first transistor, a second power supply line configured to supply a second voltage to the second wiring corresponding to the memory cell unselected in the write operation, and a first current copy circuit configured to copy a current flowing to the second power supply line from the second wiring corresponding to the memory cell unselected in the write operation, and configured to control the second transistor based on a copied current.
Inventor(s): Tomoya SANUKI of Yokkaichi Mie (JP) for kioxia corporation, Yasuhito YOSHIMIZU of Kawasaki Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C11/4096, G11C11/4074, G11C11/408
CPC Code(s): G11C11/4096
Abstract: a memory device includes a bit line, a source line, a first string in which a plurality of first memory cells are connected in series between the bit line and the source line, and a control circuit. the control circuit performs a sense operation for a search operation to determine if search data is stored in the plurality of first memory cells by supplying voltages to a plurality of word lines respectively corresponding to the plurality of first memory cells based on the search data and determining a similarity between the search data and data actually stored in the plurality of first memory cells based on a change in voltage of the bit line caused by current flowing between the bit line and the source line via the first string.
20240304245. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Kazutaka IKEGAMI of Inagi Tokyo (JP) for kioxia corporation
IPC Code(s): G11C16/04, G11C16/10, G11C16/26, G11C16/34
CPC Code(s): G11C16/0483
Abstract: a semiconductor memory device includes bit lines, memory cells that are respectively connected to the bit lines, sense amplifier units that are respectively connected to the bit lines, and each of which includes m latch circuits, and a logic control circuit configured to input data to the m latch circuits and control a write operation on each of the memory cells using the data input to the m latch circuits. the logic control circuit executes an operation to write n bits to each of the memory cells, where n is 2 or more and greater than m, by executing a plurality of write operations, including a first write operation executed on the memory cells by inputting first m bits of data to the m latch circuits, and a second write operation executed on the memory cells by inputting second m bits of data to the m latch circuits.
20240304257. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yuki INUZUKA of Yokohama Kanagawa (JP) for kioxia corporation, Hidehiro SHIGA of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): G11C16/16, G11C16/04, G11C16/08, H10B41/10, H10B41/27, H10B41/35, H10B41/50, H10B43/10, H10B43/27, H10B43/35, H10B43/50
CPC Code(s): G11C16/16
Abstract: a semiconductor memory device includes first and second semiconductor pillars, a first string including first memory cells connected in series and a second string including second memory cells connected in series on opposite sides of the first semiconductor pillar, respectively, a third string including third memory cells connected in series and a fourth string including fourth memory cells connected in series, on opposite sides of the second semiconductor pillar, respectively, first word lines, second word lines, and a driver configured to supply different voltages to the first and second word lines during an erasing operation to erase data in the second and fourth memory cells. in the erasing operation, the driver supplies a first voltage higher than a reference voltage to the first word lines, and supplies the reference voltage to the second word lines.
Inventor(s): Mariko SUMIYA of Yokkaichi Mie (JP) for kioxia corporation, Mie MATSUO of Kamakura Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L21/762, B23K26/03, B23K26/08, H01L21/18, H01L21/268, H01L21/683, H01L21/8238
CPC Code(s): H01L21/76259
Abstract: a method of manufacturing a semiconductor device includes forming a bonded substrate including an effective chip area by bonding a first chip including a first device layer on a first substrate via a porous layer and a second chip including a second device layer on a second substrate, irradiating the porous layer in an ineffective chip area surrounding the effective chip area of the bonded substrate with laser light from the first substrate side, and separating the first substrate from the bonded substrate from the porous layer in the ineffective chip area.
20240304548. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Toru NAKANISHI of Yokohama Kanagawa (JP) for kioxia corporation, Fumitaka ARAI of Yokohama Kanagawa (JP) for kioxia corporation, Kouji MATSUO of Ama Aichi (JP) for kioxia corporation
IPC Code(s): H01L23/528, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): H01L23/5283
Abstract: a semiconductor memory device of the embodiment includes first to fourth gate electrode layers which extend in a first direction, a first semiconductor layer which extends in a second direction intersecting the first direction and is provided between the first gate electrode layer and the third gate electrode layer, and between the second gate electrode layer and the fourth gate electrode layer, a first wiring layer which extends in a third direction intersecting the first direction and the second direction and is electrically connected to the first gate electrode layer, a second wiring layer which is electrically connected to the second gate electrode layer, a third wiring layer which extends in the third direction and is electrically connected to the third gate electrode layer, and a fourth wiring layer which extends in the third direction and is electrically connected to the fourth gate electrode layer. the first wiring layer is provided between the third wiring layer and the fourth wiring layer, and the second wiring layer is provided between the first wiring layer and the fourth wiring layer.
20240304576. SEMICONDUCTOR DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Yuya KIYOMURA of Kuwana Mie (JP) for kioxia corporation, Ayako KAWANISHI of Yokkaichi Mie (JP) for kioxia corporation, Yuta TAGUCHI of Yokkaichi Mie (JP) for kioxia corporation, Ayumi WATARAI of Ama Aichi (JP) for kioxia corporation, Ippei KUME of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H01L23/00, H01L25/18, H10B80/00
CPC Code(s): H01L24/05
Abstract: a memory device includes a first chip including a first electrode and a second chip including a second electrode. the first electrode includes a first conductive film having a first surface in contact with the second electrode at a boundary region of the first and second electrodes, a second surface spaced apart from the boundary region, and a third surface between the first surface and the second surface, and having a first portion on the first surface side and a second portion on the second surface side, and includes a second conductive film covering the second surface and the third surface of the first conductive film. a (111) orientation ratio of copper contained in the first portion is higher than a (111) orientation ratio of copper contained in the second portion.
20240304602. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Tomoya SANUKI of Yokkaichi (JP) for kioxia corporation, Hiroshi MAEJIMA of Tokyo (JP) for kioxia corporation, Tetsuaki UTSUMI of Yokohama (JP) for kioxia corporation
IPC Code(s): H01L25/065, H01L23/00, H01L25/18
CPC Code(s): H01L25/0657
Abstract: according to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. the memory cell is provided above a substrate. the first voltage generator is provided between the substrate and the memory cell. the first voltage generator is configured to generate a first voltage to be supplied to the memory cell. the second voltage generator is provided between the substrate and the memory cell. the second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.
Inventor(s): Kazuma HASEGAWA of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): H01L25/10, H01L23/00, H01L23/31, H10B80/00
CPC Code(s): H01L25/105
Abstract: a semiconductor device includes a substrate that includes a first surface, a first semiconductor chip that includes a second surface facing the first surface of the substrate and a third surface opposite to the second surface, each of the second and third surfaces having a rectangular shape that includes a plurality of sides and has surface areas that are different, and a second semiconductor chip disposed on the first surface of the substrate on one side of the first semiconductor chip. when viewed in a first direction substantially perpendicular to the substrate, one of the sides of the third surface that is closest to the second semiconductor chip overlaps an interior portion of the second semiconductor chip.
Inventor(s): Toshifumi WATANABE of Yokohama (JP) for kioxia corporation, Kiyofumi SAKURAI of Yokohama (JP) for kioxia corporation, Teppei HIGASHITSUJI of Fujisawa (JP) for kioxia corporation, Takumi KOSAKI of Kamakura (JP) for kioxia corporation, Eiji KOZUKA of Chuo (JP) for kioxia corporation
IPC Code(s): H03K3/356, G11C16/04, G11C16/26, G11C16/30
CPC Code(s): H03K3/356017
Abstract: a data latch circuit according to embodiments described herein includes a first circuit and a second circuit. the first circuit has a first transistor with a first conductivity type and a second transistor with a second conductivity type that differs from the first conductivity type being connected in series and stores a first logical value. the second circuit has a third transistor with the first conductivity type and a fourth transistor with the second conductivity type being connected in series and stores a second logical value being an inversion of the first logical value. the data latch circuit enables one of a first voltage and a second voltage that differs from the first voltage to be applied to back gates of the first transistor and the third transistor and enables a third voltage to be applied to sources of the first transistor and the third transistor.
Inventor(s): Takeru MAEDA of Yokkaichi Mie (JP) for kioxia corporation, Kotaro NODA of Yokkaichi Mie (JP) for kioxia corporation, Shosuke FUJII of Kuwana Mie (JP) for kioxia corporation
IPC Code(s): H10B12/00
CPC Code(s): H10B12/33
Abstract: a semiconductor device includes a semiconductor substrate, a memory capacitor provided on the semiconductor substrate, a first conductor provided above the memory capacitor and extending in a first direction, a second conductor provided above the first conductor and extending in the first direction, an oxide semiconductor layer provided between the first conductor and the second conductor and extending in the first direction, a conductive oxide layer between the second conductor and the oxide semiconductor layer, a first conductive layer between the conductive oxide layer and the second conductor, and an insulating layer in contact with the conductive oxide layer, wherein a portion of the conductive oxide layer is between and aligned with the first insulating layer and the oxide semiconductor layer in the first direction.
20240306388. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Hiroshi NAKAKI of Yokkaichi Mie (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L23/00, H01L25/065, H01L25/18, H10B41/27, H10B80/00
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes a stacked body, a plurality of columnar bodies, a plurality of bit lines, a plurality of contacts, and a plurality of dividing portions. the plurality of dividing portions is located separately in the third direction, each extending in the first direction in the stacked body, and dividing one or more gate electrode layers including the lowermost layer of the plurality of gate electrode layers in the third direction, when the one side is the lower side. the plurality of columnar bodies includes five columnar bodies provided in a region between two adjacent dividing portions among the plurality of dividing portions. regarding each columnar body provided in the five columnar bodies, a separate bit line provided in the plurality of bit lines is present between a bit line provided in the plurality of bit lines and electrically connected to the columnar body, and each bit line provided in the plurality of bit lines and electrically connected to a columnar body adjacent to that columnar body at the shortest interval among the five columnar bodies.
20240306390. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Shinya NAITO of Toyota Aichi (JP) for kioxia corporation, Takayuki KAKEGAWA of Yokkaichi Mie (JP) for kioxia corporation, Kenji KAWABATA of Yokkaichi Mie (JP) for kioxia corporation, Eri SAHARA of Nagoya Aichi (JP) for kioxia corporation
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: a semiconductor storage device includes a substrate, a wiring layer region on the substrate, a stacked body on the wiring layer region and in which conductive layers and insulating layers are alternately stacked in a first direction, and a columnar portion that includes a semiconductor body extending in the first direction through the stacked body and into the wiring layer region and a charge storage film surrounding the semiconductor body. the columnar portion includes a first columnar portion positioned at an end portion of the stacked body, a second columnar portion in the wiring layer region, and a connection portion between the first and second columnar portions. the semiconductor body in the connection portion has a first portion extending in a second direction, and the charge storage film in the connection portion has a second portion extending in the second direction and covers the first portion in the first direction.
20240306393. SEMICONDUCTOR MEMORY DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Toshifumi MINAMI of Yokohama Kanagawa (JP) for kioxia corporation, Atsuhiro SATO of Meguro Tokyo (JP) for kioxia corporation, Keisuke YONEHAMA of Kamakura Kanagawa (JP) for kioxia corporation, Yasuyuki BABA of Zama Kanagawa (JP) for kioxia corporation, Hiroshi SHINOHARA of Yokosuka Kanawaga (JP) for kioxia corporation, Hideyuki KAMATA of Kawasaki Kanagawa (JP) for kioxia corporation, Teppei HIGASHITSUJI of Fujisawa Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B43/27, H01L29/792, H10B41/20, H10B41/27, H10B43/00, H10B43/10, H10B43/20, H10B43/35
CPC Code(s): H10B43/27
Abstract: a semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. a surface of the plate, which faces the pillars, has convex portions and non-convex portions.
20240306405. SEMICONDUCTOR STORAGE DEVICE_simplified_abstract_(kioxia corporation)
Inventor(s): Junichi SATO of Yokohama Kanagawa (JP) for kioxia corporation, Kazuto UEHARA of Sagamihara Kanagawa (JP) for kioxia corporation, Yuuta SANO of Yokosuka Kanagawa (JP) for kioxia corporation, Yoshihiro SAEKI of Yokohama Kanagawa (JP) for kioxia corporation
IPC Code(s): H10B80/00, H01L25/065
CPC Code(s): H10B80/00
Abstract: a semiconductor storage device comprises a memory chip including first and second control signal pads to which first and second control signals are to be input, respectively, a data signal pad to and from which a data signal is to be input and output, and a control circuit. the control circuit stores data in the data signal in a data register, when the first and second control signals are at a first state, stores data in the data signal in a command register, when the first control signal is at a second state and the second control signal is at the first state, stores data in the data signal in an address register, when the first control signal is at the first state and the second control signal is at the second state, and outputs status data when the first and second control signals are at the second state.
Kioxia Corporation patent applications on September 12th, 2024
- Kioxia Corporation
- G06F3/06
- CPC G06F3/0604
- Kioxia corporation
- CPC G06F3/0607
- CPC G06F3/0656
- CPC G06F3/0659
- G06F12/02
- CPC G06F12/0246
- G06F11/14
- G11C11/16
- CPC G11C11/1675
- G11C11/4096
- G11C11/4074
- G11C11/408
- CPC G11C11/4096
- G11C16/04
- G11C16/10
- G11C16/26
- G11C16/34
- CPC G11C16/0483
- G11C16/16
- G11C16/08
- H10B41/10
- H10B41/27
- H10B41/35
- H10B41/50
- H10B43/10
- H10B43/27
- H10B43/35
- H10B43/50
- CPC G11C16/16
- H01L21/762
- B23K26/03
- B23K26/08
- H01L21/18
- H01L21/268
- H01L21/683
- H01L21/8238
- CPC H01L21/76259
- H01L23/528
- CPC H01L23/5283
- H01L23/00
- H01L25/18
- H10B80/00
- CPC H01L24/05
- H01L25/065
- CPC H01L25/0657
- H01L25/10
- H01L23/31
- CPC H01L25/105
- H03K3/356
- G11C16/30
- CPC H03K3/356017
- H10B12/00
- CPC H10B12/33
- CPC H10B43/27
- H01L29/792
- H10B41/20
- H10B43/00
- H10B43/20
- CPC H10B80/00
